A 320 MFLOPS CMOS floating-point processing unit for superscalar processors
N Ide, H Fukuhisa, Y Kondo, T Yoshida… - IEEE Journal of Solid …, 1993 - ieeexplore.ieee.org
A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is
described. It is fabricated using a 0.5 mu m CMOS triple-metal-layer technology on a 61
mm/sup 2/die. The FPU has two execution modes to meet precise scientific computations
and real-time applications. It can start two FPU operations in each cycle, and this achieves a
peak performance of 160 MFLOPS double or single precision with an 80 MHz clock.
Furthermore, the original computation mode, twin single-precision computation, double the …
described. It is fabricated using a 0.5 mu m CMOS triple-metal-layer technology on a 61
mm/sup 2/die. The FPU has two execution modes to meet precise scientific computations
and real-time applications. It can start two FPU operations in each cycle, and this achieves a
peak performance of 160 MFLOPS double or single precision with an 80 MHz clock.
Furthermore, the original computation mode, twin single-precision computation, double the …
この検索の最上位の結果を表示しています。 検索結果をすべて見る