[PDF][PDF] TI introduces four-processor DSP chip
CP Feigel - Microprocessor report, 1994 - cecs.uci.edu
CP Feigel
Microprocessor report, 1994•cecs.uci.eduFigure 1. The 320C80's four DSPs and its RISC master processor all share the chip's on-
board RAM via a crossbar switch. The transfer controller (TC) acts as an intelligent DMA
controller, servicing access requests to external memory space. The Frame Controllers (FC)
handle raster-format data.
board RAM via a crossbar switch. The transfer controller (TC) acts as an intelligent DMA
controller, servicing access requests to external memory space. The Frame Controllers (FC)
handle raster-format data.
Figure 1. The 320C80’s four DSPs and its RISC master processor all share the chip’s on-board RAM via a crossbar switch. The transfer controller (TC) acts as an intelligent DMA controller, servicing access requests to external memory space. The Frame Controllers (FC) handle raster-format data.
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