Systolic architecture for finite field exponentiation
A Ghafoor, A Singh - IEE Proceedings E (Computers and Digital Techniques …, 1989 - IET
A Ghafoor, A Singh
IEE Proceedings E (Computers and Digital Techniques), 1989•IETA systolic pipline architecture which can perform exponentiation function in a concurrent
environment is presented. This function is computed in Galois fields. Under a steady-state
condition the throughput of the architecture is shown to be the maximum, with the results
appearing at every clock cycle. Being systolic in nature, the architecture is amenable to easy
implementation in VLSI.
environment is presented. This function is computed in Galois fields. Under a steady-state
condition the throughput of the architecture is shown to be the maximum, with the results
appearing at every clock cycle. Being systolic in nature, the architecture is amenable to easy
implementation in VLSI.
A systolic pipline architecture which can perform exponentiation function in a concurrent environment is presented. This function is computed in Galois fields. Under a steady-state condition the throughput of the architecture is shown to be the maximum, with the results appearing at every clock cycle. Being systolic in nature, the architecture is amenable to easy implementation in VLSI.
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