James E. Smith Astronautics Corporation of America ipelined instruction processing has become a widely used technique for implementing high-performance computers. Pipelining first appeared in supercomputers and large maiiiframes, but can now be found in less expensive systems. For example, most of the recent reduced instruction set computers use pipelining.’.’Indeed, a major argument for RISC architectures is the ease with which they can be pipelined. At the other end of the spectrum, computers with more complex instruction sets, such as the VAX 8800,’make effective use of pipelining as well.

The ordering, or “scheduling,” of instructions as they enter and pass through an instruction pipeline is a critical factor in determining performance. In recent years, the RISC philosophy has become pervasive in computer design. The basic reasoning behind the RISC philosophy can be stated as “simple hardware means faster hardware, and hardware can be kept simple by doing as much as possible in software.” A corollary naturally follows, stating that instruction scheduling should be done by software at compile time. We refer to this as static instruction scheduling, and virtually every new computer system announced in the last several years has followed this approach.