Architectural features of the i860-microprocessor RISC core and on-chip caches
P Patel, D Douglass - … Conference on Computer Design: VLSI in …, 1989 - ieeexplore.ieee.org
P Patel, D Douglass
Proceedings 1989 IEEE International Conference on Computer Design …, 1989•ieeexplore.ieee.orgThe Intel i860 is a one-million-transistor, high-performance RISC (reduced-instruction-set
computer) microprocessor. The performance of the i860 CPU is derived using
supercomputer architectural concepts such as parallel instruction execution and a 64-b
architecture that provides the data and instruction bandwidth necessary to support multiple
operations. The novel features of the i860 RISC integer core are explored. The on-chip
cache architecture, which is optimized for large data and instruction bandwidth, is …
computer) microprocessor. The performance of the i860 CPU is derived using
supercomputer architectural concepts such as parallel instruction execution and a 64-b
architecture that provides the data and instruction bandwidth necessary to support multiple
operations. The novel features of the i860 RISC integer core are explored. The on-chip
cache architecture, which is optimized for large data and instruction bandwidth, is …
The Intel i860 is a one-million-transistor, high-performance RISC (reduced-instruction-set computer) microprocessor. The performance of the i860 CPU is derived using supercomputer architectural concepts such as parallel instruction execution and a 64-b architecture that provides the data and instruction bandwidth necessary to support multiple operations. The novel features of the i860 RISC integer core are explored. The on-chip cache architecture, which is optimized for large data and instruction bandwidth, is described.<>
ieeexplore.ieee.org
この検索の最上位の結果を表示しています。 検索結果をすべて見る