JPS59139448A - Floating-point multiplying device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a floating-point multiplication device, particularly to a floating-point multiplication device that performs high-speed calculations on the exponent part in floating-point multiplication that conforms to the IEEE standard format, and quickly obtains overflow and underflow detection signals. The present invention relates to a floating point multiplication device.

Conventional configuration and its problems In the exponent part calculation of a floating point multiplier, the exponent part is generally added, and then this addition is performed again after the shift signal for normalization generated by the mantissa part calculation arrives. After that, overflow and underflow detection is performed.1J The exponent unit of a conventional floating point multiplication device will be described below with reference to FIG. In Fig. 1, 1 is an exponent adder that adds the exponent part Ex of the multiplicand to the exponent part Ey of the multiplicand, and 2 is the exponent part adder that is generated by multiplying the mantissa part x of the multiplicand by the mantissa part MY of the multiplicand. +1 for normalization
Addition signal line, 3 is +1 according to the signal of addition signal line 2
or +1 adder that adds +○ to the output of exponent part adder 1; 4 is a detector that compares the output of +1 adder 3 with a predetermined value to detect overflow or underflow of the multiplication result; 5 , 6 are an underflow detection signal line and an overflow detection signal line output from the detector 4, respectively. The conventional exponent part calculator as shown in Fig. 1 is E
After x and E7 are added, the exponent part calculation is completed after waiting for the arrival of a +1 addition signal for normalization obtained by the mantissa part calculation. Detection of overflow and underflow is performed after the exponent part calculation is completely completed. Generally, in floating point multiplication, the exponent part calculation is performed after the mantissa part calculation is completed, so that the overall multiplication time can be shortened by shortening the exponent part calculation time.

However, in the above example, the +1 addition is performed after the exponent part normalization signal (corresponding to the +1 addition signal) arrives,
Since overflow and underflow detection is performed using this output, a relatively long time is required from the end of the mantissa operation until the entire multiplication result is obtained, which is undesirable for performing floating point multiplication at high speed.

Purpose of the Invention In view of such conventional problems, the present invention provides a floating point system which can minimize the time required from the arrival of the exponent part normalized signal obtained by the exponent part calculation to the end of the exponent part processing. The purpose is to provide a multiplication device.

Structure of the Invention The present invention provides a first sum of an exponent part of a multiplier, an exponent part of a multiplicand, and a predetermined constant, a second sum obtained by adding 1 to this sum, and a specific value of the two sums. By preparing a detection signal for detecting the exponent part normalization signal, the exponent part calculation result can be obtained immediately after the arrival of the exponent part normalized signal.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows the configuration of an exponent unit of a multiplier that performs floating point multiplication based on the IEEE standard format in an embodiment of the present invention. It is assumed that the exponent part has a data width of 8 pits. In Figure 2, 11 is the exponent part Ex of the multiplier, the exponent part Ey of the multiplicand, and 81 (hereinafter 81H) in hexadecimal notation.
12 is a 10-bit wide adder that adds 1 to the output of adder 11; 13 is a high logic level when exponent normalization is required as a result of mantissa multiplication; The signal line 14 is set to a low logic level (hereinafter abbreviated as "L") and the output of the adder 11 is 100H, or the upper two bits are 00.
The underlow detector 15 outputs an underlow detection signal line to the signal line 16 when is 1FFH, signal line 17
16 is an underflow detection signal line, 17 is an overflow detection signal line, 18 is an overflow detector that outputs an overflow detection signal to when the signal line 13 is H1+, and an adder when it is I+. This is a selector that outputs 11 outputs.

Single precision floating point data in the IEEE standard format is SE-127 (-1)・2・(1・F)...
・It has the form (1). In this equation, S is sign pitch 1, E is 8-bit exponent data shifted in the positive direction by 1'27 (7F H), F is 23-bit mantissa data, and overflow occurs. is, 128≦(E-127)...
The underflow is defined as (E-127)≦-127... 1, FX) - (
4) Y=(-1)8y・2 E y 127・(1,F
y) (5), the multiplication result P is expressed as the following equation.

p=x@y=(-j)Sx+Sy, 2(Ex+Ey-127,
)-127, (1, FX), (1, FyT=(-1)8
P・2EP-127・(1,FP) ・・・・・・
(6) (In the @ expression, ■ represents exclusive OR. The mantissa (1, F) is in the range 1≦(1, F) < 2, so the product of the mantissas of X and Y is 1 ≦(1,Fx), (1,Fy)<4, and in the range 2≦(1,Fx), (1,Fy)<4, it is necessary to perform normalization and add 1 to the exponent part. The signal line that propagates this signal is the signal line 13. On the other hand, the calculation of EP is 12 by expressing -127 as a complement.
It is obtained in the adder 11 by adding 9 (81H) to Ex+Ey. Depending on the multiplication result of the mantissa, it is necessary to further add 1 as described above, and this result is obtained in the adder 12. The calculation result of the exponent part is on signal line 1
When the signal of No. 3 is "Hu", it is output from the adder 12, and when it is L11, it is output from the adder 11 via the selector 18.

The overflow is Ep≧128+ from (Gong expression and (@ expression)
2, 127+1291=511 (I F FH)・
(This is the range of power. In other words, if EP is a number with a width of 10 bits, an overflow will occur if EP is 1FFH or the most significant bit of EP is 1. This is due to the following two items a, (a) When the signal on the signal line 13 is “L”, the output of the adder 12 is 512 (200H) or more. That is, the most significant bit of the output of the adder 12 is 1° (y). When the signal is "H", the output of the adder 12 is 511 (IFFH) or more. That is, the most significant bit of the output of the adder 12 is 1, or the lower 9 bits are detected by the 1FFH0 detector 15.

The underflow is EP≦−127 from the (grape formula and (6 formula)
+2.127+129=256(10C)H). In other words, Ep is 100H or the top 2 of Ep
If the bit is oo, an underflow occurs. This is equivalent to the following two items (C) and (d), and <d) When the signal on the signal line 13 is “HI+”, the output of the adder 11 is 2
56 (FFH) or less. In other words, if the high-order 2 bits of the output of the adder 11 are 00° (→ If the signal on the signal line 14 is "°I L l", the output of the adder 11 is 256 (100H) or less. In other words, the output of the adder 11 is 100H. Alternatively, the upper two bits are detected by the 00° detector 14. The detector 14 and the detector 15 can be realized by a logic circuit as shown in FIG. 2, for example.

As described above, according to this embodiment, the adder 11 and the adder 12 are each set to have a width of 10 pits, and by effectively using the signals of the upper two bits of each adder 11 and adder 12, the normalized signal is immediately inputted. Exponent data, overflow, and underflow can be detected.

In this embodiment, the predetermined constant for multiplication in the IEEE standard format is 81H, but it is possible to realize a configuration similar to this embodiment by setting a predetermined constant for multiplication in formats other than the IEEE format. it is obvious.

Furthermore, in this embodiment, two sum outputs are obtained by an adder and an incrementer that add Ex, Ep, and 81H, but two sum outputs are obtained by an adder and a decrementer that add Ex, EV, and 82H. It is clear that it is possible to obtain two identical sum outputs.

Effects of the Invention As described above, the present invention provides two outputs that can be solutions to the exponent part of the multiplication result in a floating-point multiplication device,
By providing a detector that detects each specific value, an excellent floating-point multiplication that can quickly obtain the exponential part output and overflow/underflow detection signal after the arrival of the normalized signal resulting from the mantissa operation. It is possible to realize a vessel.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional exponent part calculator, and FIG. 2 is a block diagram of an exponent part calculator in an embodiment of the present invention. 11.12...Adder, 13...Normalization signal line, 14...Underflow detector, 1
6... Overflow detector. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure ρVF (JDF

Claims (1)

[Claims] (1) Input the n-bit length exponent part of the multiplier and the n-bit length exponent part of the multiplicand, and input the n+2-bit exponent part that is the sum of the exponent part of the multiplier, the exponent part of the multiplicand, and a predetermined constant. the sum of 1 and n + 2 which is 1 greater than the first sum
first means for outputting a second sum of bits;
The upper two bits of the sum output are 00, or the most significant bit of the multiplication result of the mantissa part of the multiplier and the multiplicand is 0, and the upper two bits of the first sum output are 01, and the lower a first detector that generates an under 70-detection signal when all n pits are 0, and the most significant bit of the multiplication result of the mantissa part of the multiplicand and the multiplicand is 1;
and when the lower n-1-1 pits of the second sum output are all 1, or when the most significant bit of the second sum output is 1, a second sum output signal generating an overflow detection signal; When the most significant bit of the multiplication result of the mantissa part of the multiplier and the multiplicand is 0, the lower n bits of the first sum output are used as the exponent, and when it is 1, the lower n pits of the second sum output are used as the exponent. and a selector that outputs a partial result. Floating point multiplication device according to claim 1, characterized in that the first means comprises an adder and an incrementer whose input is the output of the adder. 2. The floating point multiplication device according to claim 1, wherein the first means comprises an adder and a decrementer whose input is the output of the adder. (2n-1+1) The floating-point multiplication device according to claim 2 or 3, characterized in that the number is (2n-1+1).