Kumar et al., 2013 - Google Patents

Simulation and synthesis of 32-bit multiplier using configurable devices

Kumar et al., 2013

Document ID
11114947605936148728
Author
Kumar D
Lall G
Publication year
Publication venue
International Journal of Advances in Engineering & Technology

External Links

Snippet

Floating-point numbers are frequently used for numerical calculations in computing systems for better accuracy, but floating-point operations are complex and difficult to design on FPGAs. This work attempts to design such hardware architecture for single precision floating …
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Classifications

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    • G06F7/52—Multiplying; Dividing
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