JPH0850575A - Programmable processor,method for execution of digital signal processing by using said programmable processor and its improvement - Google Patents

Abstract

PURPOSE: To provide a space vector data path which integrates SIMD schemes to a general purpose programmable processor. CONSTITUTION: A programmable processor includes a mode means which is connected to an instruction means and specifies whether or not an operand is processed for each instruction in one of vector and scalar modes and a processing unit 110 which is connected to the mode means, receives the operand and processes the operand in one of the vector and scalar modes in response to an instruction such that is specified by the mode means. The vector mode shows the processing unit 110 that plural elements exist in the operand and the scalar mode shows the processing unit 110 that a single element exists in the operand.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to signal processors, and more particularly to digital signal processors with spatial parallel processing capability.

[0002]

In recent years, in computer technology, computers having parallel processing schemes such as single instruction multiple data (SIMD) have been gradually gaining recognition. The SIMD computer can be conceptually shown in FIG. 1 (a), where a plurality of processing elements (PEs) are monitored by one main sequencer. All PEs receive the same instructions communicated from the main sequencer, but operate on different sets of data from separate data streams. As shown in FIG. 1 (b), each PE functions as a central processing unit (CPU) having its own local memory. Therefore, SIM
The D-computer can achieve spatial parallelism by using multiple synchronized arithmetic logic units with each PE's CPU. Once the data is within each PE, it is relatively easy for an individual PE to handle the data, but across all PEs via interconnections (not shown). Distributing and communicating is a highly complex task. Therefore, SIM
D-machines are usually designed to be dedicated, and programming and vectorization difficulties make these machines undesirable for general purpose applications.

On the other hand, SPARC (registered trademark), Pow
Current general purpose computers such as erPC® and 68000 based machines typically do not fully utilize their 32-bit memory space for high performance graphics processing. For example, while the buses of these machines are 32 bits wide, for video and image information the data is still limited to being processed at 16 bit widths or 8 bit pixels. However, these general purpose machines are attractive because of the convenience of programming in a high level language software environment. Therefore, it is desirable to balance the speed advantages of SIMD as applied to digital signal processing with the programming convenience of general purpose CPUs. Then, even if a low-performance SIMD machine is implemented, if it is incorporated into a general-purpose machine, the overall throughput will be significantly improved as if a plurality of scalar CPUs are working in parallel. Let's do it. However, when SIMD is integrated into a general-purpose machine, the increased throughput comes at the expense of using silicon, typically associated with the multi-unit scalar CPU found in traditional SIMD machines. Absent.

Therefore, it would be desirable to have a general purpose processor with SIMD capabilities for code enhancement applications and speed enhancement computations.

An object of the present invention is to use the SIMD system as a general purpose CP.
Incorporation into the U architecture to increase throughput.

It is also an object of the present invention to increase throughput without substantially incurring the use of silicon.

A further object of the invention is to increase throughput in proportion to the number of data elements processed in each instruction at the same instruction execution speed.

[0008]

SUMMARY OF THE INVENTION A space vector data path for incorporating a SIMD scheme into a general purpose programmable processor is disclosed. The programmable processor is coupled to the instruction means and is coupled to the mode means for identifying for each instruction whether the operand is processed in one of the vector and scalar modes, and coupled to the mode means for receiving the operands and by the mode means. A processing unit for processing the operand in one of a vector and a scalar mode in response to the identified instruction, the vector mode indicating that the processing unit has multiple elements in the operand, Scalar mode indicates to the processing unit that there is one element in the operand.

The present invention also discloses a method for performing digital signal processing using a general purpose computer via a plurality of data paths, the general purpose computer comprising a plurality of operands, each operand having at least one element. A data memory for storing one operand and a processing unit having a plurality of sub-processing units are included.
The method includes the following steps. a) Providing instructions from among a predetermined sequence of instructions to be executed by the processing unit. b) The instruction specifies one of scalar mode and vector mode for processing by the processing unit for the operand. Scalar mode indicates to the processing unit that there is one element in the operand, and vector mode indicates to the processing unit that there are multiple sub-elements in the operand. c) In scalar mode, each sub-processing unit in the processing unit receives a respective portion of an operand to be processed in response to an instruction and produces a partial intermediate result. d) Each sub-processing unit sends its intermediate result between multiple sub-processing units and combines its partial results with other sub-processing units to generate the final result for the operand. e)
Generate a first condition code to correspond to the final result. f) in vector mode, each sub-processing unit in the processing unit receives and processes each sub-element from a plurality of sub-elements in an operand in response to an instruction to produce a partial intermediate result, Each intermediate result is disabled and each partial result represents the final result for its corresponding element. g) Generate a plurality of second condition codes. Here, each of the second condition codes corresponds to an independent result.

[0010]

DETAILED DESCRIPTION General Implementation Considerations When incorporating the SIMD scheme into a general purpose machine, there are some issues that should preferably be considered.

1) The selection of scalar or vector operation should preferably be done on an instruction-by-instruction basis, rather than switching to vector mode for a period of time. This is because some algorithms are not easily vectorized with large vector sizes. Also, if vector operations are selected, the dimensions of the vector must be specified.

Currently, in accordance with the present invention, information about scalars / vectors is specified by a data type modifier field in each instruction that has SIMD capability. For example, an instruction may feature a 1-bit "path" modifier field that can specify a word or halfword pair operation. Furthermore, a larger vector dimension,
This field should preferably be combined with the data type conversion field in the streamer context register, for example to select 4, 8, etc. For a complete description of Streamers, see "STREAMER FOR DIGITAL SIG for RISC Digital Signal Processors".
NAL PROCESSOR) ", the disclosure of which is disclosed in related U.S. Patent Application Serial No. 917,872, filed July 23, 1992, the disclosure of which is incorporated herein by reference.

2) The machine must be prepared for conditional execution based on vector results. It is important to be able to test the result of a SIMD operation as if it were done using multiple scalar operations. For this reason, the condition code flags in the status register are preferably duplicated such that there is one set for each segment of the data path. For example, a vector dimension of 4 would require 4 sets of condition codes.

Conditional instructions also need to specify which set of condition codes to use. It would be useful to be able to test a combination of conditions, such as "if any carry flags are set" or "all carry flags are set".

3) The SIMD method should be applicable to as many operations as possible. Although the preferred embodiment of the invention described below illustrates the machine in its current implementation, such as a 16-bit multiplier and 32-bit input data, it will be appreciated by those skilled in the art that other variations can be readily constructed in accordance with the invention. Will be recognized by.

The following operations are possible operations (FIGS. 28-36) that can enhance the performance of space vector (SV) techniques.
Enumerated in) is an example.

ABS, NEG, NOT, PAR, RE
V, ADD, SUB, SUBR, ASC, MIN, MA
X, Tcond SBIT, CBIT, IBIT, TBZ, TBNZ ACC, ACCN, MUL, MAC, MACN, UMU
L, UMAC AND, ANDN, OR, XOR, XORC SHR, SHL, SHRA, SHRC, ROR, ROL Bcond LOAD, STORE, MOVE, Mcond where cond is CC, CS, VC, VS, ZC and ZS. Good.

4) The memory data bandwidth should be compatible with the SIMD data path performance.

It is desirable to adapt memory and bus bandwidth to the data requirements of the space vector data path without increasing hardware complexity. Two 32-bit buses with dual-access 32-bit memory in currently implemented machines are well suited for arithmetic logic units (ALUs) and dual 16x16 multiply / accumulate units (MACs). These are also 4
It will also fit well in one 8x8 MAC.

5) Any additions or modifications implemented should be cost-effective by maximizing performance with minimal additional hardware complexity.

The adder / subtractor stops carry propagation,
It is possible to operate in space vector mode by duplicating the condition code logic.

The shifter can also be operated in space vector mode by reconfiguring the wraparound logic and duplicating the condition code logic.

The bit logic unit can be operated in space vector mode simply by duplicating the condition code logic.

The space vector conditional move operation controls the multiplexer using a vector of condition code flags,
This can be achieved by allowing each element of the vector to be moved independently.

Space vector multiplication requires doubling the multiplier array and combining partial products. For example, four 16x8 multipliers with appropriate combinational logic
16x8 or 2 16x16 vector operations,
Alternatively it can be used to perform one 32x16 scalar operation. The space vector multiplication-accumulation operation also
We need an accumulator adder that can stop carry propagation and duplicate the condition code logic, as well as a vectorized accumulator register.

6) The programming complexity due to the realization of space vectors in general purpose computers should be minimized. Instructions can be devised to combine the space vector result with the scalar result.

ACC Az, Ax, Ay Accumulators are added. SA Ay,
Mz Store scaled accumulator pair in memory.

MAR Rz, Ax Move scaled accumulator pair to register. 7) When a vector crosses a physical memory boundary, it should still be accessible. Some algorithms, such as convolution, require increments through the data array. If the array is treated as a vector of length N, it is possible that the vectors are partially in one physical memory location and partially in adjacent physical memory locations. To maintain performance for such space vector operations, either design the memory to handle data accesses that cross physical boundaries, or refer to the aforementioned US patent application "Streamer for RISC Digital Signal Processors". Preference is given to using a streamer as described.

Overall System FIG. 2 is a generalized representation of a programmable processor which may incorporate the space vector data paths of the present invention. One of the concepts incorporated into the present invention is
By modifying a computer designed to deal with scalar operands or elements of an array one at a time, it is possible to increase its performance by allowing more than one operand to be processed at a time. is there.

Shown in FIG. 2 is a programmable processor, or broadly "computer" having a program and data storage unit 100 for storing program and data operands. The instruction collection unit 130 fetches an instruction from the storage unit 100, which is decoded and interpreted by the instruction fetch / decode / sequence unit 140,
It is executed by the processing unit 110. In this way, the processing unit 110 executes the instruction with the operand supplied from the storage unit 100.

To improve performance, there is a bit in each instruction to specify whether the operand is a scalar or a vector. Also, if they are vectors, it is specified how many elements are in each operand. This information is sent to the processing unit 110 along with the typical decoded instruction so that the processing unit 110 "knows" whether to process the operands as scalars but as vectors.

The processing unit 110 may be an ALU, shifter or MAC. The storage unit 100 may generally be some kind of memory, even a register file,
It may be semiconductor memory, magnetic memory, or any of several types of memory. Processing unit 1
10 is also capable of performing typical operations such as addition, subtraction, logical AND, logical OR, shifts such as in barrel shifters, multiplications, accumulations, and multiplications and accumulations typically found in digital signal processors. Good. The processing unit 110 takes an operand as either one operand used in an instruction, two operands used in an instruction, or many more. Processing unit 110 then performs operations on these operands to obtain their results. By starting with a scalar or vector operand, the operand completes the operation, yielding a scalar or vector result, respectively.

The next step is to more specifically recognize how the processing unit 110 may be formed and how it functions. Although data and programs are shown as being combined in storage unit 100, they can be combined in the same physical memory or implemented in separate physical memories. That would be clear. Each operand is described as having a typical length of 32 bits, but in general the operands could be any of several lengths. It can be a 16-bit machine, an 8-bit machine, a 64-bit machine, and so on. One of ordinary skill in the art will recognize that the general approach is that N-bit operands can be thought of as multiple operands taken together and N-bits added. Thus, a 32-bit word could be, for example, two 16-bit halfwords, or four 8-bit quarter words or bytes. In the current implementation by the inventors, 1
The elements in the two operands have the same width. However, a 32-bit operand can be 24 bits for one element and 8 bits for the other element. An advantage derived from using multiple data paths and multiple elements in the operands is that all elements are processed independently and simultaneously, and an increase in processing throughput is achieved.

The instructions can be of any size.
Currently, 32-bit instructions are used. However, one of ordinary skill in the art may find particular utility in 8-bit, 16-bit, 32-bit, and 64-bit.
More importantly, the instructions do not have to be even fixed length. The same concept, such as those with 16-bit instructions expandable to 32-bit instructions, or instructions are formed by some number of 8-bit bytes, which depends on which particular instruction it is Definitely, it will work even if used in a variable length instruction machine. For those skilled in the art, a summary of an exemplary instruction set is shown in Figures 28-36 to illustrate the instructions that may be implemented in accordance with the present invention.

The processing unit 110 is typically ALU1.
21 and / or MAC 122. It may also only implement the shifter 123 or the logic unit 124.

Adder FIG. 3 shows an ALU for the processing unit (110 in FIG. 2).
Is a schematic representation of an adder that may be implemented in. FIG. 3A shows a conventional 32-bit adder. FIG. 3 (b) shows two 16-bit adders connected for the halfword pair mode. FIG. 3 (c) shows two 16 connected for word mode.
It represents a bit adder.

FIGS. 3 (a) to 3 (c) show that the typical hardware in the 32-bit conventional machine in FIG. It serves to show how it may be modified to achieve.
Vectors are shown here as having two elements. More specifically, it is shown how a 32-bit conventional operand can be split into two elements, each 16 bits. The same principle could be applied to break up into several elements, some of equal length or unequal length.

Referring to FIG. 3A, the conventional adder 20
0 has an input X for the X operand and an input Y for the Y operand. It also has inputs for carry-in 201 and condition code 205, which are typically found in association with adders. Condition code 205
May be V for overflow, C for carry-out, and Z for zero result, i.e. the result from the adder is zero. In addition, it has the result operand output from the adder, which is S. X, Y, and S are all represented by 32-bit words. The control input s / u 202 represents a signed or unsigned operand, where the most significant bit indicates where the number is positive or negative, or in an unsigned operand the most significant bit contributes to the size of the operand. . FIG. 3 (b) is similar to a typical 32-bit adder, but instead is simply a 16-bit adder, where two adders are combined together to form a halfword pair, ie Indicates whether vector operations can be performed on what has two halfword elements per operand. The Y operand is split here as two halfword operands: the lower half Y0 to Y15 and the upper half V0 to V15. Similarly, the X operand is two halfword operands, namely X0 through X1 in the lower half.
5, and the upper half U0 to U15. The result S is S0 to S15 coming from the adder 210,
And the upper half W0 to W15 coming from the adder 220 are recognized. Essentially, the 32-bit adder 200
May be split in the middle to form two 16-bit adders 210 and 220. However, the upper bits will need logic to determine the nature of the sign bit of the operand. Therefore, dividing the 32-bit adder 200 will require additional logic for the lower 16-bit sign control that is divided from the 32-bit adder to form adder 210. In this case, these two adders 210 and 220 have input operands for adder 210 coming from the lower half of the 32-bit operand and input operands for 16-bit adder 220 coming from the upper half of the 32-bit operand. It will be the same, except that it is present.

When the operand elements X and U are separately added and combined with Y and V, respectively, they yield the results S and W, respectively. They also generate independent condition codes for each of the adders. Adder 2
10 generates the condition code 215, and the adder 220 generates the condition code 225. These condition codes apply to the particular halfword adder with which they are associated. Therefore, it can be seen that the conventional 32-bit adder is slightly modified to perform independent halfword pair operations.

Referring to FIG. 3 (c), the same adder unit in FIG. 3 (b) is reconnected to perform the original word operation performed in adder 200 of FIG. 3 (a). May be. This is the case when the operand represents a 32-bit scalar. The scalars are Y0 to Y31 and X0 to X31. The lower half of these operands is processed by adder 230 and the upper half is processed by adder 240.
Processed by. The mechanism that enables this is
By connecting the carry-out of adder 230 to the carry-in 236 of adder 240. As shown in FIG. 2 (c), the two combined 16-bit adders perform the same function as the single 32-bit adder of FIG. 3 (a). Therefore, as shown in FIGS.
In the implementation shown in (c), adder 210 may be essentially the same as adder 230, while adder 2
20 may be the same as the adder 240. Although this description shows how these two adders can work in either half-word pair mode or word mode, those skilled in the art have traditionally used extensions to handle the independent elements of a vector simultaneously. May be transformed into several adders, and may be recombined to perform scalar operations with scalar operands.

One thing to note about the adder of FIG. In FIG. 3C, two sets of condition codes 235 and 245 are shown. On the other hand, the original conventional adder has only one set of condition codes 205. The condition code of FIG. 3C is actually a condition code of 245 except for the condition code Z. The condition code in 235, that is, the overflow V and the carry C is effectively 23 when the condition code in the condition code 205 and the condition code Z are 23.
As long as it is the 245 Z condition code ANDed with the 5 Z condition code, it is ignored. Here, the condition code V of 205 corresponds to the V of 245. The C of 205 corresponds to the C of 245, and the Z of 205 corresponds to the Z of code 245 ANDed with the Z of code 235. The person skilled in the art will be able to combine these in any particular way which seems to fit.

Logical Unit FIG. 4 is a schematic diagram of a logical unit that may be implemented in accordance with the present invention. FIG. 4 (a) illustrates a typical 32-bit logical unit that performs bitwise logical operations, bitwise complements, or some combination typically found in current processors. What may be important is that they work independently for different bits in the condition code. Overflow bits are usually of no significance in the condition code at 305. Carry-out is not significant at all in logic operations, but zero is still significant in indicating that the result is zero. For halfword pair operations, the original 32-bit adder would be "operationally" split into two 16-bit logical units. The upper 16 bits 320 and the lower 16 bits 310 in the input operand are
It will be split into two halfwords in the same manner as for the adder. In processing logical operations, bits are generally processed independently, so there is no operational connection between the two logical units 310 and 320.

FIG. 4 (c) shows the logic units recombined to form a typical logic unit for scalar processing. Please note that no connection is required between units except in the condition code area.
The conventional logic unit zero condition code 305 may be represented herein by ANDing the unit 345 zero condition code with the unit 335 zero condition code. It should therefore be apparent to a person skilled in the art that the dual mode logic unit can be constructed by extending the concept and implementation of the dual mode adder as described above.

Shifters FIGS. 5-8 are schematic representations of barrel shifters that may be implemented in accordance with the present invention. Some processors have barrel shifters as shown in Figure 5 (b), while others have 1-bit shifters as shown in Figures 5 (a), 6 and 7. Barrel shifters are not typically required within the processor unit, but for high performance machines, the processor unit is shown in FIG.
You may implement | achieve the shifter unit as represented by.
The following description shows how shifters may be configured and implemented by those skilled in the art to speed up the process or minimize the amount of hardware required.
FIG. 5 (a) shows how a 1-bit shift, either a left shift or a right shift, may be implemented in a typical processor. The shifter 415 has 32
The bit input operand X can be shifted one bit to the left or right, or not shifted under the control of the direction input DIR 401 to produce the Z output. If a shift occurs, if it is a shift to the left, then the selection box 416 must place the bit in the least significant bit position.

When the shifter is shifted to the right, the bits from select box 400 are placed in the most significant bit position. Selection boxes 400 and 416 are shifters 415
It has several inputs that can be selected to enter.
Both boxes also have a select input labeled SEL, which comes from the instruction and is typical of conventional machines. SEL determines which of these input bits will be selected for entry into the shifter. In general, because of these select boxes, the shift can be a rotation in which the bits shifted out of the shifter are shifted in at the other end of the shifter, and when other bits are shifted right. Can be an arithmetic right shift in which the sign bit or the most significant bit is dragged, or an arithmetic left shift in which a 0 is placed when the other bits are shifted to the left. For logical shifts, "0" is entered as a bit. Also, a "1" is entered as a new bit that is placed in the logical shift.

Those skilled in the art can easily assign the condition code to the shifter by referring to the description of the condition code for adder and logic unit, overflow for arithmetic left shift operation, the last bit of shift operation. Could hold a carry, and a zero flag to record it when the result of the shift was a zero value.

By using the shifters of FIG. 5 (a) in combination, the shifters of FIG. 5 (b) may be formed as a 32-bit left / right barrel shifter. This is done by combining 32 shifters in FIG. 5 (a), cascaded them one after the other, so that the output of the first one enters the input of the second one, and so on. You may The number of bits to be shifted is determined by the pattern of 1's and 0's of the directional inputs DIR to the individual shifters. Note that in FIG. 5 (a) the orientation for the shifter is ternary. Ie left,
Right, or straight ahead, where no shift can be accomplished. Thus, in FIG. 5 (b), the directional input to each 32-bit 1-bit shifter can be left, right, or unshifted. If 32 bits should be shifted to the left, all directional inputs will point to the left.

If only one bit should be shifted to the left, the first box indicates a 1-bit shift to the left, the other 31 all indicate no shift. If N bits should be shifted to the left, the first N boxes would have a 1-bit directional input to the left and the remaining boxes would indicate no shift. The same would apply to a shift to the right. In this case the direction indicates either a shift to the right or no shift, and a shift from 0 to 32 bits would be possible in the right shift as well.

The typical 1-bit shifter in FIG. 5 (a) can now be divided into two 16-bit shifters with reference to FIG. Shown here are two 16-bit L / R 1-bit shifters connected for halfword pair mode. The shifter 415 in FIG.
Operationally, two 16-bit 1-bit shifters 45
It can be divided into 0 and 435. Each of these 16-bit shifters has the input selection logic shown in FIG. 5 (a), which in this case specifically refers to 416 and 400, which includes box 450 having boxes 460 and 445,
Box 435 is duplicated to have boxes 440 and 430. The input logic is the same, but the inputs to the select boxes are wired differently. Therefore, the difference between the shifter of FIG. 6 connected for the half word pair mode and the shifter of FIG. 7 connected for the word mode is in how the input selection boxes are wired. The input operand elements of FIG. 6 for the lower shifter 450 are X0 to X15, and the input operand elements for the shifter 435 are Y0 to Y15. In this way X
And Y indicate two halfwords.

Result The Z output operand is shown as two halfwords. Lower 16 bits are Z0 to Z15
And the upper 16 bits are W0 to W15. The input selector is wired so that the bits output from the shifter during rotation are fed back to the other end of the shifter. When the shifter 435 shifts left, the rotated bit becomes Y15, and when it shifts right, the rotated bit becomes Y0. Similarly, for shifter 450, if it is a left rotation, the input bit is X15, and if it is a right rotation, the input bit is X0. Similarly,
The choice is also made for arithmetic and logical shifts in FIG.
Works as in (a).

FIG. 7 shows how the operation of these same two shifters can be connected for word mode. Here, the shift pattern works for the entire 32 bits in the operand, unlike the two halfwords in FIG. For leftward rotation, lower shifter 486
Bit rotated from the outside (MSB bit x15)
Is rotated into the upper shifter 475, while L
The SB bit is input to the shifter 475. This forms a continuous shift between the upper 1-bit shifter and the lower 1-bit shifter. For rotations around the two shifters, X31 will be shifted to X0. If all the inputs of the selector 480 are connected to X15 and all the inputs of the selector 485 are connected to X16 as shown in FIG. 7, then the combined shifter of FIG.
It effectively operates as the shifter in (a). The input selector 470 will have the same pattern as the input selector 400. Input selector 488 will have the same input pattern as selector 416. Therefore, the combined shifter of FIG. 7 will perform the same shift operation for scalar operands as the shifter in FIG. 5 (a).

The 1-bit shifter in FIGS. 6 and 7 is further connected to the 3-bit shifter shown in FIG. 8 in a manner similar to FIG. 5B by cascade-connecting 32 1-bit shifters.
It can be extended to a 2-bit barrel shifter. If a 1 bit shift is desired, the direction control signal is used for the first shifter to indicate a 1 bit shift. There is no shift shown for the other cascaded 1-bit shifters. For N-bit shift, the first N
The direction input in each 1-bit shifter indicates that it shifts by 1 bit, and the remaining 1-bit shifters pass the data without shifting.

Similarly, the barrel shifter of FIG. 8 can perform either word or halfword pair mode operations. This is because the individual bit shifters can perform either word or halfword pair operations. Although the embodiments of FIGS. 5-8 are representative of one method of implementing a barrel shifter, the same concept of splitting the barrel shifter in the middle to provide the input selection logic applies to many other implementations of the barrel shifter. Can also be applied. One of ordinary skill in the art will be able to find suitable implementations depending on the particular hardware or throughput requirements.

Multiply Accumulator FIGS. 9 and 10 are schematic diagrams of a multiply and accumulate (MAC) unit that may be implemented in accordance with the present invention.

A typical 32-bit processor will usually not require an expensive 32x32 multiplier array implementation. Multiplication will probably be established in other ways. However, in a typical 16-bit signal processor, 1
A 6x16 multiplier array is quite common. Since 16-bit data is typically used for types of computations that require fast multiplication, 16 × 16 multiplier arrays have become more prevalent, which is a few
This is true even in bit processors.
Therefore, by treating a 32-bit operand as two 16-bit halfword pairs, a 32-bit word operand in one vectorized operand,
Two 16x16 multiplier arrays can be implemented to take advantage of the concept of halfword operands, or spatial vectors of halfword elements.

The following example shows how a 16 × 16 multiplier array can be duplicated and used as two halfword pair multipliers, which are connected together. May result in a 32 × 16 scaler multiplication. This 32 × 16 scalar multiplication has the usefulness that two of these multipliers can be used together to make a 32 × 32 bit multiplication. Or 32x
16 multiplications can also be used on their own, in this case 32
Bit precision operands may be multiplied by only 16 bit precision operands.

MAC units are not typically found on all processors. However, this is typically implemented in high performance processors for signal processing applications. FIG. 9 shows a conventional implementation example of a MAC unit. The MAC can be any of various sizes. This is a 1 in the multiplier that forms the 32-bit product.
It is a unit of 6 bits × 16 bits. This 32-bit product may be added with the third operand in the accumulator adder, which may be longer than the product due to the extra high order bits called "guard bits".

As shown in FIG. 9, the input operand is 16 bits and contains X0 to X15 and Y0 to Y.
It is represented by 15. These produce a 32-bit product Z, which may be added to the feedback operand F. In this case, F is designated as F0 through F39, which represents a 40-bit feedback word or operand. This is 40 bits because 32 holds the product.
This is because an additional 8 bits would be needed for the bits plus the guard bits. Guard bits are included to handle overflow. This is because overflow can occur when several products are added and the guard bits accumulate overflows to protect them. Typically the number of guard bits will be 4 or 8. Although eight bits are shown in this example, several sizes are possible. The accumulator results are presented as 40-bit results A0 through A39.

It should be noted that the multiplier array can be used without a multiplier or with a multiplier. It should be noted that another input S / U, which means signed or unsigned, indicates whether the input operand should be treated as a signed or unsigned number. Those skilled in the art will recognize that the upper bits of the multiplier are treated differently depending on whether the input operand is signed or unsigned.

FIG. 10 shows how a typical 16 × 16 array is formed to handle halfword pair operands. In this case, the 32-bit input operand X
Is divided into two halfwords. The lower halfwords for multiplier 520 are X0 to X15 and the upper halfwords for multiplier 515 are X16 to X3.
It is 1. The Y input operand is also split into two halfword operands. The lower halfwords for multiplier 520 are Y0 to Y15, and the upper half for multiplier 515 is Y16 to Y31. FIG. 10 thus represents a connection for multiplying each halfword operand of the X operand with each halfword operand of the Y operand. The lowest halfword of X is multiplier 5
Note that at 20 is multiplied with the least significant halfword of Y. Also, in the multiplier 515 independently and simultaneously, the upper halfword of X is multiplied with the upper halfword of Y. These two multiplications yield two products. The 32-bit product from multiplier 520 is Z
0 to Z31, and similarly the 32-bit result of multiplier 515 is represented by W0 to W31. The two products are each larger than 16 bits to preserve their precision. At this point, the halfword product is saved as a representation of the independent operands.

The product from the lower halfword output from multiplier 520 is sent to accumulator 530, which is F0 through F39.
It is added in the feedback register represented by. This gives the accumulated product A represented by A0 to A39.
Is formed. Similarly, in the upper halfword, the product is represented by W0 through W31 and is added in accumulator 525 to the feedback register represented by G0 through G39 to form the 40 bit result B, which The results are represented by B0 to B39. The results of these accumulators are generally stored as larger numbers in the accumulator as operands represented by larger numbers or bits to preserve the precision of the multiplication.

The feedback bits will typically come from either memory (100 in FIG. 2) or a specialized memory capable of storing a larger number of bits. A typical memory location can handle 32 bits, but a special memory, typically called an accumulator file, can store 40 bits for a scalar product or 80 bits for a halfword pair product. Could be stored. In this case, two accumulation registers capable of handling scalar operands may be used to form the storage for the halfword pair operands. In other words, two 40-bit accumulators could be used to store the two 40-bit results of a halfword pair operation.

MAC Interconnect FIGS. 11 and 12 show 16 for scalar operands.
11 illustrates how two 16-bit multipliers of the array of FIG. 10 can be interconnected to form a x32-bit multiplication. In this example, the multiplier array is implemented as an adder train. Carry-out 605 of lowest multiplier array 610 is provided as a carry input to the adder of upper multiplier array 600. Further, the sum bit 606 formed at the bottom end of the upper multiplier array 600 is provided at the top end of the adder of the lower multiplier array 610.

Other connections occur to accumulators 615 and 605. The accumulator 615, which represents the lower part of the product, is limited to 32 bits and the upper 8 guard bits are unused. Three
2-bit carry out is the upper 40-bit accumulator 60
The carry input of 5 and the result is a 72 bit operand, shown here as B0 through B39. This operand is typically stored as two operands with the lower 32 bits stored in one accumulator 615 and the upper 40 bits stored in a second accumulator 605. Further, in this operation, the lower half of the input operand X is treated as an unsigned number in the multiplier 610 because of the signed and unsigned bits, and the upper 16 bits of the input operand X are in the upper multiplier array 60.
At 0, it is treated as a signed or unsigned operand.

Further, in the lower accumulator 615 the product is treated as an unsigned operand while the upper accumulator 60
In 5, the operand is treated as a signed number. It should be added that the 40-bit accumulator is treated as a signed number in all the examples of FIGS.
This is because the guard bit, an extension of the accumulator, allows bits that even an unsigned number could be considered the positive part of a signed number. Therefore, the signed number in the extended accumulator includes both signed and unsigned operands.

FIG. 12 illustrates multiplier arrays 600 and 61.
It shows in more detail how the carry and sum bits interact between the adders that make up 0. For example,
Adders 625 and 635 are shown as part of multiplier array 610 and adders 620 and 630 are shown as part of multiplier array 600. It should be noted that multiplier arrays 610 and 600 are typically implemented with some form of adder. Depending on the particular implementation, the interconnection of the adders may be done in various ways. Although FIG. 10 shows a simple cascade of adders, this same technique may be used in other ways where the adders would be connected as in, for example, a Booth multiplier or a Wallace tree multiplier. . As shown in FIG. 12, the adder 625 of the lower multiplier array 610 is
Provides a carry-out 621 provided to the carry input of the corresponding adder 620 of the upper multiplier array 610. Lower multiplier array 610 operates as if the input operands of the X-input were unsigned. The sign of the input operand is specified, and the upper multiplier 6
00 is used for sign control of the upper adders 620 and 630 of the array.

Furthermore, the adders are connected in such a way that they are offset from the least significant bit of the multiplier to the most significant bit of the multiplier, which gives the opportunity to add back the total bits back. More specifically, adder 625
And 620 correspond to the lower bits of the multiplier, designated Yi. Adders 635 and 630 have Y (i
+1) corresponding to the next higher bit of the multiplier. This offset is the output S1 of the adder 625 given to the input B0 of the adder 635 and the adder 635.
Can be seen as S15 of the adder 625 fed to the input B14 of This 1-bit offset is added by the adder 620.
B1 of input of adder 635 to receive input S0 from
5, the sum bits from the most significant multiplier array 600 are provided as input bits to the least significant multiplier array 610.

Furthermore, the total bit S from the adder 625
The 0 goes directly to the next partial product, shown as 640, and does not have to go through an additional multiplier or adder stage. Therefore, outputting S0 from successive adder stages 625, 635, etc., produces output bits Z0 through Z15 of FIG. The output bits from the final partial product corresponding to S0 to S15 of adder 635 are shown in FIG.
Will produce output bits from array 610 of.

Those skilled in the art will understand how the final adder stage could be used to provide compensation should multiplier Y be negative.

Classification of Operand Data Types Attention is now paid to the classification of operand data types. One approach to specifying the type of operand mode as a scalar or vector is to include that information in the instruction, but an alternative approach is to add that information in additional bits of the operand. For example, if the operand is 32 bits, one additional bit may be used to identify the operand as either a scalar or a vector. Additional bits may also be used if the number of vector elements is explicitly indicated or may be assumed to be some number such as two.
The operand processing unit will be adapted to process the operand as a scalar or as a vector by responding to the information added to the operand.

Whether the operand is a scalar or a vector may be further specified by the way the operand is selected. For example, the information may be contained in a bit field at a memory location that further identifies the address of the operand.

If two operands are processed by a processing unit and the mode information is different in the two operands, the processing unit may be prescribed by a person skilled in the art to handle mixed mode operations. For example, an ADD operation with a vector operand and a scalar operand may be processed by the processing unit by forming a vector from the scalar, truncating if necessary, and then performing the vector operation.

An alternative to spatial hardware
It will be appreciated by those skilled in the art that time-sharing an im-sharing implementation can often be a substitute for a spatially-distributed implementation. For example, one vector adder may be used multiple times to effectively implement multiple adders in a spatially distributed vector processing unit. With hardware multiplexing and demultiplexing,
It is also possible to order the input operands and the result. A vector adder with additional support hardware may also be used to handle the scalar operands in a manner similar to how distributed vector adders may be interconnected to handle the scalar operands. . Support hardware is used to process intermediate results that pass between vector processing elements.

With the above description of the invention in mind, an exemplary RISC-type processor incorporating the space vector data path of the present invention will now be described. Note that the processor system below is but one example of how a person of ordinary skill in the art would incorporate the present invention. Other examples will find their advantageous application according to the invention described.

Exemplary Processor Incorporating the Invention Reference is made to FIG. 13 which shows a functional diagram of a processing element incorporating the invention. The following description refers to specific bit widths,
Those skilled in the art will appreciate that they are for illustration only and that other widths can be readily constructed in accordance with the teachings of the present invention.

Referring to FIG. 13, an instruction capable of specifying two source operands and one destination operand is used to control the illustrated data processing unit.

Operands are typically stored in registers and in data memory (200). Arithmetic, logical, and shift instructions are ALU240 and MAC
At 230, the operand is executed from the register space and the result is returned to the register space. The register space consists of register file 220 and some other internal registers (not shown). Operands stored in register space are either 32-bit words or halfword pairs. Operands are loaded and stored in register space and memory 200.
To or from the register space and the streamer 210, which is an automatic memory access unit, as described above.

Referring to FIG. 14, a functional block diagram of ALU 240 is shown. ALU is an adder 410, 420
And barrel shifter 470. Generally, AL
The U instruction takes two operands from the register space,
Write the result to the register space. The ALU instruction can execute each clock cycle, requiring only one instruction clock cycle in the ALU pipe.

Adders 410 and 420 and shifter 470
Performs an operation using a word or halfword pair operand. Signed operands are represented in two's complement notation. Currently, signed, unsigned, decimal, and integer operands can be specified by instructions for ALU operations.

Adder Adders (410, 420) perform addition and logical operations on word and halfword pairs. For halfword pair operations, adders 410, 420 function as if there were two halves. The lower half 420 uses the lower operand 460 of the halfword pair to perform the operation and the upper half 4
10 is the same operation as the upper operand 45 of a halfword pair
Run with 0. When in halfword pair mode, the two adders 410, 420 are essentially independent of each other. The 32-bit logic unit 440 is used to send information from the lower adder 420 to the upper adder 410 and vice versa when the two adders are operating in word mode.

The adder operation affects two carry (CU and CL), two overflow (VU and VL), and two zero (ZU and ZL) condition code bits. CU is a carry flag for word operation, and CU and CL are carry flags for halfword pair operation. Similarly, VU indicates overflow in word operation, and VU and VL indicate overflow in halfword pair operation.

Overflow affecting the overflow flags can result from adder arithmetic instructions and from MAC scalar instructions. The overflow flag is set even if the executed instruction saturates the result.
Once set, the condition code does not change until there is another instruction that can set the flag.

An error exception request occurs when an adder operation instruction without saturation overflows and error exceptions are enabled. Separate signals are sent to the debug logic to indicate saturated and unsaturated overflows.

Barrel Shifter Referring to FIG. 14, during one clock cycle, the barrel shifter shifts all bits in the word operand up to a 32-bit position to either the left or the right, while zero, the sign bit of the operand, Alternatively, the upper carry flag (CU) of the adder can be rotated or inserted. For halfword pair operations, in one clock cycle, the shifter shifts both halfwords up to the 16-bit position to the left or right, while zero, sign bit, or adder carry flags (CU and C).
L) can be rotated or inserted.

For a typical shift / rotate operation, barrel shifter 470 moves each bit in both source operand positions in the direction indicated by the operation. For each position shift, barrel shifter 470 either rotates the last bit or inserts a sign bit, carry flag (CU or CL), or zero, depending on the operation selected.

For example, for left rotation, the bits are shifted to the left. Bit 31 is bit 0 in word mode
Is shifted to. For halfword pair mode, bit 31 is rotated to bit 16 and bit 15 is rotated to bit 0. For right rotation, the bits are shifted to the right. Zero is bit 31 in word mode
Is inserted into. For halfword pair mode, zeros are inserted in both bit 31 and bit 15. Similarly, for shifts with carry propagation, the carry flag (CU) is inserted in bit 31 in word mode.
In the halfword pair mode, carry flags (CU and CL) of each halfword are inserted in bit 31 and bit 15.

Next, referring to FIG. The dual MAC units are two MAC units 520, 550, 57 that are interconnected together to produce either two 16x16 or 16x32 products.
0, 590 and 510, 540, 560, 580. Each MAC has a 16 × 16 multiplication array 51
0 and 520, accumulators and adders 560 and 570, accumulator register files 580 and 590, and a scaler 591.

Some exemplary instructions are: multiplication, accumulation, multiplication and accumulation, universal halfword pair multiplication, universal halfword pair multiplication and accumulation, double multiplication step, and double multiplication and accumulation step. Two
8--See the summary of instructions listed in FIG.

Word operations can be performed on either MAC unit. It should be noted that the "word" used in the MAC unit is 16 bits, as the MAC is currently a 16x16 operation. However,
A more convenient approach is to represent the operation with a vector length of 1, 2, 4 or 8. Therefore, MA
Word operations in C can be called vector length one, while halfword pair operations will be vector length two. The MAC, including the destination accumulator, is the one currently used to perform operations.

Halfword pair operations use both MAC units. The instruction identifies the particular accumulator as the destination accumulator, which becomes the addressed accumulator. A MAC that includes an addressed accumulator that is addressed operates on the lower halfword pair element and the other ("corresponding") M
AC performs the same operation on the upper halfword pair element.
The result from the corresponding MAC is stored in the corresponding accumulator, and the addressed accumulator and the corresponding accumulator are located at the same relative position in their respective register files.

Double precision operations are performed on halfwords and words, and this operation is combined as a dual MAC.
One MAC. The "upper" MAC does the top part of the calculation and the "lower" MAC does the bottom part of the calculation.

The MAC unit may support integer or fractional operands and signed or unsigned operands.

Accumulator Register File The two MAC units are called upper MAC and lower MAC. Each MAC has an accumulator register file consisting of four 40-bit guarded accumulator registers, for a total of eight accumulators in the ALU. Each guarded accumulator (AGn) consists of a 32-bit accumulator register (An) that is extended with an 8-bit guard register (Gn) at the most significant end. FIG. 16 shows the layout of the accumulator register file.

The halfword pair operand accumulator is stored in two accumulators. The subelements of a halfword pair are accumulated as a 40-bit number in one accumulator of either MAC. The upper element of the halfword pair is 40 in the corresponding accumulator in the other MAC.
It is accumulated as the number of bits (FIG. 17 shows the corresponding address).

The two accumulators are further used to store the results of double precision step operations. The most significant part of the result is stored in the guarded accumulator AG of the upper MAC. The least significant part of the result is stored in the accumulator A of the lower MAC. The lower MAC accumulator guard bits are not used.

Each accumulator has two addresses in the register space called the upper and lower accumulator addresses or the upper and lower redundant addresses. (The assembly language name of these addresses for accumulator n is An respectively
H and AnL. The effect of which address is used depends on how the register is used in the instruction, and these effects are discussed in detail in the subsections below.

The instruction format (and assembly language) provides several ways of addressing accumulators.

As an element of register space. Each accumulator has a high and low address in the range 111 to 127 with assembly language symbols ARnH and ARnL.

As an accumulator operand. The instruction format takes a number in the range 0-7 and the corresponding assembly language symbol is the An format.

As an accumulator operand with separate upper and lower addresses. The instruction field takes values in the range 0-15 and the assembly language format is AnH or AnL.

Each of the eight guard registers has an address in the extended register space (160-167; assembly language symbols have the AGn format).

The remaining subsections of this section specify the treatment of accumulators and guard registers as instructions. There are many special examples, depending on whether the register is the source or the destination and the element of the operation is a word or a halfword pair.

1. Accumulation as word source operand
The upper-order accumulator address specifies the upper 32 bits of the accumulator An as a decimal word operand, and the lower-order address is An.
The lower 32 bits of are specified as an integer word operand. In the current version of the processor, the accumulator is 32
Because of the length of the bits, both addresses refer to the same 32 bits. However, common processor architectures allow longer accumulators. Guard bits are ignored by instructions that use accumulators (assembly language An) as 32-bit source operands. If the instruction specifies to use a guarded accumulator (assembly language AGn), for example for an accumulator register or as input to the scaler, the guard bit is included in the 40-bit source operand.

The bus structure currently allows one accumulator register from each MAC to be used as the source operand specified in any given instruction.

When the accumulator is selected as the source operand for the multiply operation, all 32 bits are presented by the accumulator. The instruction further selects the lower or upper halfword for input to the multiply array with an integer / fraction option.

2. Halfword vs source operand
Each element of every accumulator halfword pair is held in the accumulator as if it were a word operand. The two elements of the halfword pair are stored in corresponding accumulators on separate MACs. When used as accumulator registers in their respective MACs or as inputs to the scaler, they are used as 40-bit source operands.

Otherwise, the elements are assembled as two halfwords in a halfword pair operand. If the halfword-to-source operand is the upper accumulator address, the upper halfword of the accumulator is used for each element. If the lower accumulator address is used, the lower halfword is used. The addressed accumulator provides the lower halfword and the corresponding accumulator provides the upper halfword. Any MAC can supply any element of a halfword pair.

3. Accumulate as double precision source operand
The accumulator is used for precision source operands only in double precision step operations. The addressed accumulator provides the least significant 32 bits and the corresponding guarded accumulator provides the most significant 40 bits.

4. Guard register as source operand
The star 8-bit guard register (Gx) can be directly accessed from the extension register space as a sign extension integer.
If the guard register is the source operand of a halfword pair operation, the guard addressed is the lowest halfword operand and the corresponding guard is the highest half operand. In both examples, the guard register is sign extended to 16 bits.

5. For word operations with accumulator MAC as the word destination operand, the 32-bit result of the multiply operation is stored in the destination accumulator and sign extended via its guard register. The 40-bit result of the accumulate operation is stored in the destination guard accumulator.

In another register-to-register instruction, the result is moved to the destination accumulator and sign-extended through its guard register.

6. Accumulate as word versus destination operand
In a load instruction that targets an accumulator that specifies the conversion of the data type of an instrument word pair, the word from the lower memory address is loaded into the addressed accumulator, and the highest word from the higher memory address is loaded. The low byte is loaded into the accumulator guard register.

7. Halfword vs as destination operand
Accumulator In a halfword pair operation using two MAC units, the result of each MAC is stored in its accumulator file. The MAC containing the destination accumulator processes the lower halfword pair element and its 40-bit result is stored in its guarded accumulator (AG). The corresponding MAC processes the upper halfword pair element and its 40-bit result is stored in the corresponding guarded accumulator (AGC).

In another register-to-register instruction, the particular accumulator address selected for the destination accumulator determines how the result is stored. If the high address is used, the lowest halfword is loaded into the highest half of the selected accumulator, zero-extended to the right, and sign-extended through its guard register. The most significant halfword is loaded into the most significant half of the corresponding accumulator, zero-extended to the right, and sign-extended through its guard register. If the lower address is used, the least significant halfword is loaded into the least significant half of the selected accumulator and coded through the most significant half of the selected accumulator and then through its guard register. To be extended. The most significant halfword is loaded into the least significant half of the corresponding accumulator and sign extended as described above.

8. Accumulator as Double Precision Operand The least significant 32 bits of the result of the double precision multiply step operation are stored in the destination accumulator and the most significant 40 bits are stored in the corresponding guarded accumulator. The destination accumulator guard bits are all set to zero.

9. Guard register as destination operand
If data guard register is the destination operand, the result 8
The two least significant bits are stored in the addressed guard register. If the guard register is used as the destination operand of a halfword pair operation, the 8 least significant bits of the result are stored in the addressed guard register and the 8 least significant bits of the upper halfword are stored in the corresponding guard register. Stored.

Multiplication Array Reference is now made to FIG. The multiplication array or unit for each MAC is 32 from the two 16-bit inputs.
Produces a product of bits. Signed and unsigned inputs, integer and decimal inputs may be multiplied in any combination.
For integer inputs, the least significant halfword of the source operand is used. For decimal input, the most significant halfword is used. Figure 18 shows the input scaling,
FIG. 19 shows output scaling.

If two word operands or one word and one immediate operand are to be multiplied,
Only the MAC containing the destination accumulator is used. 2 HP
If the operands or one HP and one immediate operand are multiplied, both MACs are used and the MAC containing the destination accumulator multiplies the lower HP elements.

The two multiply arrays used together yield a 48-bit product from one 16-bit input and one 32-bit input scaled according to FIG. This product is scaled according to FIGS. 20 and 21.

Multiply Saturation If -1.0 is multiplied by -1.0 (as a 16-bit signed fraction) without accumulation, the result (+1.
0) saturates to prevent overflow to guard bits. The largest positive number is placed in the accumulator (A) and the guard bit is set to zero. If the multiply instruction involves an accumulate, the result will not saturate and instead the complete result will be accumulated and placed in the destination guard accumulator.

Multiply Scaling FIGS. 18, 19, 20 and 21 show the scaling of source operands and results for multiply operations. The table shows the assumed position of the decimal point and the treatment of any sign bit.

FIG. 18 illustrates the scaling of source operands for multiply operations. FIG. 19 shows the scaling for a 32-bit product. 20 and 21 show scaling for a 48-bit product. (Fig. 20 (a)
And (b) show scaling of right-justified products in lower and upper MAC, respectively, also in FIG.
(A) and (b) show scaling of left-justified products. ) Accumulating Adder Referring to FIG. 15, each MAC includes an accumulating adder capable of adding inputs to (or subtracting inputs from) an accumulator. Possible inputs are:
Product from multiplication array, immediate operand, either MA
Accumulator from C, or register containing word or halfword pairs.

The accumulation initialization characteristics are controlled by the IMAC (inhibit MAC accumulation) bit of the status register (ST) (not shown). If the instruction performing the multiply / accumulate operation is executed and the IMAC bit is true (= 1), the destination accumulator is initialized to the input operand and the IMA
The C bit is reset to false (= 0) (actually the destination accumulator is set to 0 before the inputs are accumulated).

Similar initialization and rounding characteristics are controlled by the IMAR bit in the status register. IM
When an instruction that performs a cumulative adder operation is executed while the AR bit is true, the accumulate register is replaced by the rounding factor and the destination accumulator is initialized to the input operand plus the rounding bit. And the IMAR bit is reset to false. The rounding factors are all 0s, except for the 1s in the most significant bit of the lower halfword.

Some multiply instructions include a rounding option implemented in the accumulator adder. The rounded result is placed in the upper halfword of the destination accumulator and zero is placed in the lower halfword. The result should be considered to have a decimal point between the lower halfword and the upper halfword, the result is rounded to the nearest integer, and if the lower halfword is ½ (ie the upper bits are 1
, The result is rounded to the nearest even integer.

Overflow of the accumulator does not set the overflow flag. When an overflow occurs for an accumulate instruction with the saturation option, the guarded accumulator is set to its largest positive or smallest negative number depending on the direction of overflow. If the instruction does not specify saturation and error exceptions are enabled, overflow results in an error exception request. Separate signals are sent to the debug logic for overflow with saturation and overflow without saturation.

FIG. 22 shows a word or accumulator operand that is added to the accumulate register. FIG. 23 shows a halfword pair operand (from a register or accumulator) that is added to a halfword pair in an accumulation register.

FIG. 24 shows the products added to the accumulation register. FIG. 25 shows the product of halfword pairs that are added to the halfword pairs in the accumulation register.

FIG. 26 shows a 48-bit product accumulated using the right justify option. This option is applicable to the first step of a 16x32 product, or a 32x32 product, where an integer result is desired.

FIG. 27 shows a 48-bit product accumulated using the left justification option. This option is applicable to the second step of a 16x32 product, or a 32x32 product, where a fractional result is desired.

28-36 are a summary of the operational instructions that would be implemented according to the space vector data path of the present invention.

Scaler Referring to FIG. 15, the scaler unit can perform a right barrel shift of 0 to 8 bit positions over the length of the guarded accumulator. The most significant guard bit is propagated to the vacant bit.

If the guard bits and the most significant bit of the result do not all match, an overflow occurs during the scaler instruction. (If these bits match,
That means the sign bit of the accumulator propagates through the entire guard register and no overflow of the accumulator occurred in the guard bit. The scaler instruction supports an option to saturate the result when an overflow occurs. In this example, the result is set to the largest positive or smallest negative number plus one least significant bit, depending on the direction of the overflow (the most significant guard bit is the original number). Was positive or negative.) When overflow occurred and saturation was not specified,
An error exception occurs if the error exception is enabled. Unsaturated and saturated overflows are reported to the debug logic in separate signals.

To normalize the accumulator, a move to register scaled accumulator (MAR) may be used. To normalize the accumulator An: MAR Rx, AnH, # 8; Scale AGn with 8 bits MEXP Rc, Rx; Measure exponent SUBRU. W. SAT Rc, Rc, # 8; Calculate the number of shifts required for normalization MAR Rx, AnH, Rc; Normalize the contents of the accumulator After this sequence, Rc normalizes the guarded accumulator Rx contains the normalized result.

Although the present invention has been described with reference to FIGS. 1-36, it is understood that the teachings of the present invention may be applied to various processing schemes as determined by those skilled in the art.

[Brief description of drawings]

FIG. 1A shows a conventional single instruction, multiple data (SI).
MD) is a conceptual diagram of a computer. (B) is SI
FIG. 3 is a simple diagram of a processing element used in an MD computer.

FIG. 2 is a generalized diagram of a programmable processor that will incorporate the present invention.

FIG. 3 (a) is a schematic diagram of a conventional adder that would be incorporated into an ALU for a processing unit. (B) and (c) are schematic diagrams of an adder that will implement the present invention.

FIG. 4 (a) is a schematic diagram of a conventional logic unit that would be incorporated into an ALU for a processing unit.
(B) and (c) are schematic diagrams of logic units that will implement the present invention.

5 (a) and 5 (b) are schematic views of a conventional shifter that will actually implement the present invention.

FIG. 6 is a diagram of a shifter that may incorporate the present invention.

FIG. 7 is a diagram of a shifter that may incorporate the present invention.

FIG. 8 is a diagram of a shifter that may incorporate the present invention.

FIG. 9 is a simple diagram of a conventional Multiply Accumulator (MAC).

FIG. 10 is a diagram showing how a MAC may incorporate the present invention.

FIG. 11 is a diagram showing how a MAC may incorporate the present invention in a 32 × 16 mode.

FIG. 12 shows the intra-MAC interconnection for 32 × 16 mode.

FIG. 13 is a simple functional diagram of a processing element incorporating the present invention.

FIG. 14 is a simple diagram of an ALU and shifter incorporating the present invention.

FIG. 15 is a diagram showing a dual MAC configuration.

FIG. 16 is a diagram showing a layout of an accumulator register file.

17 (a) and (b) are diagrams showing corresponding accumulator addresses.

FIG. 18 is a diagram showing source operands for multiplication operations and scaling of results.

FIG. 19 is a diagram showing source operands for multiplication operations and scaling of results.

20 (a) and (b) are diagrams showing source operand and result scaling for multiplication operations.

21 (a) and (b) are diagrams showing source operand and result scaling for multiplication operations.

FIG. 22 illustrates a word or accumulator operand added to an accumulator register.

FIG. 23 illustrates a halfword pair operand that is added to a halfword pair in an accumulation register.

FIG. 24 is a diagram showing products added to an accumulation register.

FIG. 25 is a diagram showing a product of a halfword pair added to a halfword pair in an accumulation register.

FIG. 26 is a diagram illustrating a 48-bit product accumulated using the right justification option.

FIG. 27 shows a 48-bit product accumulated using the left justification option.

FIG. 28 is a diagram showing a summary of instructions that may be implemented in accordance with the present invention.

FIG. 29 shows a summary of instructions that may be implemented in accordance with the present invention.

FIG. 30 shows a summary of instructions that may be implemented in accordance with the present invention.

FIG. 31 is a diagram showing a summary of instructions that may be implemented in accordance with the present invention.

FIG. 32 is a diagram showing a summary of instructions that may be implemented in accordance with the present invention.

FIG. 33 is a diagram showing a summary of instructions that may be implemented in accordance with the present invention.

FIG. 34 shows a summary of instructions that may be implemented in accordance with the present invention.

FIG. 35 is a diagram showing a summary of instructions that may be implemented in accordance with the present invention.

FIG. 36 illustrates a summary of instructions that may be implemented in accordance with the present invention.

[Explanation of symbols]

 100 program and data storage unit 110 processing unit 121 ALU 122 MAC 123 shifter 124 logic unit 130 instruction collection unit 140 instruction fetch / decoder / sequence unit

Front Page Continuation (72) Inventor Kennis E. Galley United States, 92714 California, Irvine, Friends Court, 17531 (72) Inventor George A. Watson United States, 92635 Fullerton, California, Treeview Place , 2952 (72) Inventor John Earl, United States, 92680 Williams Street, Tustin, California, 15512-pea

Claims (30)

[Claims] 1. A programmable processor for multiple data path processing of at least one operand, each operand comprising at least one element, said processor being predetermined as determined by instruction fetch / decode / sequence means. Executing instructions in sequence, the programmable processor a) coupled to the instruction means to identify for each instruction whether the at least one operand is processed in one of a vector and a scalar mode B) a processing unit coupled to said mode means, said processing unit receiving said at least one operand and responsive to said vector identified by said mode means and said vector and In one of the scalar modes Process at least one operand, the vector mode indicates to the processing unit that there are multiple elements in the operand, and the scalar mode indicates to the processing unit that one element is in the operand. , Programmable processors. 2. The processing unit is a) responsive to an instruction from the mode means to concurrently parallel process each respective element in the at least one operand to provide an independent operation for each respective element in the vector mode. B) responsive to the instruction from the mode means, a first element in the at least one operand is associated with at least one of the operands in the vector mode. Second vector means for processing in selective combination with a second element, and c) processing each respective part of said operand in response to said instruction from said mode means to produce a respective partial result. And scalar means for deriving a scalar result in said scalar mode by combining each respective partial result. Programmable processor. 3. The first vector means and the scalar means are at least one of a) a plurality of multiply-accumulators, b) a plurality of shifters, c) a plurality of arithmetic units, and d) a logic unit. The programmable processor of claim 2, comprising one, each processing one of at least one respective element in the vector operand and each portion of the scalar operand. 4. The scalar means performs conditional movement,
The second vector means and the scalar means are the second
4. The programmable processor of claim 3, wherein conditional branching is performed based on said selective combination of said first and second elements in said operand in said vector mode. 5. The processing unit comprises: a) a plurality of adders operating in one of the vector and scalar modes, each adder of the plurality of adders being a vector specified by the mode means. The elements from the operands are received and processed individually, the adders receive a scalar operand specified by the mode means and process it together, the processing unit further comprising: b) the adders. And adder control means for sending a carry status between each of the plurality of adders in the scalar mode so that the plurality of adders treat the scalar operand as one adder. The programmable processor according to claim 1. 6. The adder control means further sends an overflow status between each of the plurality of adders in the scalar mode so that the plurality of adders processes the scalar operand as one adder. The programmable processor according to claim 5. 7. The processing unit comprises: a) a plurality of Multiplier Accumulators (MACs) operating in one of the vector and scalar modes, each MAC
Receives the elements in the vector operand as specified by the mode means and concurrently processes them separately in parallel, the plurality of MACs receives the scalar operand specified by the mode means and processes them together, The processing unit further comprises: b) MAC control means coupled to the MAC and responsive to the mode means for operating the plurality of MACs independently of each other in the vector mode and together in the scalar mode. The programmable processor according to claim 1. 8. The processing unit comprises: a) a plurality of logic units operating in one of the vector and scalar modes, each logic unit of the plurality of logic units being identified by the mode means. An element in a different vector operand and concurrently processing them separately in parallel, the plurality of logical units receiving a scalar operand specified by the mode means and processing it together, the processing unit further comprising: b) A logic coupled to the plurality of logical units for sending a zero status between each of the plurality of logical units in the scalar mode so that the plurality of logical units treat the scalar operand as one logical unit. The programmable processor according to claim 1, comprising control means. 9. The processing unit comprises: a) a plurality of shifters for selectively operating as one integrated shifter in the scalar mode and as a plurality of shifters in the vector mode, Each of the shifters is responsive to the mode means in the first mode of operation and receives an element from the identified vector operand for parallel processing separately and the plurality of shifters are Responsive to the mode means in operation of a mode, receiving a scalar operand and processing it together, the processing unit further comprising: b) being coupled to the shifter, the plurality of shifters processing the scalar operand, A shifter control means for sending a shifted operand bit between each of the plurality of shifters in the scalar mode; Motor control means, in the vector mode, disabling the sending shifted operand bits from each of said plurality of shifters, programmable processor of claim 1. 10. The programmable processor of claim 1, further comprising comparison means for evaluating the condition of the operand in one of scalar and vector modes. 11. A programmable processor according to claim 10, wherein said comparing means evaluates the condition of each operand to modify the sequence of instruction execution. 12. A first operand is conditionally moved from a first storage location to a second storage location based on said comparison means, said comparison means being such that the corresponding element in the first operand is moved. The programmable processor of claim 10, including a plurality of sub-comparators each comparing corresponding elements in the second and third operands to determine if they are done. 13. The programmable processor of claim 1, wherein the mode means is included as a field within each instruction so that each instruction specifies one of a vector and a scalar mode on an instruction-by-instruction basis. 14. The programmable processor of claim 13, wherein the mode means is included as a bit field within each instruction. 15. A data memory for storing an operand having at least one element in each operand, an instruction memory for storing an instruction for execution, an instruction means, and a plurality of arithmetic logic units (ALUs). ) Is a structure for performing a multi-data digital signal processing in a general-purpose computer coupled to a), and a) is coupled to the instruction memory and the instruction means, and the operand is in a vector mode or a scalar mode by the processing unit. Mode means for specifying in each instruction whether or not to process as one of: b) in response to said mode means, said ALU together with said ALU in the first mode as one unit And in the case of vector operands with each unit in the second mode A for selectively performing be operated independently 's operation unit and by
LU control means, c) coupled to the ALU control means and the ALU,
Carry condition means for selectively sending a carry condition between each of the ALUs for a scalar operand and ignoring the carry condition for each of the ALUs for a vector operand. A data memory for storing an operand having at least one element in the operand, an instruction memory for storing an instruction for execution, an instruction means, and a plurality of arithmetic logic units (ALUs). A configuration for performing multi-data digital signal processing in a general-purpose computer. 16. A data memory for storing an operand, each having at least one element therein, an instruction memory for storing an instruction for execution, an instruction means, and a first multiply accumulate. A structure for performing multiple data digital signal processing in a general-purpose computer coupled to a processor (MAC), comprising: a) being coupled to the instruction memory and the instruction means, the operands being in vector mode by the processing unit; Mode means for specifying in each instruction whether to be processed as one of the scalar modes, b) a plurality of MACs, c) coupled to each of the first and a plurality of MACs,
Responsive to said mode means, said first and plurality of MACs
For operating a plurality of data digital signals, each of which is operated independently of each other in the vector mode, and selectively operated together in the scalar mode. 17. Processing of operands by an ALU includes: a) a plurality of condition codes, each set of condition codes being combined with each independent element in the operand; and b) a selective combination of combinations in the operands. 16. The arrangement of claim 15, modified based on one of: c) and c) the one set of condition codes for the scalar operand. 18. The sequence of execution of the instructions comprises: a) each set of condition codes associated with each independent element in the operand; and b) multiple sets of condition codes in selective combinations. 16. The arrangement of claim 15, wherein one modifies the first instruction to a second instruction. 19. The operands are: a) each set of condition codes associated with each independent element in the operand, b) multiple sets of condition codes in selective combinations, and c) of the scalar operands. 19. The signal processor of claim 18, wherein the signal processor is selectively moved from a first storage location to a second storage location based on one of the set of condition codes for and. 20. a) further comprising a plurality of shifters for selectively operating as one integrated shifter in the scalar mode and as a plurality of shifters in the vector mode, each of the plurality of shifters , Responsive to said mode means in a first mode of operation, receiving an element from a vector operand as specified and processing it independently, said plurality of shifters being in a second mode of operation Responsive to the mode means, receiving a scalar operand and processing it together, and b) coupling the operand bits shifted to the scalar mode so that the plurality of shifters process the scalar operand. And including shifter control means for sending between each of the plurality of shifters in the vector mode. 16. The arrangement of claim 15, disabling sending shifted operand bits from each of the plurality of shifters. 21. A programmable processor for computing multiple data paths using a general purpose computer, comprising:
The general-purpose computer is coupled to the instruction memory, a data memory for storing an operand, a memory access bus for transferring an operand from the data memory, an instruction memory for storing an instruction for execution. Instruction means for fetching, decoding and ordering instructions, the programmable processor a) being coupled to the instruction means, wherein an operand from a data memory is one of a single data path mode and a multiple data path mode. Mode means for specifying in each instruction whether to be processed in one instruction, b) each data path includes an arithmetic unit, a multiply accumulator (MAC), and the programmable processor further comprises: c) In response to the mode means, the arithmetic unit in each data path is In order to selectively operate as a single unit in one mode in the case of a operand, and independently as an arithmetic unit in the case of a vector operand as each unit is in a different mode. Arithmetic control means, d) coupled to the arithmetic control means and the arithmetic units on each path, selectively sending a carry condition between each of the arithmetic units in the case of scalar operands, and vector operands And carry condition means for disabling the carry condition corresponding to each arithmetic unit, e) coupled to each MAC and responsive to the mode means,
A programmable processor including MAC control means for selectively operating each MAC independently of each other in the vector mode and operating them together in the scalar mode. 22. a) further comprising a plurality of shifters for selectively operating as one integrated shifter in the scalar mode and as a plurality of shifters in the vector mode, each of the plurality of shifters Responsive to said mode means in a first mode of operation, receiving an element from a specified vector operand and processing it independently, said plurality of shifters being in said second mode of operation Responsive to the means for receiving a scalar operand and processing it together, and b) coupling the operand bits shifted in the scalar mode to the shifter such that the plurality of shifters process the scalar operand. A shifter control means for transmitting between each of the plurality of shifters, the shifter control means comprising: 22. The programmable processor of claim 21, which disables sending shifted operand bits from each of the number shifters. 23. A method of digital signal processing using a programmable processor via multiple data paths, wherein the programmable processor operates on at least one operand, each having at least one element, the programmable processor comprising: Has a plurality of sub-processing units, the method comprising: a) supplying instructions from a predetermined sequence of instructions to be executed by the programmable processor; and b) the instructions by the programmable processor. Causing one of a scalar and a vector mode of processing on at least one operand, the scalar mode indicating to the programmable processor that there is one element in the at least one operand. The vector mode indicates to the programmable processor that there are multiple sub-elements in the at least one operand, the method further comprising: c) in scalar mode, each sub-processing unit of the programmable processor is Responding to commands,
Receiving and processing respective portions of said operands to produce partial and intermediate results, and d) each sub-processing unit sending its intermediate results among said plurality of sub-processing units and its partial results. Together with other sub-processing units to generate a final result for the operands; e) generate a first condition code to correspond to the final result; and f) in vector mode. , Each sub-processing unit of the programmable processor is responsive to the instruction, receives each sub-element from the plurality of sub-elements in the operand and processes it, each intermediate result being disabled and each part Generating partial and intermediate results with the explicit result representing the final result for its corresponding element, and g) a plurality of second conditions. The over-de, and a step of generating in a state corresponding to the result of each of independent, digital signal processing method. 24. A programmable processor for computing multiple data paths via a general purpose computer, comprising:
The general-purpose computer includes a data memory for storing operands, an instruction memory for storing program instructions, and instruction means, the programmable processor is coupled to the instruction means, and the operands from the data memory are Mode means for identifying whether to be treated as one of vector and scalar modes,
The vector mode determines a plurality of elements in each operand, the scalar mode determines a single element in the operands, and the programmable processor further includes a plurality of processing units coupled to the mode means and the data memory, Each processing unit receives a respective element of an operand and processes it to obtain partial result and propagation information, the programmable processor further operating in the vector mode and coupled to the processing unit, Sending each partial result as its final result of the processing of each element, vector means for ignoring propagation information, operating in said scalar mode and coupled to said processing unit, for each partial result and propagation information Together with scalar means for obtaining its final result of processing each operand,
Programmable processor. 25. Each processing unit comprises a set of condition codes for storing a processing condition, said set of condition codes comprising: a) each set individually in a first vector mode; and b) a second set. Modifying the processing of the programmable processor by one of each set in selective combination with another set in vector mode, and c) all sets of scalar operands combined in said scalar mode. Item 24. The processor according to Item 24. 26. The processor of claim 25, wherein each processing unit comprises at least one of: a) an arithmetic unit; b) a multiplication accumulator; c) a logical operator; and d) a barrel shifter. . 27. The programmable processor of claim 1, wherein the mode means is specified by a bit field in the at least one operand. 28. The at least one mode means comprises:
Specified by the way the two operands are selected,
The programmable processor according to claim 1. 29. The mode means comprises the at least one
3. A bit field located in a memory location that further specifies the address of one operand.
8. The programmable processor according to item 8. 30. Responsive to the mode means, further comprising third vector means for processing each respective element of the first operand in vector mode with the second operand in scalar mode. The programmable processor according to claim 2.