SE7901812L - ELECTRONIC TREATMENT SYSTEM - Google Patents

ELECTRONIC TREATMENT SYSTEM

Info

Publication number
SE7901812L
SE7901812L SE7901812A SE7901812A SE7901812L SE 7901812 L SE7901812 L SE 7901812L SE 7901812 A SE7901812 A SE 7901812A SE 7901812 A SE7901812 A SE 7901812A SE 7901812 L SE7901812 L SE 7901812L
Authority
SE
Sweden
Prior art keywords
microprocessor
bus
pair
processing
unit
Prior art date
Application number
SE7901812A
Other languages
Unknown language ( )
Swedish (sv)
Other versions
SE439701B (en
Inventor
G Sofi
R Cedolin
W Chiarottino
G Giandonato
S Villone
S Giorcelli
G Martinengo
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Publication of SE7901812L publication Critical patent/SE7901812L/en
Publication of SE439701B publication Critical patent/SE439701B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1654—Error detection by comparing the output of redundant processing systems where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1633—Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1683—Temporal synchronisation or re-synchronisation of redundant processing components at instruction level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1691—Temporal synchronisation or re-synchronisation of redundant processing components using a quantum
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.
SE7901812A 1978-03-03 1979-02-28 MULTI-CONFIGURATIVE MODULE PROCESSING UNIT SE439701B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT67447/78A IT1111606B (en) 1978-03-03 1978-03-03 MULTI-CONFIGURABLE MODULAR PROCESSING SYSTEM INTEGRATED WITH A PRE-PROCESSING SYSTEM

Publications (2)

Publication Number Publication Date
SE7901812L true SE7901812L (en) 1979-09-04
SE439701B SE439701B (en) 1985-06-24

Family

ID=11302453

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7901812A SE439701B (en) 1978-03-03 1979-02-28 MULTI-CONFIGURATIVE MODULE PROCESSING UNIT

Country Status (12)

Country Link
US (1) US4366535A (en)
JP (1) JPS5935057B2 (en)
BE (1) BE873220A (en)
BR (1) BR7901049A (en)
CA (1) CA1121513A (en)
DE (1) DE2908316C2 (en)
ES (1) ES478130A1 (en)
FR (1) FR2418989B1 (en)
GB (1) GB2016176B (en)
IT (1) IT1111606B (en)
NL (1) NL184297C (en)
SE (1) SE439701B (en)

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US5295258A (en) * 1989-12-22 1994-03-15 Tandem Computers Incorporated Fault-tolerant computer system with online recovery and reintegration of redundant components
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US6173357B1 (en) * 1998-06-30 2001-01-09 Shinemore Technology Corp. External apparatus for combining partially defected synchronous dynamic random access memories
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US6691257B1 (en) 2000-04-13 2004-02-10 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus protocol and method for using the same
US6820213B1 (en) 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
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Also Published As

Publication number Publication date
DE2908316C2 (en) 1984-10-25
IT7867447A0 (en) 1978-03-03
BR7901049A (en) 1979-11-20
BE873220A (en) 1979-04-17
ES478130A1 (en) 1979-05-16
NL7901708A (en) 1979-09-05
CA1121513A (en) 1982-04-06
GB2016176B (en) 1982-08-25
FR2418989B1 (en) 1987-11-13
GB2016176A (en) 1979-09-19
NL184297C (en) 1989-06-01
SE439701B (en) 1985-06-24
JPS54124652A (en) 1979-09-27
US4366535A (en) 1982-12-28
DE2908316A1 (en) 1979-09-06
JPS5935057B2 (en) 1984-08-27
IT1111606B (en) 1986-01-13
FR2418989A1 (en) 1979-09-28
NL184297B (en) 1989-01-02

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