CN105612494A - Data processing apparatus and method for controlling performance of speculative vector operations - Google Patents

Abstract

A data processing apparatus and a method of controlling performance of speculative vector operations are provided. The apparatus comprises processing circuitry for performing a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements, and speculation control circuitry for maintaining a speculation width indication indicating the number of vector elements of each vector operand to be subjected to the speculative vector operations. The speculation width indication is set to an initial value prior to performance of the sequence of speculative vector operations. The processing circuitry generates progress indications during performance of the sequence of speculative vector operations, and the speculation control circuitry detects, with reference to the progress indications and speculation reduction criteria, presence of a speculation reduction condition. The speculation reduction condition is a condition indicating that a reduction in the speculation width indication is expected to improve at least one performance characteristic of the data processing apparatus relative to continued operation without the reduction in the speculation width indication. The speculation control circuitry is responsive to detection of the speculation reduction condition to reduce the speculation width indication. This can significantly increase performance (for example in terms of throughput and/or energy consumption) when performing speculative vector operations.

Description

Data processing device and method for controlling performance of speculative vector operations

technical field

The present invention relates to a data processing device and method for controlling performance of speculative vector operations.

Background technique

One known technique for increasing the performance of data processing devices is to provide circuitry to support the execution of vector operations. A vector operation is performed on at least one vector operand, where each vector operand includes a plurality of vector elements. Thus, performance of a vector operation involves repeatedly applying an operation to multiple vector elements within one or more vector operands.

In a typical data processing system that supports the performance of vector operations, a bank of vector registers will be provided for storing vector operands. Thus, for example, each vector register within a vector register bank may store a vector operand comprising a plurality of vector elements.

In high-performance implementations, it is also known to provide vector processing circuitry (often referred to as Single Instruction Multiple Data (SIMD) processing circuitry) that can execute all operations in parallel on multiple vector elements within a vector operand. need to calculate. In an alternative embodiment, scalar processing circuitry can still be used to perform vector operations, but in this case, the vector operations are performed by iteratively performing operations through the scalar processing circuitry, each iteration of the vector operand Operate on different vector elements.

Through the use of vector operations, significant performance benefits can be realized compared to the performance of an equivalent series of scalar operations.

When trying to obtain the performance benefits of vector processing, it is known to try to vectorize a series of scalar operations in order to replace them with an equivalent series of vector operations. For example, for a loop containing a sequence of scalar instructions, it is possible to vectorize the loop by replacing the sequence of scalar instructions with an equivalent sequence of vector instructions, where the vector operands contain elements associated with different iterations of the original scalar loop as vector elements.

Nevertheless, while this approach can be effective if the required number of iterations through the original scalar loop is predetermined, it is more difficult to vectorize such a loop when the number of iterations is not predetermined. In particular, since the number of iterations is not predetermined, it is not predetermined how many vector elements will be required in each vector operand.

In some cases of the type described above, it is possible to perform speculative vector processing in which the required number of vector elements is guessed, and corrective action is taken later when the exact number of vector elements required is determined.

KAsanovic's doctoral dissertation titled "Vector Microprocessors" (Berkeley College, 1998, pp. 116-121) discusses performing speculation on the entire width of vector operands, and additionally tracking what happens during speculation Schema events (such as page faults). This architectural event will trigger an exception, causing the operating system to execute an exception routine in order to resolve the exception. The proposed method records the position of each vector element within the width of the vector where the architectural event was detected. Then, when a commit point is reached where the set of required vector element positions is known, each required vector element position is compared to this record of architectural events. Any such delay exception is triggered at the commit point because any architectural event associated with the desired vector element location would prevent the vector processing circuitry from correctly performing the vector operation. If none of the required set of vector element positions is associated with a fabric event, then update the vector length and mask, and clear the record of the fabric event.

The above process allows speculative vector processing to be performed while ensuring correct operation by masking architectural events at commit points.

Nonetheless, while the methods described above may ensure correct operation while performing speculative vector processing operations, there are other factors that may affect the benefits of performing speculative vector processing. As mentioned earlier, when performing speculation, the number of iterations required is unknown, and therefore there is the possibility of performing certain operations that may adversely affect the performance characteristics of the device (such as yield or energy consumption), only at a slight Later, it was found that those operations were not needed. Therefore, it would be desirable to provide a mechanism for performing speculative vector operations while managing the impact of such speculative vector processing on the performance characteristics of the device.

Contents of the invention

As seen from a first aspect, the present invention provides a data processing apparatus comprising: processing circuitry configured to perform a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements; Speculation control circuitry configured to maintain a speculation width indication indicating the number of vector elements in each vector operand that will be subject to the speculative vector operations, the speculation width indicating at the end of the sequence of speculative vector operations initialized to initial values prior to execution; the processing circuitry configured to generate a progress indication during execution of the speculative vector operation sequence; speculation control circuitry further configured to detect speculation by reference to the progress indication and the speculation reduction criteria the existence of a reduction condition, the speculative reduction condition being a condition indicating that reduction of the speculative width indication is expected to improve at least one performance characteristic of the data processing device relative to successive operations without reduction of the speculation width indication; the speculative control circuit The system further shrinks the speculation width indication in response to detection of the speculation shrinkage condition.

By configuring the processing circuitry to generate an indication of progress during execution of a sequence of speculative vector operations, this allows the speculative control circuitry to scale down criteria relative to speculation (these criteria may be fixed or may be stored for use by the speculative control circuitry). System Access and Reconfigurable Criteria) evaluates those progress indicators to determine situations where the current speculation width appears to have a significant adverse effect on selected performance characteristics (eg, throughput or power consumption) of the data processing device. Upon detection of this, the speculation control circuitry is then configured to reduce the speculation width indication, thereby reducing the number of vector elements in each vector operand that will be subject to a speculative vector operation.

Typically, the progress indicators will be arranged so as to allow the speculative control circuitry to identify any vector element locations where performance of speculative vector operations adversely affects performance characteristics. For example, each progress indication may specifically identify the vector element position to which the progress indication is associated.

By way of example only, if the progress indication identifies that a particular vector element to be loaded from memory at element location x during execution of a speculative vector load operation has resulted in a cache miss at a cache level within the system's cache hierarchy, The speculative shrinkage criteria may then identify the expected latency to be associated with such a cache miss event, or may directly identify the occurrence of such an event indicating a speculative shrinkage condition. Although speculative vector processing can continue correctly at the currently specified speculative width, this can significantly affect performance due to the latency introduced by cache misses, and by reducing the speculative width here to exclude element position x and higher to avoid this latent time. The sequence of vector operations can then be repeated if desired to try to perform the vector operations on the omitted vector elements, and may not have the same latent-time problem until the time at which the sequence of vector operations is repeated (e.g., before that time, all The required data element may exist in the cache, and thus may not generate a cache miss).

Thus, through use of the present invention, at least one performance characteristic of a data processing device may be performed while performing speculative vector operations, by managing to avoid situations where performing speculative vector operations with a particular speculation width would have an adverse effect on the selected performance characteristic And be improved.

Progress indicators can take many forms. In one embodiment, the progress indication indicates a yield impacting event that occurred within the processing circuitry during execution of the speculative vector operation. Alternatively or additionally, the progress indication may indicate an energy consumption impacting event occurring within the processing circuitry during execution of the speculative vector operation. Although in one embodiment the impact events indicated by the progress indications are events that have a negative impact on the performance characteristic, in one embodiment the impact events may also identify events that have a positive impact on the performance characteristic, such as more than expected Perform specific operations faster or consume less energy.

The event that triggers the generation of the progress indication can take a variety of forms. In one embodiment, at least some of the progress indications are issued in response to microarchitectural events occurring within the processing circuitry during execution of the speculative vector operations.

If a feature, component, or behavior of a processor affects only the quality of the implementation (such as causing the processor to use more or less time or energy to execute a program) rather than the correctness of the implementation (that is, whether the instruction set architecture is implemented correctly) , the features, components, or behaviors of a processor can be considered a "microarchitecture." For example, modern processors use branch predictors to speed up branches, caches to speed up memory reads, write buffers to speed up memory writes, transform lookaside buffers to speed up page table lookups, and pipelines to speed up Execution of a sequence of instructions. All of these features can be considered microarchitectural features because they speed up execution without affecting the final output of the program.

This shall be in contrast to processor features, components, or behaviors that affect implementation correctness, which are considered "architecture". For example, modern processors use page tables and page fault exceptions to implement virtual memory, interrupts to support context switching, and arithmetic exceptions to handle arithmetic error conditions such as "divide by zero". Architectural features, components, or behaviors generate architectural events that typically affect program execution, such as by causing additional instructions to be executed. In contrast, microarchitectural features, components, or behaviors generate microarchitectural events that affect the behavior of the microarchitecture, but have no effect on the architecture level. These microarchitectural features, components, or behaviors may, for example, cause a program to run slightly slower than otherwise, but do not affect program execution.

The speculative width indication may take a variety of forms. For example, the speculative width indication may be specified by a mask or by the contents of one or more registers identifying a particular element position, such as a start element position and/or an end element position. In one embodiment, the speculation width indication not only indicates the number of vector elements in each vector operand that will be subjected to the speculative vector operation, but further identifies the first vector element in each vector operand that will be subjected to the speculative vector operation.

Although the number of vector elements that will be subject to a speculative vector operation need not occupy a series of contiguous vector element positions, in one embodiment the speculative width indication does place the number of vector elements that will be subject to that speculative vector operation in each vector operand Identifies the specified number of sequential vector elements starting from the first vector element.

In one embodiment, the processing circuitry is configured to execute an instruction vector loop comprising instructions defining the sequence of vector operations and at least one evaluation instruction executed at a commit point within the vector loop after execution of the sequence of vector operations , the execution of the at least one evaluation instruction results in a determination of the required vector width. Further, the speculation control circuitry is responsive to the determination of the desired vector width to determine whether execution of the sequence of vector operations results in over-speculation or under-speculation by referring to a current value indicated by the speculation width, and if under-speculation occurs, setting A repeat flag is set to enable further iterations of the instruction vector loop to be performed. Thus, the speculation width may be varied during execution of a speculative vector operation as necessary, and subsequent iterations of the sequence of speculative vector operations are performed as necessary to ensure that eventually the vector operation is performed on all required vector elements.

In one embodiment, after a further iteration of the instruction vector loop, the speculation control circuitry is configured to initialize the speculation width indication to the revised the initial value of .

In one embodiment, where the vector loop includes one or more non-speculative instructions to be executed after the commit point, the speculative control circuitry is further configured to set mask values to identify each vector operand that will be subject to the one or more The number of vector elements for non-speculative operations defined by non-speculative instructions. In one embodiment, if under-speculation occurs, the mask will be set to identify the value of the speculative width that exists at the commit point, and if over-speculation occurs, the mask will be set to identify the value of the speculative width at the commit point Determine the desired vector width.

In one embodiment, a data processing apparatus includes a vector register bank configured to store vector operands for access by processing circuitry, and the processing circuitry includes data access circuitry configured to Vector access operations are performed to move vector operands between a vector register bank and a memory system including at least one level of cache memory. In this embodiment, the data access circuitry may be configured to issue information related to cache misses that occur during execution of the vector access operation as an indication of progress. Such cache misses can have significant latency and thus provide useful information when deciding whether to reduce the speculation width.

In one embodiment, the data processing apparatus further includes a translation lookaside buffer (TLB), the data access circuitry refers to the TLB during execution of a vector access operation, the data access circuitry is further configured to issue and Information about TLB misses that occur during the execution of a vector access operation as an indication of progress. A TLB miss can also generate significant latency because in this case a "page table move" process may have to be performed in order to fetch the required page table information from memory for storage in the TLB, thus, the indication of a TLB miss Also provides useful information when deciding whether to reduce the speculation width.

Although the above two examples of progress indications relate to the activity of the data access circuitry, it will be appreciated that other components of the processing circuitry may also be arranged to provide progress indications to the speculative control circuitry. In fact, in addition to progress indications issued by processing circuitry performing speculative vector operations, progress indications may also be issued by other components within the system, such as scalar circuitry configured to perform scalar operations, because the speculative Vector operations may have performance impacts on those other components within the system. For example, if a speculative loop contains a large number of operations (whether vector or scalar), those operations will have to be repeated if the speculative width is reduced too much. Tracking the number of scalar and vector operations performed allows this potential repetition cost to influence the decision to reduce the speculation width.

In one embodiment, the data processing circuitry changes the number of vector elements per vector operand that are subject to selected vector operations that occur in the sequence from A vector operation is initiated, and the progress indication of the vector operation results in the detection of a speculative reduction condition that causes the speculative width indication to be reduced. In a particular embodiment, the selected vector operation includes a vector operation whose progress indication results in a speculative width reduction and all vector operations following that vector operation in sequence.

Furthermore, in one embodiment, this method can be extended to additionally vary the number of vector elements in each vector operand that are subject to outstanding vector operations that occur before a vector operation in the sequence that The progress indication of the operation results in the detection of a speculative reduction condition that causes the speculative width indication to be reduced. Thus, this approach allows retrospective trimming of the number of vector elements that were subject to previously initiated vector operations that were still in progress at the time of the reduced speculation width indication. This can thereby reduce the energy consumption otherwise consumed in completing those previously initiated speculative vector operations.

In one embodiment, the data processing apparatus further includes control circuitry configured to reduce power consumption within one or more components of the processing circuitry in response to the reduction of the speculation width indication. This can be accomplished in a number of ways, but in one embodiment, the control circuitry employs at least one of clock gating and power gating to reduce power consumption within the one or more components. Thus, if a clock gating mechanism is used, certain components within the processing circuitry can have their clock signals removed in order to prevent these components from being consumed in the execution of speculative vector operations that are now at element locations outside the modified speculative width. power. In some cases, power gating may instead be used to remove power supply from associated components. In one embodiment, the control circuitry may be configured to continuously receive an indication of the current speculation width, or may be configured to receive an indication only when the speculation width has changed.

There are several ways to specify the initial value of the speculative width indicator and the speculative reduction criteria. For example, in one embodiment at least one of an initialized initial value of the speculation width indication and a speculation reduction criterion are specified by instructions to be executed by the data processing apparatus. The instruction may be one of the instructions executed by the processing circuitry, or indeed may be a specific instruction executed by the speculative control circuitry, such as an instruction to enable speculation. In an alternative embodiment, the predetermined speculation width indicates at least one of an initialized initial value and a speculation reduction criterion.

In yet another embodiment, the data processing apparatus may further include predictive circuitry configured to maintain historical data about speculative width values for speculative vectors previously executed by the processing circuitry at the commit point sequence of operations. The predictive circuitry may then be configured for the current sequence of speculative vector operations to be performed by the processing circuitry to refer to historical data to determine an initial value for setting the speculative width indication prior to performing the current sequence of speculative vector operations. Alternatively or additionally, the predictive circuitry may maintain historical data regarding the speculative reduction criteria used for previous sequences of speculative vector operations and then refer to the historical data to determine the speculative reduction criteria to be used for the current sequence of speculative vector operations.

The sequence of speculative vector operations can be identified in a number of ways. For example, an instruction set may include non-speculative and speculative versions of certain vector instructions so that certain instructions can be unambiguously identified as speculative. Alternatively, the data processing apparatus may be configured to enter and exit a speculative computing mode, in which all instructions encountered within a speculative computing method are executed speculatively. In one embodiment that supports such a speculative mode of operation, the speculative control circuitry triggers the speculative mode of operation in response to beginning execution of a speculative instruction, and the processing circuitry is configured to respond to instructions executed during the speculative mode of operation. Perform speculative vector operations.

In one such embodiment, the speculative control circuitry is further responsive to execution of the committed instruction to terminate the speculative mode of operation.

In one embodiment, the speculation control circuitry modifies the speculation width indication to indicate that at least one vector element in each vector operand is to be subjected to a speculative vector operation in response to the speculation reduction condition. This ensures that progress is always positive by placing a minimum limit on the speculative width indication to process at least one vector element in each vector operand. When the speculation width indicates that a single vector element is identified, this is actually the case when no speculation is being performed.

Although the speculative shrinkage criteria may directly specify one or more criteria that, if satisfied, indicate the existence of a speculative shrinkage condition, alternatively or additionally, the speculative shrinkage criteria may include performance margin information maintained by the speculative control circuitry, speculatively The control circuitry is configured to adjust the performance margin information taking into account an indication of progress generated during execution of the sequence of speculative vector operations. In one such embodiment, the performance margin information can be viewed as providing an indication of available slack of how performance characteristics are affected during the processing of speculative vector operations, which is then adjusted according to received progress indications . In one embodiment, the progress indicator may only indicate events that have a negative impact on the selected performance characteristic, thus, the slack indicator will only be adjusted in one direction. However, in alternative embodiments, progress indicators may indicate events that have both negative and positive impacts, and in such embodiments, slack indicators may be adjusted bi-directionally. Regardless of how the performance margin information (slack indication) is adjusted, the speculative control circuitry can be configured to detect a speculative reduction condition if the performance margin information reaches a trigger point.

In one embodiment, the speculation control circuitry references the performance margin information when submitting the speculation width indicating the amount by which it will be reduced. This enables the amount of speculative width reduction to be dynamically managed taking into account the extent to which performance tolerances are exceeded.

Alternatively, the amount by which the speculative width indication will be reduced when a speculative reduction condition is detected may be predetermined. This amount can be predetermined by identifying a preset number of element positions by which the speculative width will be reduced, or by identifying a particular rule used in determining how to adjust the speculative width.

As seen from a second aspect, the present invention provides a method of controlling the performance of speculative vector operations, the method comprising: performing a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements; A speculative width indication of the number of vector elements to be subjected to the speculative vector operation, the speculative width indication being initialized to an initial value prior to execution of the speculative vector operation sequence; a progress indication generated during execution of the speculative vector operation sequence; referring to progress Indicating and speculative reduction criteria to detect the presence of a speculative reduction condition, the speculative reduction condition being a condition indicating that reduction of the speculative width indication is expected to improve data processing equipment relative to successive operations without reduction of the speculation width indication at least one performance characteristic of; and shrinking the speculative width indication when the speculative shrinking condition is detected.

As seen from a third aspect, the present invention provides a computer program product storing in non-transitory form a computer program for controlling a computer to provide a data processing device corresponding to the first aspect of the present invention. The virtual machine execution environment for program instructions.

As can be seen from the fourth aspect, the present invention provides a data processing device comprising: processing means for performing a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements; speculative control means for maintaining a speculative width indication indicating the number of vector elements to be subjected to the speculative vector operation in each vector operand, the speculative width indication being initialized to an initial value prior to execution of the speculative vector operation sequence; the means for processing in the A progress indication is generated during the execution of the sequence of speculative vector operations; speculation control means for detecting the presence of a speculative reduction condition with reference to the progress indication and a speculative reduction criterion, the speculative reduction condition being a condition indicating: relative to the speculative width indication Reduction of the speculative width indication is expected to improve at least one performance characteristic of the data processing device for consecutive operations without reduction; speculative control means for responding to detection of the speculative reduction condition by reducing the speculation width indication.

Description of drawings

The invention will be further described, by way of example only, by reference to embodiments thereof, as illustrated in the accompanying drawings, in which:

Figure 1 is a block diagram of a data processing device according to one embodiment;

2A-2C schematically illustrate various control registers provided within the speculative control circuitry in FIG. 1 according to one embodiment;

Figure 3 schematically illustrates a scalar instruction loop that can be vectorized using techniques of embodiments described herein;

Figures 4 and 5 schematically illustrate vector instruction sequences used to vectorize the scalar loop in Figure 3 according to one embodiment;

Figure 6 is a flow diagram schematically illustrating the manner in which speculation width is reduced according to one embodiment during execution of a sequence of speculative vector operations;

Figure 7 is a flowchart illustrating the steps performed when initiating speculation according to one embodiment;

Figure 8 is a flowchart illustrating the steps taken during the submission process according to one embodiment;

Figure 9 is a flowchart illustrating the steps performed during the execution of a sequence of vector operations during the conditional exit phase, according to one embodiment;

Figures 10A and 10B schematically illustrate how the operation of shelving speculative vector operations may be changed after speculation width reduction, according to certain embodiments;

Figures 11A and 11B schematically illustrate how the operation of shelving speculative vector operations may be changed after speculation width reduction, according to yet another embodiment;

12A and 12B schematically illustrate what can be achieved when using the techniques of embodiments described herein (FIG. 12B), compared to the performance of speculative vector operations without using the techniques of embodiments described herein (FIG. 12A). potency difference;

Figure 13 is a flow diagram illustrating how speculation width may be adjusted in an embodiment in which the reduction criteria includes performance margin information in the form of a slack indication, according to one embodiment;

Figures 14A and 14B schematically illustrate how the slack indication may vary when the method of Figure 13 is employed, according to two embodiments; and

Fig. 15 schematically illustrates a virtual machine implementation of a data processing device according to an embodiment.

detailed description

Fig. 1 illustrates a part of a data processing device 5 according to an embodiment. The figure only shows the vector processing portion, and there may also be scalar processing circuitry, scalar load/store units, and scalar register banks so that vector and scalar instructions can be decoded and executed.

An instruction queue 10 is provided which holds instructions to be executed which are routed to decoding circuitry 20 which is arranged to decode the instructions and send control signals to the appropriate circuits within the apparatus of FIG. 1 . In particular, for general vector processing instructions, decode circuitry 20 issues control signals to associated vector processing units 35 within vector processing circuitry 30, which then store references in vector register bank 40 One or more vector source operands to perform the desired vector processing operations. Typically, the results of those operations are also stored back into the vector register bank 40 as one or more vector destination operands. As schematically shown in FIG. 1 , the vector processing unit may take various forms, such as one or more arithmetic logic units (arithmetic logic unit; ALU), floating point unit (floating point unit; FPU) and the like.

For any vector data access instructions, decoding of those instructions will cause control signals to be issued to vector load/store unit 50 within vector processing circuitry 30, which is configured so that one or more data operands are Movement between the vector register bank 40 and the cache/memory (cache/memory is referred to herein as the memory system) is in either direction in both directions. As illustrated for purposes of illustration, the memory system may include a hierarchical cache structure consisting of a level 1 cache 72, a level 2 cache 74, and possibly more caches located between the vector register bank and main memory 76. composed of grades.

If the vector data access instruction is a vector load instruction, the load/store unit 50 will load at least one vector operand from the memory system to the vector register bank 40 . Likewise, if the vector data access instruction is a vector store instruction, the load/store unit 50 will store at least one vector operand from the vector register bank 40 to the memory system.

According to embodiments described herein, processing circuitry 30 may be arranged to perform a sequence of speculative vector operations, speculative control circuitry 60 is provided to maintain a speculative width indication indicating the number of vector elements in each vector operand that will be subject to speculative vector operations . In particular, the speculation control circuitry has a number of control registers 65 that control the information delivered to the vector processing circuitry 30 via path 82. In one embodiment, the state of those control registers identifies when the speculative operation is performed and The current speculation width is also identified.

In the embodiment illustrated in FIG. 1, the sequence of instructions stored in instruction queue 10 will include a start speculative instruction which, when decoded by decode circuitry 20, will cause control signals to be issued to the speculative control circuit. The system 60 is enabled in speculative computing mode. Specifically, in one embodiment, speculative control circuitry 60 will respond to such a control signal by setting a speculative flag in control register 65 to identify that speculative mode is currently active. This information will then be routed to vector circuitry 30 via path 82, and any subsequent operations to be performed by vector processing circuitry 30 based on control signals received from decode circuitry 20 will then be performed speculatively until the speculative operation until the mode is exited. In one embodiment, speculative mode is exited via committing an instruction that, when decoded by decode circuitry 20, causes a control signal to be sent to speculative control circuitry 60, causing the control circuitry to clear the speculative flag.

While specific speculative modes of operation are provided in the described embodiments, no specific speculative mode of operation is required. Rather, in alternative embodiments, speculative and non-speculative versions of at least a subset of instructions in an instruction set may be provided such that individual instructions within a sequence may be speculatively executed.

For any speculative operations performed by vector processing circuitry 30, a speculative width indication is delivered via path 82 from control register 65 within speculative control circuitry 60 to identify the vectors of each vector operand that will be subjected to those speculative vector operations number of elements. When speculation is enabled, the speculation width indication will be initialized to an initial value, which in one embodiment may be, for example, the entire vector width of the operand. Therefore, for example only, if the vector operand contains 16 vector elements, the initial value of the speculative width indicator may be set to 16.

During execution of speculative vector operations, processing circuitry 30 is arranged to issue progress indications to speculative control circuitry 60 via path 80 . Progress indicators provide information about the progress of operations being performed by the vector processing circuitry. Although a progress indication can be issued in a variety of ways, in one embodiment, several events within the vector processing circuitry cause the output of a progress indication. In one embodiment, these progress indicators will indicate yield impacting events and/or energy consumption impacting events. In one embodiment, these events are of the type that have a negative impact on yield or energy consumption. However, in alternative embodiments, such as those described later with reference to FIG. 13 , these events may also include events that have a positive impact on yield or energy consumption.

The types of events that generate such progress indications can take many forms, but in one embodiment, these events are microarchitectural events that occur within processing circuitry 30 during the execution of speculative vector operations. As discussed above, such microarchitectural events only affect the quality of the implementation (eg, causing the processing circuitry to use more or less time or energy in executing the program containing the instructions being executed), not the correctness of the implementation. Thus, the existence of a microarchitectural event does not in itself require changes to circuitry operation. However, as will be discussed in more detail below, according to the described embodiments, the speculative control circuitry uses the progress indication in order to determine whether a reduction in speculative width is likely to occur relative to continuing operations without such a reduction in speculative width. At least one performance characteristic of the data processing device is improved.

In particular, speculative control circuitry 60 has access to reduction criteria 70, which may be fixed criteria, or may be configurable, eg, via execution of instructions within an instruction stream. There are several ways to specify the reduction criteria. For example, speculative reduction criteria may identify expected latencies and/or energy consumption that will be associated with certain events reported via progress indications, speculative control circuitry 60 maintains latencies and/or energy consumption associated with events received over time. Energy consumption tags and speculative reduction conditions are detected when a certain trigger point is reached. Alternatively, narrowing criteria 70 may directly identify certain events that, when present, indicate the existence of a presumed narrowing condition.

Speculation control circuitry 60 is configured to reduce the speculation width via analysis of progress indications received via path 80 against reduction criteria 70 when a speculation reduction condition is detected, at which point the contents of control register 65 are updated To recognize the reduced speculation width, the new speculation width is forwarded to vector processing circuitry 30 via path 82 . This will allow vector processing circuitry 30 to reduce the number of vector elements subject to ongoing vector processing operations. In particular, at least the vector operations performed after the operation that produced the progress indication that resulted in the speculative width reduction will generally be performed on a reduced number of vector elements. In one embodiment, the reduced speculation width may also be applied to the operation, assuming the operation that generated the progress indication that caused the speculation width reduction to occur is still in progress. In addition, in one embodiment discussed below with reference to FIG. 10B , the speculative width reduction can also affect any vector operations that were still in progress when the reduction occurred, even if those operations were producing indications of progress that reduced the speculation width. The same is true for those emitted before the operation.

By using the progress indication to detect situations where successive operations with the current speculation width may have an adverse effect on performance characteristics such as throughput or energy consumption, the speculation control circuitry can then reduce the speculation width in an attempt to avoid this effect. If it is subsequently determined that the required vector element width is greater than the reduced speculative width, any vector elements excluded from the speculative operation due to this reduced speculative width may thus be the subject of subsequent iterations of the speculative vector operation.

To reduce energy consumption of vector processing circuitry 30 as the speculation width is reduced, clock/power gating circuitry 92 may optionally be provided, or may be arranged to receive an indication of the current speculation width via path 90 . Based on the current speculation width information, clock/power gating circuitry may vary the clock or power supplied to various components within vector processing circuitry 30 . For example, if it is determined that certain components within the processing circuitry do not need to perform any operations for one or more clock cycles due to the reduced speculation width, the clock signal may be removed from those components to reduce the power consumed by those components. If those components are not needed for longer periods of time, it may be appropriate to put them in a low power operating mode by removing or reducing the voltage supply to those components if the device supports dynamic voltage scaling techniques.

Any component within the vector processing circuitry may be arranged to generate an indication of progress via path 80 . However, considering events that may have an adverse impact on throughput, these events are often associated with cache misses that occur when a load or store operation is performed using a vector load/store unit (LSU) 50 . In particular, if, while performing a vector load or store operation, the LSU detects a cache miss in either the L1 cache 72 or the L2 cache 74 associated with a particular vector element location, the LSU may be sent via path 80 A progress indicator identifying in which cache level the miss was detected and the element location where the cache miss occurred. Thus, the speculation control circuitry can use this information, in association with the reduction criteria 70, to determine whether to reduce the speculation width. Reduction criteria may, for example, recognize that any level 2 cache misses (which typically result in significant latency) will cause the speculation width to be reduced to exclude vector element locations that produced level 2 cache misses. Alternatively, narrowing criteria 70 may effectively provide different criteria for different element positions. For example, as element positions within a vector increase, this represents a higher degree of speculation, whereby while cache misses associated with higher element positions immediately reduce the speculative width, those associated with lower element positions A cache miss does not require a reduction in the speculative width.

Data processing systems often use virtual addresses when accessing memory, and the TLB store 55 is used to convert those virtual addresses into physical addresses for accessing the memory system. It will be readily understood that TLB store 55 has several entries that identify specific virtual addresses, information used to translate each virtual address into a physical address, and certain information such as whether those addresses are cacheable or cacheable memory regions. some license attribute information. The LSU will thus issue a virtual address to the TLB store, and if a hit to the virtual address is detected in the TLB store, the required physical address and permission attribute information can be immediately returned to the LSU. However, in the event of a miss, the TLB store will generally need to perform a page table movement process to retrieve the page table from the memory system containing the necessary information to enable the translation of virtual addresses into physical addresses and provide associated permission attributes. During this process, TLB store 55 will access L1 cache 72 and lower levels of memory as needed in order to retrieve the required page table information. If a cache miss occurs during the process, this can again be reported via path 80 as an indication of progress to the speculation control circuitry and used by the speculation control circuitry to determine whether to reduce the speculation width.

In one embodiment, the initialization initial value of the speculation width indication and the speculation reduction criterion may be predetermined. However, both may alternatively be specified by at least one of the instructions executed by the data processing device. For example, a start speculation instruction may identify an initial speculation width to be set in control register 65 . The instruction may also identify certain speculative reduction criteria to be used by the speculative control circuitry 60 when evaluating whether to reduce the speculative width during execution of a speculative vector operation. As another option, speculative estimation circuitry 85 may be provided for maintaining historical data regarding the speculative width values and/or speculative reduction criteria for previous sequences of speculative vector operations. For speculative width values, historical data may identify the final speculative width value at the commit point during the execution of a previous sequence of speculative vector operations. Prediction circuitry may thus be arranged to receive a program counter value associated with the instruction that initiated speculation, and to refer to historical data based on that program counter value, taking into account any previous sequence of speculative vector operations initiated from that program counter value. , to determine an initial value for the speculation width indication and, if necessary, the speculation reduction criteria to use. The historical data will be stored in historical storage 87 accessible by speculative estimation circuitry 85 .

Although in FIG. 1 progress indications are shown as being issued by vector processing circuitry 30 only, in alternative embodiments speculative control circuitry 60 may receive progress indications from elsewhere within the system, such as from scalar processing circuitry The system receives.

The control register 65 can take a variety of forms. Labeled FIG. 2A illustrates several parameters that can be stored in the control register. First, a speculative width value of 100 is maintained, and in one embodiment, this value may take a value between 1 and 16, which indicates that the number of vector elements to be subjected to a speculative vector operation in each vector operand may be between 1 and 16. Change between 16 vector elements (in one embodiment, 16 vector elements represent the full width of the vector operand).

In one embodiment, the control register 65 also includes a speculation flag 105 that is set to indicate whether speculation is on or off. When speculation is off, vector operations are performed non-speculatively. However, when speculation is turned on, vector operations are performed speculatively.

Speculative width indication 100 may be specified in a variety of ways. However, in one embodiment, the control registers 65 include both the first element position register 110 and the speculative width register 115 . The first element position register 110 identifies the first vector element position to be subjected to a vector processing operation, while the speculative width register 115 identifies the final vector element position, and the difference between the contents of these two registers then indicates the position of the vector element within the vector operand 120. The inferred width of .

During a first iteration of a sequence of vector operations, it may be that the first element position register points to the first vector element within vector 120, and the speculative width register 115 may, for example, point to the last vector element, thereby specifying the overall vector width. During execution of a vector operation, the speculation width register content may be reduced to identify the reduced speculation width. If, by the time the commit point is reached, the speculation width has shrunk below the required number of vector elements determined at the commit point, then a subsequent iteration of the vector operation may be performed, at which point the first element position register 110 will be set to identify the The first desired vector element processed iteratively via a previous speculative vector operation. The speculation width register 115 will then be set to identify the speculation width required for subsequent iterations.

Although in the example of FIG. 2B two separate registers are maintained, in an alternative embodiment, mask register 130 may be provided to recognize speculation width indications. In particular, the mask may include bits for each element position within the vector operand 120, those bits set to zero or one to identify the speculation width. In one embodiment, the speculation width will be specified by a series of logic 1 values contained within the mask by identifying a reduced speculation width by transitioning some of those logic 1 values to logic 0 values, when the speculation width When shrinking, the contents of this mask are updated during operation execution. It will be appreciated that in alternative embodiments, the meaning of the logic 1 and logic 0 values within the mask may be reversed.

Figure 3 schematically illustrates a scalar loop that can be vectorized by using the embodiments described above. This loop of scalar instructions includes a series of instructions, some of which occur before a conditional test executed to determine whether to exit the loop, and some of which occur after the conditional test. In the example sequence illustrated, the loop goes through three full iterations 200 , 205 , 210 , and then the conditional test is evaluated to indicate that the loop will end at point 220 partially traversing the fourth iteration 215 . It is often the case that in a conditional test, the number of iterations required is unknown, so although in this instance the loop terminates partially through the fourth iteration, in other instances the loop may not terminate until more iterations are performed , or even terminate early.

When performing speculative vector operations to vectorize such a scalar loop, each scalar instruction is replaced by a vector instruction, in which case the specified vector operands include a plurality of vector elements, each vector element associated with a different iteration. Because it is not known at which iteration a scalar loop will exit, it is not possible to vectorize a loop by specifying a vector operand with a specific number of vector elements. In contrast, as illustrated in Figure 4, for the equivalent vector instruction of a scalar instruction that occurs before a conditional test, the speculation width is used to speculate on the number of vector elements required. As previously discussed, in one embodiment, this speculation width will initially be set to a chosen value such as 16, whereby execution of each of these vector instructions will initially be replicated 16 times in this example Execution of the equivalent scalar instruction (ie, one for each of 16 individual iterations). If the current speculative width produces progress indicators that cause a speculative reduction condition to be detected, then as discussed above, the speculative width will be reduced while ensuring that at least one vector element in each vector operand continues to be processed.

When the conditional test is subsequently evaluated, it can then be determined how many vector elements are required. For example, it can be estimated that the equivalent scalar loop would have ended at the third iteration, whereby the required speculation width is three. Assuming the speculative width is still greater than three, all required vector elements will have been processed. However, if the current speculation width is less than the number of iterations indicated by the conditional test, then at least one further iteration of the sequence of vector operations will then need to be performed to process the remaining required vector elements.

After the commit point, the remaining vector instructions are executed non-speculatively. However, masking can be set to ensure that only the required number of vector elements are processed (or, if the speculative width is less than the required width, the number equivalent to the current speculative width, given the widths identified during conditional test analysis, by This will require yet another iteration). Processing will then exit conditionally. In particular, if the conditional test indicates that all required data has been written, then processing will exit, otherwise processing will repeat at least once.

Figure 5 illustrates a vector loop for the case of using specific speculative and commit instructions. The speculative command is used to turn on speculation and thus set the speculative flag 105 . Subsequently, the sequence of instructions is executed speculatively, with a speculative width of 100 identifying the number of vector elements in each vector operand. As previously discussed, the speculative width may be reduced during execution of a vector operation upon detection of a speculative reduction condition. Thereafter, one or more instructions will be executed to determine the appropriate width to commit, and then a separate commit instruction will be executed to turn speculation off. Following this, a series of non-speculative instructions will be executed, and as previously discussed, a mask or length value can be used in association with those instructions to set vector elements appropriately taking into account determinations made prior to the commit point width. Branch instructions can then be used in order to determine whether the loop should be repeated or should be exited.

Figure 6 is a flow diagram illustrating the speculative width reduction process performed according to one embodiment. In step 300, the speculative control circuitry waits for the receipt of a progress indication, and if in step 300 it is determined that no progress indication has been received, and in step 305 it is determined that the speculative flag is still located within the control register 65 Terminates, the process waits at step 300 until a progress indication is received. If the speculation is terminated, the process proceeds from step 305 to 310 where the process ends.

After receiving the progress indication, in step 315 the speculation control circuitry 60 analyzes the progress indication with reference to the speculation reduction criteria 70 and then in step 320 determines whether a speculation reduction condition has been detected. If not detected, the process returns to step 300 . However, if a speculative downscaling condition is detected, then in step 325 the speculative control circuitry determines the degree of speculative downscaling required. The degree may be a predetermined amount by which the speculation control circuitry reduces the speculation width, or conversely the degree may be predetermined in terms of rules to be applied, such as setting a new speculation width so that the most significant element position is identified The position to the left of the element position that yields the progress indication, thereby excluding the identified element position from the revised guess width.

In alternative embodiments, the degree of speculative reduction may be determined taking into account the speculative reduction criteria themselves. An example of such an approach will be described below with reference to FIG. 13 , where the reduction criterion maintains a slack value indicating the slack available during the processing of speculative vector operations in terms of how performance characteristics are affected, and the degree to which excess slack is taken into account. The speculative width reduction is dynamically managed in the case of .

After determining the degree of speculative reduction in step 325 , in step 330 the speculative width is reduced and the process then returns to step 300 . As described above, once the speculation width has been reduced, this information is passed via path 82 to vector processing circuitry 30 and causes the number of vector elements processed during execution of any outstanding speculative operations to be reduced.

FIG. 7 is a flow chart illustrating the process performed when speculation is started. Although speculation can be initiated in a variety of ways, in one embodiment an explicit start speculation instruction is provided which when decoded by decode circuitry 20 causes the appropriate control signals to be issued to speculation control circuitry 60 . In step 340, the initial guess width is determined and set by setting the appropriate control register 65. As previously described, the initial speculation width may be predetermined, may be identified within control information passed from the decoding circuitry, or may even be provided by the speculation estimation circuitry 85 . Following step 340, speculative mode is selectively enabled in step 345 depending on whether the device is using an explicit speculative mode.

FIG. 8 is a flow diagram illustrating a commit process that is performed after the series of speculative operations within the vector loop of FIG. 5 have been performed and before the performance of any non-speculative operations. One or more instructions may be executed to perform the steps illustrated in FIG. 8 . In step 350, a conditional test is performed to determine the required vector width, ie, the required number of vector elements, to be processed. Then, in step 355, the current speculation width is read, and in step 360, the current speculation width is compared with the desired vector width.

In step 365, it is then determined whether a speculative vector operation has resulted in under-speculation. This will happen if, by the time the commit point is reached, the speculative width has shrunk to the point where it is smaller than the desired vector width. Otherwise, if the current speculation width is larger than the required vector width, the process will have over-speculated.

If over speculation, the process proceeds to step 385 where the repeat flag is cleared, indicating that no more vector loop iterations are required. Next, a mask is set for non-speculative instructions in step 390 to identify the required vector width. This will enable a vector loop to vectorize an equivalent scalar loop without another iteration.

However, if the speculation is insufficient, then in step 370, a repeat flag is set to invoke a subsequent iteration of the vector loop. Next, a mask is set for non-speculative instructions in step 375 to identify the current speculative width. Thus, once the current vector loop is complete, both speculative and non-speculative operations will have processed the same number of vector elements. Thus, the vector loop can be repeated one or more times to handle the remaining vector elements within the desired vector width.

In embodiments using a specific speculative mode, after step 375 or 390 the speculative mode is turned off in step 380 . This will ensure that subsequent instructions within the vector loop are executed in a non-speculative manner.

FIG. 9 illustrates a conditional exit process that is typically performed by a branch instruction such as that illustrated in FIG. 5 after the execution of a series of speculative and non-speculative instructions. In step 400, it is determined whether a repeat flag is set. If the setting is confirmed, the process returns to the starting guess point at the beginning of the vector loop in step 405 , otherwise the process ends in step 410 .

FIG. 10A is a diagram schematically illustrating how the processing of speculative vector operations changes when the speculative width is reduced. First, a speculative instruction is executed to turn on speculative mode and set the speculative width to a specified amount, in this example 16 vector elements. In the illustrated example, it is assumed that the components within the vector processing circuitry are capable of processing two vector elements from each source operand during a single cycle, thus, the components performing the vector operation VOP 1420 will take 8 cycles to complete All required operations.

In the illustrated example, it is assumed that there is a data dependency between VOP1 and VOP2 (in this example, VOP2 is a vector load), so that execution of VOP2 does not begin one cycle after execution of VOP1 begins.

As illustrated in this example, when LSU 50 is processing a vector load, the LSU detects a microarchitectural event associated with vector element 9 (i.e., the vector element at element position 10) and issues a progress indication that identifies the event and element positions, as indicated by reference numeral 430 in FIG. 10A . Such a microarchitectural event could be, for example, a cache miss that occurs while attempting to load vector element 9, and in this example it is assumed that when evaluating this indication of progress relative to shrinkage criteria 70, speculation control circuitry 60 decides to speculate width Reduce to a width of 9 elements, thereby excluding vector element 9 (which, as mentioned earlier, is at element position 10). Vector Operation VOP3 illustrates an example of a vector operation that started processing before the progress indication was issued and the associated speculative width reduction, but was still in progress at the time of the speculative width reduction. As illustrated by the cross within VOP3 435, in response to the reduction in speculation width, the components performing VOP3 may be arranged to cull any of the vector elements at element position 10 or higher. As discussed above with reference to FIG. 1 , clock gating and/or power gating techniques may be used to reduce energy consumption of components executing VOP3 based on the reduced speculation width.

Vector operation VOP4 illustrates a vector operation that is initiated only after a speculative width reduction has been performed, and in this example, as indicated by reference numeral 440, this is the case at the initial ( Subject to no further speculative width reductions) will be known.

In the example illustrated in FIG. 10A , it is assumed that vector operation VOP4 440 is another vector load operation, and that this vector load cannot begin execution until the previous vector load VOP2 is completed.

Figure 10B illustrates an alternative embodiment in which the adjustment of the speculation width affects not only future vector operations, but previous vector operations as well. In particular, as indicated by reference numeral 450, when the speculative width is reduced, this may cause the component performing VOP2 (ie, the vector operation that produced the speculative reduction) to also terminate processing for one or more subsequent iterations, in which case, Two iterations are relative to the last four vector elements.

Furthermore, in one embodiment, the process can be used to retrospectively trim operations of vector operations that have been issued even before VOP2. In the example shown, the final iteration of VOP1 also terminates based on reducing the speculation width, as indicated by reference numeral 445 . Again, clock and power gating techniques can be used to reduce the energy consumption of the components performing these operations. Another advantage that can be realized is increased performance, as components will be available to process other operations more quickly. For example, when compared to the example of FIG. 10A, in the example of FIG. 10B, the LSU 50 will terminate the execution of VOP2 two cycles earlier in consideration of VOP4, whereby VOP4 can start two cycles earlier.

11A and 11B illustrate other examples of how speculation reduction can trigger corrections in the performance of subsequent operations. In this example, it is assumed that the components executing VOP1 and VOP2 are capable of processing 8 vector elements in each source vector operand in each iteration, whereby the originally specified 16 vector elements can be processed in two cycles. If a speculative shrink trigger occurs at point 465 when VOP1 460 is executing, this trigger can be used to clock gating (or even power gating) certain components of VOP2 (as indicated by reference numeral 475) for processing at element position 465 This is especially true for those components whose element positions above or cause speculative shrinkage. However, not all element positions on or above the element position that produced the speculative reduction need be clock-gated, and as shown in FIG. 11B, in an alternative embodiment, only a subset of higher element positions may be clock-gated Clock gating is performed, as indicated by reference numeral 480 . As discussed below with reference to FIG. 14 , this may be due, for example, to speculation control circuitry 60 determining with reference to the reduction criteria that the speculation width should actually only be trimmed by 2, rather than all trimming to exclude vector element positions 465 and higher.

12A illustrates how microarchitectural events such as level 2 cache misses can introduce significant latency when performing speculative vector operations. In this example, a speculative instruction is executed at point 500 , which sets an initial speculation width of sixteen. Then, a vector load instruction 510 is executed, but in this case a level 2 cache miss occurs when trying to load vector element 6 (ie, the data element at vector element position 7). In this example, this introduces 200 latency cycles before the vector load operation is able to load vector element 6 and the remaining vector elements. This situation has an impact on the next two vector operations, VOP1515 and VOP2520, due to the data dependencies between those multiple vector operations. Thus, another cycle is consumed at point 525 as the commit process is performed, at which point the speculative width is still 16. As can be seen, this results in a total of 212 cycles required to perform the required vector operations, requiring an average of 13.25 cycles per vector element.

In contrast, FIG. 12B illustrates the situation when using the adaptive guess width method in the described embodiment. Although in step 500 the speculative width is again initially set to 16, when a level 2 cache miss is detected with respect to data element 6 (element position 7) of the vector load operation 530, this situation causes the speculative control Circuitry 60 dynamically scales down the speculation width to 6 after a short delay due to the time it takes to evaluate the indication of progress relative to the scale down criteria and determine the scale down to make. Due to the reduced speculation width, VOP1 535 and VOP2 540 only process the first 6 element positions, whereby the commit process can then be performed at point 525 based on the current speculation width of 6 after the first 6 elements of VOP2 have been executed. As a result, the process takes 7 cycles to process 6 elements, an average of 1.167 cycles per vector element.

Assuming at the commit point it is determined that the required speculation width is 6 or less, no further iterations of the vector loop will be required and the process will complete. If, instead, the required vector width is determined to be greater than 6, then one or more additional iterations of the vector loop will need to be performed to process the remaining elements. However, this can still result in a significant performance gain because it is entirely possible that no level 2 cache misses will occur with respect to vector element 6 before subsequent iterations are performed, and thus subsequent iterations proceed more efficiently.

Although the speculative shrinkage criteria may directly specify one or more criteria that, if satisfied, indicate the presence of a speculative shrinkage condition, alternatively or additionally, the speculative shrinkage criteria may include performance margin information maintained by the speculative control circuitry, and The performance margin information is adjusted taking into account progress indications generated during execution of the sequence of speculative vector operations. Figure 13 is a flow diagram illustrating the execution of a speculative reduction process according to one such embodiment, wherein the performance margin information is in the form of a slack indication that provides performance characteristics during the processing of speculative vector operations. An indication of how the aspect is affected against the available slack.

In step 600, the speculation width is set to an initial value at the start of speculation, and in step 605, a parameter "slack" is set to some specified budget value. This value may be provided by an instruction to start speculation, may be by default, or may be provided in other ways, such as by such speculative estimation circuitry 85 in embodiments that include it.

In step 610, it is determined whether a progress indication has been received, and if not, it is determined in step 615 whether the speculation has terminated. If so, the process ends at step 620 , otherwise, the process returns to step 610 .

When an indication of progress is received, a determination is made as to whether the indication of progress indicates a negative or positive impact on the performance characteristic. In particular, in an alternative embodiment, processing circuitry 30 may provide progress indications not only with respect to events that have a negative impact on performance characteristics, but also with respect to certain events that have a positive impact, such as indicating that certain Some operations have performed faster than expected. In the event of a positive indication of progress, in step 630 the slack value is increased by the amount indicated by the indication of progress and the process returns to step 610 .

Conversely, if in step 625 a negative progress indication is detected, then in step 635 a parameter "cost" is evaluated, which indicates the performance cost associated with the negative indication. Then, the slack value is adjusted by subtracting the cost value from the current slack value. Then, in step 655 , it is determined whether the slack value is currently negative, if not, the process returns to step 610 .

If the slack value is determined to be negative in step 655, an internal parameter (SW) is set by subtracting the value determined as a function of the current slack value from the current guess width. The function can be set in a number of ways, but in one example, the function will result in: the greater the negative slack value, the greater the amount subtracted from the inferred width.

In step 665, it is detected whether the parameter SW is less than 1. If less than 1, then set SW equal to 1 in step 670 before the process proceeds to step 675 , otherwise, the process proceeds directly from step 665 to step 675 . The purpose of steps 665, 670 is to ensure that the internal parameter SW never falls below 1, so as to ensure that the current iteration of the vector loop will always produce some positive progress. In particular, in step 685 the speculative width will be set equal to SW, whereby the speculative width will be set to a value of 1 or greater before the process returns to step 610 .

Steps 675 and 680 are optional. In step 675, an internal parameter "reduction" is determined by subtracting the internal parameter SW from the current speculation width (ie, the speculation width before adjustment in step 685). Then, in step 680, the slack value is increased by the determined "reduction" value. Then, in step 685 the speculation width is reduced. When using the optional steps 675, 680, it will thus be seen that whenever the speculative width is reduced, the slack value is adjusted positively by the amount of reduction of the speculative width.

14A and 14B schematically illustrate how the slack value may change when the process of FIG. 13 is performed. In this example of FIG. 14A, it is assumed that optional step 630 is performed. As shown by slope 687 , the slack value initially increases after some positive indication is received via path 80 . A negative indication causes the slack value to drop for the first time, and then a second negative indication causes the slack value to drop to a negative value at point 688 . At this point, the speculation width is reduced, and the slack value reduction is adjusted positively. Successive positive indications of progress increase the slack value even more, as indicated by slope 689 , but after two negative indications of progress the slack value returns to negative again at point 690 . This again reduces the speculation width, and the slack value is optionally increased based on the reduction of the speculation width. Therefore, a positive progress indication causes the slack value to follow line 691 .

In one embodiment, upon receiving a positive indication, the amount by which the slack value is adjusted positively depends on the inference width. In particular, the higher the inferred width, the greater the overall effect of the positive indication, whereby slope 687 has a steeper slope than slope 689 , and likewise slope 689 has a steeper slope than slope 691 .

In FIG. 14A, it is assumed that optional steps 675, 680 are not performed, whereby the slack value is not adjusted in the positive direction to compensate for the reduction of the speculative width. However, in an alternative embodiment, steps 675 and 680 would be performed so that at points 688, 690 the slack value would have a positive jump ahead of the slope 689, 691 followed. Positive jumps in the slack value may or may not take a positive slack value again, as this will depend on the slack value function applied in step 660, and thus on the extent of the speculative width reduction that occurred.

FIG. 14B illustrates an example in which no positive indications of progress are received, whereby the slack value starts at an initial budget value and then steps down each time a negative indication is received. After the slack value becomes negative, the speculative width shrinks each time the slack value decreases.

Figure 15 illustrates a virtual machine implementation that may be used. While the foregoing described embodiments implement the invention in terms of apparatus and methods for operating specific processing hardware supporting the related art, it is also possible to provide so-called hardware device virtual machine implementations. These virtual machine implementations run on a host processor 730 , which typically runs a host operating system 720 that supports a virtual machine program 710 . Typically, a powerful processor is needed to provide a virtual machine implementation that executes at reasonable speeds, but this approach is appropriate in some cases, such as those that need to run on another processor for compatibility or reuse reasons The situation of the local code. The virtual machine program 710 can execute the application program (or operating system) 700, and the result obtained is the same as that obtained by executing the program on a real hardware device. Thus, program instructions including the speculative vector instructions described above can be executed within the application program 700 by using the virtual machine program 710 .

By using the techniques described above, at least one performance characteristic of a data processing device, such as throughput or energy consumption performance, can be achieved while performing speculative vector operations by trying to avoid that performing speculative vector operations with a specific speculation width would have a negative impact on the selected performance characteristic. Improvements in the event of excessive adverse effects. In this way, the speculation width can be dynamically adjusted to try to avoid time-consuming or energy-intensive work that may not be necessary, thereby saving time and energy. To guarantee progress, in one embodiment speculative width reductions below 1 element are prohibited.

Although specific embodiments have been described herein, it will be understood that the invention is not limited to those embodiments and that numerous modifications and additions are possible within the scope of the invention. For example, various combinations of the features of the following dependent claims may be made from the features of the independent claims without departing from the scope of the present invention.

Claims (28)

1. A data processing device comprising: processing circuitry configured to perform a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements; speculation control circuitry configured to maintain a speculation width indication indicating the number of vector elements in each vector operand that will be subjected to said speculative vector operation, the speculation width indicating execution of said speculative vector operation sequence was previously initialized to its initial value; the processing circuitry configured to generate a progress indication during execution of the sequence of speculative vector operations; The speculative control circuitry is further configured to detect the presence of a speculative shrinkage condition with reference to the progress indication and the speculative shrinkage criterion, the speculative shrinkage condition being a condition indicating: relative to no shrinkage at the speculative width indication In continuous operation under, the reduction of the speculation width indication is expected to improve at least one performance characteristic of the data processing device; The speculation control circuitry further scales down the speculation width indication in response to detection of the speculation shrinkage condition. 2. The data processing apparatus of claim 1, wherein the progress indication is indicative of a yield impacting event occurring within the processing circuitry during execution of the speculative vector operation. 3. A data processing apparatus as claimed in claim 1 or 2, wherein the progress indication is indicative of an energy consumption affecting event occurring within the processing circuitry during execution of the speculative vector operation. 4. A data processing apparatus as claimed in any preceding claim, wherein the progress indication is issued in response to a microarchitectural event occurring within the processing circuitry during execution of the speculative vector operation. 5. A data processing apparatus as claimed in any preceding claim, wherein the speculation width indication further identifies a first vector element of each vector operand to be subjected to the speculative vector operation. 6. A data processing apparatus as claimed in claim 5 , wherein said speculation width indication identifies the number of vector elements in each vector operand that will be subjected to said speculative vector operation as the number from said first vector element The specified number of sequential vector elements to start with. 7. Data processing apparatus as claimed in any preceding claim, wherein: The processing circuitry is configured to execute an instruction vector loop comprising instructions defining the sequence of vector operations and at least one evaluation performed at a commit point within the vector loop after execution of the sequence of vector operations instructions, execution of the at least one evaluation instruction causes a required vector width to be determined; The speculation control circuitry is responsive to the determination of the required vector width to determine with reference to the current value of the speculation width indication whether execution of the sequence of vector operations results in over-speculation or under-speculation, and in the event of the under-speculation, The repeat flag is then set such that another iteration of the instruction vector loop is performed. 8. The data processing apparatus of claim 7 , wherein after a further iteration of the instruction vector loop, the speculative control circuitry is configured to take into account vectors processed during a previous iteration of the instruction vector loop The number of elements to initialize the speculative width indicator to the corrected initial value. 9. A data processing apparatus as claimed in claim 7 or 8, wherein said vector loop includes one or more non-speculative instructions executed after said commit point, the speculative control circuitry being further configured to set a mask value to A number of vector elements in each vector operand that are to be subjected to a non-speculative operation defined by the one or more non-speculative instructions is identified. 10. Data processing apparatus as claimed in any preceding claim, further comprising: a vector register bank configured to store the vector operands for access by the processing circuitry; The processing circuitry includes data access circuitry configured to perform vector access operations to move vector operands between the vector register bank and a memory system that includes at least one Hierarchical cache memory; The data access circuitry is configured to issue information related to cache misses that occur during execution of the vector access operation as the progress indication. 11. The data processing apparatus of claim 10 , further comprising a translation lookaside buffer (TLB), the data access circuitry referring to the TLB during execution of the vector access operation, the data access circuitry The system is further configured to issue information related to TLB misses that occur during execution of the vector access operation as the progress indication. 12. A data processing apparatus as claimed in any preceding claim, wherein the data processing circuitry responds to the reduction of the speculation width indication to vary the number of vector elements per vector operand subject to the selected vector operation, the The selected vector operation occurs in the sequence beginning with the vector operation whose progress indication results in detection of the speculative reduction condition that causes the speculation width indication to be reduced. 13. The data processing apparatus of claim 12 , wherein the data processing circuitry is further responsive to the reduction of the speculative width indication to vary the number of vector elements subjected to a non-complete vector operation in each vector operand, the A non-complete vector operation occurs before a vector operation in the sequence whose progress indication results in detection of the speculative reduction condition that causes the speculative width indication to be reduced. 14. A data processing apparatus as claimed in any preceding claim, further comprising control circuitry configured to reduce the inference within one or more components of the processing circuitry in response to the reduction of the speculation width indication. Power consumption. 15. The data processing apparatus of claim 14, wherein the control circuitry employs at least one of clock gating and power gating to reduce power consumption within the one or more components. 16. A data processing apparatus as claimed in any preceding claim, wherein at least one of the initialization initial value of the speculative width indication and the speculative reduction criteria is specified by instructions to be executed by the data processing apparatus. 17. A data processing apparatus as claimed in any one of claims 1 to 15, wherein at least one of an initialization initial value of the speculation width indication and said speculation reduction criterion is predetermined. 18. A data processing apparatus as claimed in any one of claims 1 to 15, further comprising: predictive circuitry configured to maintain historical data regarding speculative width values for sequences of speculative vector operations previously performed by the processing circuitry at the commit point; The predictive circuitry is configured for a current sequence of speculative vector operations to be performed by the processing circuitry to, prior to execution of the current sequence of speculative vector operations, refer to the historical data to determine that the speculative width indication is to be set the initial value of . 19. A data processing apparatus as claimed in any one of claims 1 to 15, further comprising: predictive circuitry configured to maintain historical data regarding speculative reduction criteria for sequences of speculative vector operations previously performed by the processing circuitry; The predictive circuitry is configured, for a current sequence of speculative vector operations to be performed by the processing circuitry, to reference the historical data to determine speculative reduction criteria for execution of the current sequence of speculative vector operations. 20. Data processing apparatus as claimed in any preceding claim, wherein the speculative control circuitry triggers a speculative mode of operation in response to commencing execution of a speculative instruction, the processing circuitry being configured to respond to operations performed during the speculative mode of operation The instruction executed performs the speculative vector operation. 21. The data processing apparatus of claim 20, wherein the speculative control circuitry is responsive to execution of a commit instruction to terminate the speculative mode of operation. 22. A data processing apparatus as claimed in any preceding claim, wherein the speculation control circuitry modifies the speculation width indication in response to the speculation reduction condition to indicate that at least one vector element in each vector operand will be subjected to the Speculative vector operations. 23. Data processing apparatus as claimed in any preceding claim, wherein: the speculative reduction criteria include performance margin information maintained by the speculative control circuitry; the speculative control circuitry configured to adjust the performance margin information taking into account an indication of progress generated during execution of the speculative vector operation sequence; and The speculative control circuitry is configured to detect the speculative reduction condition when the performance margin information reaches a trigger point. 24. The data processing apparatus of claim 23, wherein the speculation control circuitry refers to the performance margin information when determining an amount by which the speculation width indication is to be reduced. 25. A data processing apparatus as claimed in any preceding claim, wherein the speculative width is predetermined to indicate an amount to be reduced when the speculative reduction condition is detected. 26. A method of controlling performance of speculative vector operations, the method comprising the steps of: performing a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements; maintaining a speculative width indication indicating the number of vector elements in each vector operand that will be subjected to said speculative vector operation, the speculation width indication being initialized to an initial value prior to execution of said speculative vector operation sequence; generating a progress indication during execution of the sequence of speculative vector operations; Detecting the presence of a speculative shrinkage condition with reference to the progress indication and the speculative shrinkage criterion, the speculative shrinkage condition being a condition indicating that, relative to successive operations where the speculation width indicates no shrinkage, the speculative shrinkage condition The reduction in width indication is expected to improve at least one performance characteristic of the data processing device; and The speculative width indication is scaled down upon detection of the speculative shrinkage condition. 27. A computer program product storing a computer program in non-transitory form for controlling a computer, thereby providing a virtual machine execution environment for program instructions corresponding to any one of claims 1 to 25 data processing equipment. 28. A data processing device comprising: processing means for performing a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements; speculation control means for maintaining a speculation width indication indicating the number of vector elements in each vector operand that will be subjected to said speculative vector operation, the speculation width indication being determined prior to execution of said speculative vector operation sequence Initialize to initial value; said processing means for generating an indication of progress during execution of said sequence of speculative vector operations; The speculative control means for detecting the presence of a speculative shrinkage condition with reference to the progress indication and the speculative shrinkage criterion, the speculative shrinkage condition being a condition indicating: relative to the case where the speculative width indicates no shrinkage successive operations of , the reduction of the speculation width indication is expected to improve at least one performance characteristic of the data processing device; The speculation control means is for responding to detecting the speculation reduction condition by reducing the speculation width indication.