JPH0981616A - Static timing analysis device and its analysis method - Google Patents

Abstract

(57) [Abstract] [Problem] It is possible to reliably identify a sequential circuit and divide it into a combinational circuit, there are few false paths in the analysis result, the design efficiency is good, the design period can be shortened, and the burden on the user can be reduced. And According to a circuit structure developed from a netlist, it is determined whether an output of a circuit to which a clock signal is input can be high impedance (S3), and if the output can be high impedance, this circuit The output of is set as the start point of the path search, and the input other than the clock signal of this circuit is set as the end point of the path search (S4) .If the output cannot be high impedance, set the output of this circuit as the clock node. In addition to setting, the input node other than the clock signal of this circuit is set as the end point of the path search.
(S5). Therefore, the sequential circuit can be reliably divided into combinational circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CAD (C
omputer Aided Design) device, and more particularly to a static timing analysis device and its analysis method for searching a critical path of a circuit having the longest time from connection information of a transistor.

[0002]

2. Description of the Related Art Today, the number of transistors integrated in an LSI is increasing dramatically, and especially in a system LSI represented by a microprocessor, the circuit complexity is also increasing. Thus, in order to improve the performance of a large-scale and complicated semiconductor device and shorten the design period, a CAD device for manufacturing a semiconductor device is indispensable. As one of tools used in this CAD device, a static timing analysis system for finding a critical path of a circuit based on circuit connection information of a transistor has been proposed. This static timing analysis system does not require a combination sequence of input signals called a test vector,
Due to the short execution time, it has become popular rapidly in recent years. The static timing analysis system is an inverter circuit or N
Various types have been proposed, such as those that perform analysis at the gate level of AND circuits, and those that perform analysis at the transistor level.
For example, various things such as PathMill of EPIC have been proposed.

In recent years, a gated clock (Gated Clock) has been used as a designing method for a microprocessor because of a demand for low power consumption. This method called gated clock uses a clock signal with NA
Gating is performed by an ND circuit or the like, and it is also required to analyze the static timing of the circuit designed by this method.

By the way, various static timing analysis system algorithms for reading and analyzing a transistor-level netlist have been proposed. FIG.
0 indicates an example of a conventional static timing analysis method, and the outline of the processing flow will be described below. First, a netlist is read from the memory and the netlist is expanded to construct a data structure (step S1).
1). Thereafter, the start point and end point of the path search specified by the user using, for example, an editor are recognized from the constructed data structure (step S12), and the synchronous sequential circuit (hereinafter The sequential circuit) is divided into combinational circuits (step S13).
Next, the path search process of the static timing analysis is performed on all the divided combinational circuits (steps S14 and S15), and the result is finally output (step S16).

In the case of the method shown in FIG. 10, the user must specify the starting point and the ending point of the path search. Therefore, there is a problem that the burden on the user is large, the design efficiency is low, and the design period is long.

FIG. 11 shows another conventional example.
In this case, first, the netlist is read to construct a data structure (step S21). Next, pattern matching is performed using a predetermined rule or a rule defined by the user, and the net expressed at the transistor level is converted into a net expressed at the gate level (step S22). After that, the sequential circuit is divided into combinational circuits (step S23), a path search at the gate level is performed for each combinational circuit, and when the path search is completed for all combinational circuits (steps S24, S25), the result is output. Yes (step S26).

In the conventional example shown in FIG. 11, since the pattern matching process is performed, the execution time becomes very long, and since the user defines the pattern matching rule, there is a problem that the burden on the user is heavy. is there. Further, the path search process is performed at the transistor level with better timing accuracy than at the gate level, and it is possible to reliably verify whether or not the searched path is an activated path.
However, since the path search is performed at the gate level in this example, it is difficult to reduce the false paths due to poor timing accuracy. For this reason, there have been problems that the efficiency of design becomes poor and the design period becomes long.

FIG. 12 shows still another conventional example. In this case, first, the netlist is read to construct a data structure (step S31). Next, the input and output ends of the signal defined by the user and the clock node to which the clock signal is input are recognized (step S3).
2) Based on that, the start point and the end point of the path search are set (step S33). As a system for setting the start point and the end point of this path search, for example, the EPIC Path
Mill is used. In the case of this system, each node is followed sequentially from the clock node specified by the user, and when it reaches the gate of the transistor other than the inverter circuit, that node is set as the end point of the path search and the source or drain of the transistor is searched for the path. Is the starting point. In this way, after setting the start point and the end point of the path search, the path search from each start point to the end point is performed, and when the path search from all the start points of the path search is completed (steps S34, S35), the result is Output (step S3
6).

In the case of the conventional example shown in FIG. 12, since the path search is performed at the transistor level, the timing accuracy is better than that of the conventional example shown in FIG. However, when setting the start point and the end point of the path search, the path search is not performed when the clock signal is at the low level, and the path search is performed only when the clock signal is at the high level. Therefore, for example, the precharge circuit and the latch circuit are identified. Is difficult. Also, NAN
Since the output of the D circuit is not recognized as a clock, there is a problem that it cannot be applied to the clocked gate used as a design method in recent years. Furthermore, in this conventional example, since the sequential circuit is not divided into combinational circuits, it is not possible to verify whether the searched path is an activated path, the number of false paths increases, and the design efficiency decreases. However, there is a problem that the design period becomes long.

[0010]

As described above, in the conventional transistor-level path analysis system, since a sufficient search is not performed when setting the start point and the end point of the path search, it is possible to identify the sequential circuit. It was not possible, and there were many false paths in the analysis results. Moreover, the burden on the user is large, and the circuit designed by the gated clock method cannot be analyzed. Therefore, there is a problem that the design efficiency is low and the design period is prolonged.

The present invention is intended to solve the above problems, and an object of the present invention is to reliably identify a sequential circuit and divide it into combinational circuits, reduce false paths in analysis results, and improve design efficiency. An object of the present invention is to provide a static timing analysis apparatus and its analysis method that can shorten the design period and reduce the burden on the user.

[0012]

A static timing analysis apparatus according to the present invention comprises storage means for storing a netlist, construction means for constructing a transistor-level circuit structure from the netlist read from the storage means, and input means. From the recognition means for recognizing the node to which the clock signal input from is supplied from the constructed circuit structure, and the circuit structure constructed by the construction means, the output of the circuit to which the clock signal is input becomes high impedance. If the output of the circuit can be high impedance, the output of this circuit is set as the start point of the path search, and the input other than the clock signal of this circuit is set as the end point of the path search. If the output of the first setting means and the circuit set to the above cannot be high impedance, the output of this circuit Are you and a second setting means for setting a node for outputting a clock signal, setting the input nodes other than the clock signal of the circuit to the end of the path search.

According to the static timing analysis method of the present invention, a step of constructing a transistor level circuit structure from a netlist and a step of recognizing a node to which a clock signal input from an input means is supplied from the constructed circuit structure. From the circuit structure constructed by the constructing means, a step of determining whether the output of the circuit to which the clock signal is input can be high impedance; and when the output of the circuit can be high impedance, The output of this circuit is set as the start point of the path search, and the input other than the clock signal of this circuit is set as the end point of the path search, and when the output of the circuit cannot be high impedance, the output of this circuit is Set the node for outputting the clock signal, and set the input nodes other than the clock signal of this circuit to the path search. And it includes a step of setting a point.

That is, according to the present invention, it is determined from the transistor-level circuit structure developed from the netlist whether the output of the circuit to which the clock signal is input can be high impedance, and the output of the circuit is high impedance. If this is the case, the output of this circuit is set as the start point of the path search, and the input other than the clock signal of this circuit is set as the end point of the path search. If the output of the circuit cannot be high impedance, the output of this circuit is set as the node for outputting the clock signal, and the input node other than the clock signal of this circuit is set as the end point of the path search. . Therefore, the sequential circuit can be identified with certainty and can be divided into combinational circuits.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a static timing analysis device to which the present invention is applied.
This device includes a microprocessor unit (MPU) 12 connected to a system bus 11, a memory 13, a display 1
4, a keyboard 15 and a mouse 16. In the memory 13, a transistor-level netlist including connection information of a circuit to be processed, which will be described later, and other data, a clock node recognition process, a sequential circuit division process, a path search process, which will be described later by controlling the operation of the MPU 12, Various programs for executing output processing of processing results and the like are stored. The display 14 displays the processing content and processing result of the MPU 12, the designation information of, for example, a clock node input from the keyboard 15, the information designated by the mouse 16, and the like.

Next, referring to FIG. 1, an analysis method by the static timing analysis device will be described.
In this static timing analysis device, first, a netlist relating to a circuit to be processed is read from the memory 13 and a data structure necessary for processing is constructed (step S).
1). Since this device analyzes at the transistor level, all the data of the hierarchical structure read from the memory 13 is expanded into flat data. Next, the clock node designated by the user is recognized from the expanded data (step S2). The designation of the clock node is
For example, using an editor, a desired clock node is input from the keyboard 15 on the screen of this editor. After recognizing the clock node, the sequential circuit is divided into a circuit group including only combinational circuits. This division processing is executed as follows.

In general, sequential circuits store information in a high impedance state created by a clock signal. Therefore, it can be considered that the signal path is divided by the node in the high impedance state.
Paying attention to this, when dividing the sequential circuit, first, the clock node is traced based on the clock signal, and a node which can be in high impedance by the clock signal is searched for (step S3). If the output node of the circuit to which the clock signal is input can be high impedance,
The output node of the circuit is set as the start point of the path search, and the input node other than the clock signal of this circuit is set as the end point (step S4). Such a circuit corresponds to, for example, a pass transistor having a gate to which a complementary clock signal is input, a precharge circuit, a clock type CMOS circuit, or the like.

When the output node of the circuit to which the clock signal is input cannot be in high impedance, the output node of the circuit is set as the clock node, and the input node other than the clock signal of the circuit is set as the end point. (Step S5). Such a circuit is, for example, an inverter circuit or a NAND circuit or a NOD forming a gated clock.
The R circuit is applicable.

The above operation is repeated to divide the sequential circuit into a circuit group composed of only combinational circuits. When this division processing is completed (step S6), the path search is performed for each combinational circuit as in the conventional case, and when the path search is completed for all combinational circuits (steps S7, S).
8) Then, the processing result is output to, for example, the display 14 (step S9).

In an actual timing analysis system,
In consideration of the processing time, the inverter circuit and the pass transistor are recognized in advance by using a pattern matching method. Here, the division processing method of the sequential circuits shown in steps S3 to S6 will be specifically described. First, the level of the clock signal and the level of each node corresponding to this clock signal are defined as shown in FIG.

The clock signal C is set to the clock node designated by the user. The path of the clock signal propagation is traced based on this node. As shown in FIG. 3, when the clock signal C is input to the inverter circuit, its output node becomes CI which is the inverted clock signal C. When the clock signal C enters the gate of a P-channel MOS transistor (hereinafter referred to as PMOS), its source or drain becomes the high level portion CHI of the clock signal whose phase is inverted. When the clock signal C enters the gate of an N-channel MOS transistor (hereinafter referred to as NMOS), its source or drain becomes the low-level portion CLI of the clock signal C whose phase is inverted.

When the clock signal CI is input to the inverter circuit, its output node is the clock signal CI.
Is the inverted C. When the clock signal CI enters the gate of the PMOS, its source or drain becomes the high-level portion CH of the clock signal whose phase is inverted. NM
When the clock signal CI enters the gate of OS, its source or drain becomes the low-level portion CL of the clock signal whose phase is inverted. Clock signals C, CI, CH, CL, CH at the source or drain of the PMOS or NMOS
When I and CLI are input, these signals pass through other channels as they are.

Based on the above definition, a concrete circuit
A method of setting the start point and the end point of the path search will be described. FIG. 4 shows a pass transistor. The pass transistor 41 is used as a component of a flip-flop or a latch as a memory element. When the sources and drains of the PMOS and NMOS are connected together by the pattern matching process and the complementary signal is input to the gate, this circuit is recognized as a pass transistor. This pass transistor has a start point ST and an end point T of the path search according to the signal direction of the pass transistor 41 as shown in FIG.
P is set.

FIG. 5 shows a clocked inverter circuit as an example of the clock type CMOS circuit. The output of the clocked inverter circuit 51 is determined according to the value of the input signal when the clock signal is high level, and the output becomes high impedance regardless of the level of the input signal when the clock signal is low level. The starting point and the ending point of the path search of the clock type CMOS circuit are set by using such characteristics. First, when the following conditions (a) and (b) are satisfied, it is recognized as a clock type CMOS circuit.

(A) CH and CLI or CI and CHI are generated in one node. (b) There is a transistor with a common gate, which is a transistor whose path from the power supply to ground is divided by the clock signal.

Condition (a) confirms that the clock signal creates a high impedance at the node. The condition (b) is necessary for distinguishing it from the precharge circuit and the NAND circuit.

The following processing is performed on the circuit recognized as the clock type CMOS circuit based on the above conditions. (1) The node corresponding to the condition (a) is set as the starting point SP of the path search.

(2) The node satisfying the condition (b) is set as the end point TP of the path search. FIG. 6 shows an example of the precharge circuit. In the precharge circuit 61, when the clock signal is at the low level, the output signal becomes the high level regardless of the value of the input signal (precharge period), and when the clock signal is at the high level, the high impedance according to the value of the input signal. Or it becomes low level (evaluation period). The recognition of the precharge circuit is performed using such characteristics. That is, if the following condition (a) is satisfied, it is recognized as a precharge circuit.

(A) CH and CL or C in one node
The node can be set to the high level or the low level only by the transistors to which LI and CHI are generated and the clock signal is input.

This condition is based on the characteristic that the output node may have a high impedance depending on the clock signal. The following processing is performed on the circuit recognized as the precharge circuit under the above conditions.

(1) The node where CH and CL or CLI and CHI occur is set as the starting point SP of the path search. (2) The gate of the transistor to which a signal other than the clock signal is input is set as the end point TP of the path search.

However, when analyzing a domino circuit in which the precharge circuits are connected in cascade, the attributes of the precharge circuit are added to the start point and the end point of the path search of the circuit recognized as the precharge circuit. When a signal passes through a plurality of precharge circuits connected during the evaluation period like a domino circuit, the path search does not always end at the end point of the path search of one precharge circuit and the phase of the clock signal is changed. The path search can be advanced to the previous precharge circuit while considering it. By doing so, the path search of the domino circuit becomes possible.

FIG. 7 shows a NAND circuit as an example of a gate circuit.
The circuit is shown. The clock signal C and the enable signal EN are input to the NAND circuit 71 used as a gated clock. When the enable signal is high level, the clock signal is passed, when the enable signal is low level, the clock signal is not passed, and the output signal of the NAND circuit is always high level. Thus, the gated clock may or may not pass the clock signal depending on the level of the enable signal. Further, the output signal of the gate circuit never becomes high impedance. The gate circuit can be recognized by using such characteristics. That is, when the following two conditions (a) and (b) are satisfied, it is recognized as a gate circuit.

(A) CH and CL or C in one node
When HI and CLI are generated, there is an element other than the element to which the clock signal is input, which can bring the node to the high level or the low level.

(B) The gates of the transistors which are connected to the node and to which the clock signal is not supplied are commonly connected. It is confirmed that the output does not become high impedance by the condition (a). Further, the condition (b) is necessary to confirm that the clock signal is controlled by the enable signal.

The circuit recognized as a gate circuit under the above conditions is subjected to the following processing. (1) The node corresponding to the condition (a) is used as a clock node and is advanced. (2) The node corresponding to the condition (b) is set as the end point TP of the path search.

The enable signal of the gated clock has a fixed time determined with the timing of the clock signal, and it is necessary to analyze the path of the combinational circuit that produces the enable signal.

FIG. 8 shows an inverter circuit. Recognize the inverter circuit 81 by pattern matching,
When the clock signal is input, its output node is an inverted signal of the input clock signal and is set to the clock node.

As described above, with respect to the entire circuit in which the input signal, the output signal, the start point and the end point of the path search are set, the combination circuit is arranged so as to include all the nodes related to the input signal and the start point of the path search. , The sequential circuit is divided into a plurality of combinational circuits.

FIG. 9 shows a case where the test circuit is divided by the above method. In FIG. 9, this test circuit is divided into four combinational circuits indicated by broken lines, a path search is performed for each of these four combinational circuits, and the result is output.

According to the above embodiment, it is judged from the circuit structure developed from the netlist whether or not the output of the circuit to which the clock signal is input can have high impedance, and the output of the circuit becomes high impedance. If you get
While setting the output of this circuit as the starting point of the path search,
If an input other than the clock signal of this circuit is set as the end point of the path search and the output of the circuit cannot be high impedance, set the output of this circuit as the clock node and the input node other than the clock signal of this circuit. Is set as the end point of the path search. Therefore, the sequential circuit can be reliably divided into combinational circuits.

Further, in this division processing, the path search is performed even when the clock signal is at the low level.
The precharge circuit and the latch circuit can be identified, and the output of the NAND circuit can be recognized as a clock node. Therefore, the sequential circuit can be surely divided into combinational circuits, and it is possible to deal with clocked gates. For example, a circuit using a domino circuit or a gated clock circuit in which precharge circuits are connected in series can be easily analyzed.
Moreover, since this division processing is performed at the transistor level, it has the advantages of good timing accuracy and reduced false paths in the analysis results.

Further, the user does not need to input all the start points and end points of the path search or define the pattern matching rule as in the conventional case, and only needs to specify the node to which the clock signal is supplied. Therefore, the burden on the user can be significantly reduced. Furthermore, since the burden on the user is small and the division processing can be speeded up,
Design efficiency is good and the design period can be shortened.

[0044]

As described above in detail, according to the present invention,
A static timing analysis device and its analysis method that can reliably identify sequential circuits and divide them into combinational circuits, have few false paths in analysis results, have good design efficiency, can shorten the design period, and can reduce the burden on the user. Can be provided.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the operation of FIG.

FIG. 2 is a configuration diagram showing an embodiment of the present invention.

FIG. 3 is a diagram specifically illustrating a division processing method of a sequential circuit.

FIG. 4 is a circuit diagram illustrating a method of setting a start point and an end point of a path search of a pass transistor.

FIG. 5 is a circuit diagram illustrating a method of setting a start point and an end point of a path search of a clock type CMOS circuit.

FIG. 6 is a circuit diagram illustrating a method of setting a start point and an end point of a path search of a precharge circuit.

FIG. 7 is a circuit diagram illustrating a method of setting a start point and an end point of a path search of a gate circuit.

FIG. 8 is a circuit diagram illustrating a method of setting a start point and an end point of a path search of an inverter circuit.

FIG. 9 is a circuit diagram showing a case where a test circuit is divided.

FIG. 10 is a flowchart showing a conventional static timing analysis method.

FIG. 11 is a flowchart showing another conventional static timing analysis method.

FIG. 12 is a flowchart showing another conventional static timing analysis method.

[Explanation of symbols]

12 ... Microprocessor unit (MPU), 13 ...
Memory, 14 ... Display, 15 ... Keyboard.

Claims (2)

[Claims] 1. A storage means for storing a netlist, a construction means for constructing a transistor-level circuit structure from the netlist read from the storage means, and a node to which a clock signal input from an input means is supplied. A recognition means for recognizing from the constructed circuit structure; a discrimination means for discriminating whether or not the output of the circuit to which the clock signal is inputted can be high impedance from the circuit structure constructed by the construction means; If the output of the circuit can be high impedance,
First setting means for setting the output of this circuit as the start point of the path search and setting the inputs other than the clock signal of this circuit as the end point of the path search, and when the output of the circuit cannot be high impedance, A static timing analysis, comprising: a second setting means for setting an output of the circuit to a node for outputting a clock signal and setting an input node other than the clock signal of the circuit to an end point of the path search. apparatus. 2. A step of constructing a transistor-level circuit structure from a netlist, a step of recognizing a node to which a clock signal input from an input means is supplied from the constructed circuit structure, and a step of constructing by the constructing means. From the circuit structure described above, a step of determining whether the output of the circuit to which the clock signal is input can be high impedance, and if the output of the circuit can be high impedance,
Setting the output of this circuit as the start point of the path search and setting the input other than the clock signal of this circuit as the end point of the path search, and if the output of the circuit cannot be high impedance, then the output of this circuit is And a step of setting a node for outputting a clock signal and setting an input node other than the clock signal of this circuit as an end point of the path search.