EP0541216B1 - Data driven processing system - Google Patents
Data driven processing system Download PDFInfo
- Publication number
- EP0541216B1 EP0541216B1 EP92307642A EP92307642A EP0541216B1 EP 0541216 B1 EP0541216 B1 EP 0541216B1 EP 92307642 A EP92307642 A EP 92307642A EP 92307642 A EP92307642 A EP 92307642A EP 0541216 B1 EP0541216 B1 EP 0541216B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- instructions
- register
- instruction
- execution
- units
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4494—Execution paradigms, e.g. implementations of programming paradigms data driven
Definitions
- This invention relates to data processing systems.
- the performance of data processing units is improving at a rate greater than that of main memory (RAM) storage.
- RAM main memory
- the latencies involved in memory access are typically several times the average execution time of an instruction and can thus degrade performance dramatically. On the other hand, the latencies are not usually long enough to make it worth while switching to execute a different process while the memory is being accessed.
- the effect of memory latency on processor performance can be reduced by reducing the number of main memory accesses, for example by using a large, possibly multi-level cache.
- main memory accesses for example by using a large, possibly multi-level cache.
- cache miss rate for some types of application it is almost impossible to reduce the cache miss rate to less than 5% - 10% and in such cases memory access time can still dominate the overall processor performance.
- large database applications typically exhibit random access profiles to records which may be distributed within gigabytes of memory and in such a case the cache miss rate can be very high.
- the object of the present invention is to provide a novel data processing system architecture which overcomes or alleviates these problems.
- a data processing system comprising:-
- the invention provides the ability to run multiple independent data-driven instruction streams. Since the streams are independent, if instructions from one stream are held up by a memory access, it will in general be possible to continue processing another stream and hence the effects of memory latency will be masked.
- FIG. 1 is a block diagram of a data processing system embodying the invention.
- the system is designed to handle a plurality of independent processes simultaneously. Each of these processes has a unique context number allocated to it, and consists of an independent stream of instructions.
- the system includes a main memory 10, which holds both data (operands) and instructions. Copies of recently used instructions are held in an instruction cache 12, and copies of recently used operands are held in a data cache 14.
- the caches 12, 14 are small and fast relative to the main memory 10 and allow instructions and operands to be accessed rapidly, provided that they are available in the cache. Each entry in the caches is tagged with the context number of the process to which it relates.
- the system also includes a plurality of instruction prefetch and buffer units 16, one for each of a number of independent instruction streams.
- Each of these units 16 prefetches a sequence of instructions for a particular instruction stream, either from the instruction cache 12 (if the required instruction is available in the cache) or from the main memory 10.
- the prefetched instructions are held in a first-in-first-out queue, the process context number being stored along with each instruction.
- the instruction fetch and buffer units also perform branch prediction and speculative branch fetches.
- the system also includes a plurality of register renaming units 18, one for each of the independent instruction streams. These perform register renaming operations so as to map the architecturally defined process state registers (such as stack front register, accumulator and descriptor register) on to a number of physical registers in a register file 20.
- the renaming units 18 keep track of the renaming state of each process independently, but have common register allocation logic 22 for allocating registers to the streams in a globally unique manner.
- the instructions from the prefetch and buffer units 16 are fed, by way of the register renaming units 18, to an instruction scheduler 24, which schedules the instructions for execution and passes them to one of a number of execution units 26 and/or one of a number of memory address generation units 28.
- the operation of the scheduler 24 will be described in more detail below.
- the execution units 26 can operate in parallel to execute a number of independent instructions simultaneously. An instruction from any one of the instruction streams can be scheduled to any one of the execution units; the execution units need not be aware of the process context of the work they perform. Similarly, the address generation units 28 can generate memory addresses for a number of independent instructions simultaneously in parallel. The execution units 26 and address generation units 28 both have access to the register file 20 to allow them to read and update the appropriate registers.
- the outputs of the address generation units 28 are fed to common memory access unit 30 which accesses the data cache 14 or the main memory 10, so as to fetch the specified operands.
- the results from the execution units 26 and the memory access unit 30 are passed to a termination unit 32.
- the termination unit 32 For each process the termination unit 32 maintains a record of the most recent guaranteed correct state of that process, so as to allow recovery of the process in the case of exception.
- the termination unit 32 uses the process context number associated with each terminating instruction to index a state table so as to update the state of the process in question.
- the termination unit 24 feeds the results of terminating instructions back to the scheduler 24, for use by the scheduler in determining which instructions to schedule, as will be described.
- a physical register in the register file 20 may become free (ie eligible for re-use) if all instructions that could have made reference to that physical register have been successfully terminated.
- the termination unit 32 detects this, and passes the identity of the free register back to the register allocation unit 22 so that it can be reallocated.
- the scheduling unit receives the instructions from the instruction buffers 16, and determines which of these have all their operands available (as indicated by the results from the termination stage) and hence are eligible for immediate execution. If more than one instruction is eligible, one is selected on the basis of a predetermined scheduling policy (which may, for example, involve scheduling on a predetermined priority basis).
- the selected instruction is then passed to any available one of the execution units and/or memory address generation units, for processing as required.
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Description
This invention relates to data processing systems.
The performance of data processing units is improving at a
rate greater than that of main memory (RAM) storage. The
latencies involved in memory access are typically several
times the average execution time of an instruction and can
thus degrade performance dramatically. On the other hand,
the latencies are not usually long enough to make it worth
while switching to execute a different process while the
memory is being accessed.
The effect of memory latency on processor performance can be
reduced by reducing the number of main memory accesses, for
example by using a large, possibly multi-level cache.
However, for some types of application it is almost
impossible to reduce the cache miss rate to less than 5% -
10% and in such cases memory access time can still dominate
the overall processor performance. For example, large
database applications typically exhibit random access
profiles to records which may be distributed within gigabytes
of memory and in such a case the cache miss rate can be very
high.
The object of the present invention is to provide a novel
data processing system architecture which overcomes or
alleviates these problems.
According to the invention there is provided a data
processing system comprising:-
Thus, it can be seen that the invention provides the ability
to run multiple independent data-driven instruction streams.
Since the streams are independent, if instructions from one
stream are held up by a memory access, it will in general be
possible to continue processing another stream and hence the
effects of memory latency will be masked.
One particularly useful result of this is that it becomes
possible to trade memory bandwidth for low latency in memory
designs. High memory bandwidth can be achieved relatively
cheaply for example by using partitioned or interleaved
memories. Low-latency memories, on the other hand, requires
the use of faster technology, and this usually results in
greater cost and reduced scaleability.
Figure 1 is a block diagram of a data processing system
embodying the invention.
One data processing system in accordance with the invention
will now be described by way of example with reference to the
accompanying drawing.
The system is designed to handle a plurality of independent
processes simultaneously. Each of these processes has a
unique context number allocated to it, and consists of an
independent stream of instructions.
Referring to the drawing, the system includes a main memory
10, which holds both data (operands) and instructions.
Copies of recently used instructions are held in an
instruction cache 12, and copies of recently used operands
are held in a data cache 14. The caches 12, 14 are small and
fast relative to the main memory 10 and allow instructions
and operands to be accessed rapidly, provided that they are
available in the cache. Each entry in the caches is tagged
with the context number of the process to which it relates.
The system also includes a plurality of instruction prefetch
and buffer units 16, one for each of a number of independent
instruction streams. Each of these units 16 prefetches a
sequence of instructions for a particular instruction stream,
either from the instruction cache 12 (if the required
instruction is available in the cache) or from the main
memory 10. The prefetched instructions are held in a first-in-first-out
queue, the process context number being stored
along with each instruction. The instruction fetch and
buffer units also perform branch prediction and speculative
branch fetches.
The system also includes a plurality of register renaming
units 18, one for each of the independent instruction
streams. These perform register renaming operations so as to
map the architecturally defined process state registers (such
as stack front register, accumulator and descriptor register)
on to a number of physical registers in a register file 20.
The renaming units 18 keep track of the renaming state of
each process independently, but have common register
allocation logic 22 for allocating registers to the streams
in a globally unique manner.
The instructions from the prefetch and buffer units 16 are
fed, by way of the register renaming units 18, to an
instruction scheduler 24, which schedules the instructions
for execution and passes them to one of a number of execution
units 26 and/or one of a number of memory address generation
units 28. The operation of the scheduler 24 will be
described in more detail below.
The execution units 26 can operate in parallel to execute a
number of independent instructions simultaneously. An
instruction from any one of the instruction streams can be
scheduled to any one of the execution units; the execution
units need not be aware of the process context of the work
they perform. Similarly, the address generation units 28 can
generate memory addresses for a number of independent
instructions simultaneously in parallel. The execution units
26 and address generation units 28 both have access to the
register file 20 to allow them to read and update the
appropriate registers.
The outputs of the address generation units 28
are fed to common memory access unit 30 which accesses the
data cache 14 or the main memory 10, so as to fetch the
specified operands.
The results from the execution units 26 and the memory access
unit 30 are passed to a termination unit 32. For each
process the termination unit 32 maintains a record of the
most recent guaranteed correct state of that process, so as
to allow recovery of the process in the case of exception.
In order to achieve this the termination unit 32 uses the
process context number associated with each terminating
instruction to index a state table so as to update the state
of the process in question.
When an instruction is successfully terminated its result
becomes available to any instruction that requires this
result as an input operand. The termination unit 24 feeds
the results of terminating instructions back to the scheduler
24, for use by the scheduler in determining which
instructions to schedule, as will be described.
A physical register (in the register file 20) may become free
(ie eligible for re-use) if all instructions that could have
made reference to that physical register have been
successfully terminated. The termination unit 32 detects
this, and passes the identity of the free register back to
the register allocation unit 22 so that it can be
reallocated.
The operation of the scheduling unit 24 will now be described
in more detail.
The scheduling unit receives the instructions from the
instruction buffers 16, and determines which of these have
all their operands available (as indicated by the results
from the termination stage) and hence are eligible for
immediate execution. If more than one instruction is
eligible, one is selected on the basis of a predetermined
scheduling policy (which may, for example, involve scheduling
on a predetermined priority basis).
The selected instruction is then passed to any available one
of the execution units and/or memory address generation
units, for processing as required.
Claims (6)
- A data processing system comprising:-(a) a plurality of instruction buffers (16) for buffering instructions from a plurality of independent instruction streams,(b) a plurality of execution units (26), for executing instructions,(c) a termination unit (32) for receiving results of execution from the execution units and for producing indications of which operands are made available by said results, and(d) a scheduling unit (24) responsive to said indications from the termination unit, for determining which instructions in said instruction buffers have all their operands available and for assigning those instructions to the execution units for execution.
- A system according to Claim 1 further including a register file (20) for holding a plurality of physical registers, and a plurality of register renaming units (18) for mapping logical register identities from each of the instruction streams on to the physical registers.
- A system according to Claim 2 further including a register allocation unit (22), common to all the register renaming units, for allocating a free physical register to a logical register.
- A system according to Claim 3 wherein said termination unit (32) includes means for detecting when a physical register has been freed and for passing an identifier for that register to the register allocation unit.
- A system according to any preceding claim further including a main memory (10) and an instruction cache (12) for holding copies of instructions from the main memory, the instruction cache being connected to feed instructions to all said instruction buffers (16).
- A data processing method comprising the steps:-(a) buffering instructions from a plurality of independent instruction streams in a plurality of instruction buffers,(b) scheduling instructions from the buffers to a plurality of execution units for execution,(c) using results of execution from the execution units to produce operand availability information, and(d) using the operand availability information to control the scheduling of the instructions.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9123271 | 1991-11-02 | ||
| GB919123271A GB9123271D0 (en) | 1991-11-02 | 1991-11-02 | Data processing system |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0541216A2 EP0541216A2 (en) | 1993-05-12 |
| EP0541216A3 EP0541216A3 (en) | 1993-10-20 |
| EP0541216B1 true EP0541216B1 (en) | 1998-04-22 |
Family
ID=10703953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP92307642A Expired - Lifetime EP0541216B1 (en) | 1991-11-02 | 1992-08-21 | Data driven processing system |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5530816A (en) |
| EP (1) | EP0541216B1 (en) |
| JP (1) | JPH05224921A (en) |
| AU (1) | AU2744992A (en) |
| DE (1) | DE69225195T2 (en) |
| GB (1) | GB9123271D0 (en) |
| ZA (1) | ZA926505B (en) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5689673A (en) * | 1995-02-14 | 1997-11-18 | Hal Computer Systems, Inc. | Apparatus and method for controlling instruction flow by using a matrix of transmission gates in super-scaler microprocessor and selectively delaying microprocessor instruction execution based on resource availability |
| EP0870228B1 (en) | 1995-10-06 | 2003-08-13 | Advanced Micro Devices, Inc. | Unified multi-function operation scheduler for out-of-order execution in a superscalar processor |
| US5884059A (en) * | 1996-01-26 | 1999-03-16 | Advanced Micro Devices, Inc. | Unified multi-function operation scheduler for out-of-order execution in a superscalar processor |
| US5958042A (en) | 1996-06-11 | 1999-09-28 | Sun Microsystems, Inc. | Grouping logic circuit in a pipelined superscalar processor |
| US5848257A (en) * | 1996-09-20 | 1998-12-08 | Bay Networks, Inc. | Method and apparatus for multitasking in a computer system |
| US6035388A (en) | 1997-06-27 | 2000-03-07 | Sandcraft, Inc. | Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units |
| US6044438A (en) * | 1997-07-10 | 2000-03-28 | International Business Machiness Corporation | Memory controller for controlling memory accesses across networks in distributed shared memory processing systems |
| US6092155A (en) | 1997-07-10 | 2000-07-18 | International Business Machines Corporation | Cache coherent network adapter for scalable shared memory processing systems |
| US6122656A (en) * | 1998-07-31 | 2000-09-19 | Advanced Micro Devices, Inc. | Processor configured to map logical register numbers to physical register numbers using virtual register numbers |
| US6230262B1 (en) * | 1998-07-31 | 2001-05-08 | Advanced Micro Devices, Inc. | Processor configured to selectively free physical registers upon retirement of instructions |
| US6119223A (en) * | 1998-07-31 | 2000-09-12 | Advanced Micro Devices, Inc. | Map unit having rapid misprediction recovery |
| US6742111B2 (en) * | 1998-08-31 | 2004-05-25 | Stmicroelectronics, Inc. | Reservation stations to increase instruction level parallelism |
| US6341338B1 (en) * | 1999-02-04 | 2002-01-22 | Sun Microsystems, Inc. | Protocol for coordinating the distribution of shared memory |
| US6434714B1 (en) | 1999-02-04 | 2002-08-13 | Sun Microsystems, Inc. | Methods, systems, and articles of manufacture for analyzing performance of application programs |
| US6378066B1 (en) | 1999-02-04 | 2002-04-23 | Sun Microsystems, Inc. | Method, apparatus, and article of manufacture for developing and executing data flow programs, and optimizing user input specifications |
| CN1148647C (en) | 1999-08-30 | 2004-05-05 | Ip菲力股份有限公司 | Data processing system and its control method |
| DE10000960C1 (en) * | 2000-01-12 | 2001-12-20 | Infineon Technologies Ag | Data processing device |
| AU2001241487A1 (en) * | 2000-02-14 | 2001-08-27 | Chicory Systems, Inc. | Transforming a stack-based code sequence to a register based code sequence |
| US7035989B1 (en) | 2000-02-16 | 2006-04-25 | Sun Microsystems, Inc. | Adaptive memory allocation |
| US6546359B1 (en) | 2000-04-24 | 2003-04-08 | Sun Microsystems, Inc. | Method and apparatus for multiplexing hardware performance indicators |
| US6647546B1 (en) | 2000-05-03 | 2003-11-11 | Sun Microsystems, Inc. | Avoiding gather and scatter when calling Fortran 77 code from Fortran 90 code |
| US6802057B1 (en) | 2000-05-03 | 2004-10-05 | Sun Microsystems, Inc. | Automatic generation of fortran 90 interfaces to fortran 77 code |
| US6986130B1 (en) | 2000-07-28 | 2006-01-10 | Sun Microsystems, Inc. | Methods and apparatus for compiling computer programs using partial function inlining |
| JP4025493B2 (en) * | 2000-08-08 | 2007-12-19 | 富士通株式会社 | Instruction issuing device that issues instructions to the appropriate issuer |
| US6910107B1 (en) | 2000-08-23 | 2005-06-21 | Sun Microsystems, Inc. | Method and apparatus for invalidation of data in computer systems |
| DE10043003A1 (en) | 2000-09-01 | 2002-03-14 | Infineon Technologies Ag | Program controlled unit |
| US6957208B1 (en) | 2000-10-31 | 2005-10-18 | Sun Microsystems, Inc. | Method, apparatus, and article of manufacture for performance analysis using semantic knowledge |
| US7234144B2 (en) * | 2002-01-04 | 2007-06-19 | Microsoft Corporation | Methods and system for managing computational resources of a coprocessor in a computing system |
| KR100725091B1 (en) * | 2006-09-06 | 2007-06-04 | 최종욱 | Super Fertilizer |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3728692A (en) * | 1971-08-31 | 1973-04-17 | Ibm | Instruction selection in a two-program counter instruction unit |
| US4901233A (en) * | 1987-07-20 | 1990-02-13 | International Business Machines Corporation | Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries |
| US5247628A (en) * | 1987-11-30 | 1993-09-21 | International Business Machines Corporation | Parallel processor instruction dispatch apparatus with interrupt handler |
| GB8817911D0 (en) * | 1988-07-27 | 1988-09-01 | Int Computers Ltd | Data processing apparatus |
| JP2810068B2 (en) * | 1988-11-11 | 1998-10-15 | 株式会社日立製作所 | Processor system, computer system, and instruction processing method |
-
1991
- 1991-11-02 GB GB919123271A patent/GB9123271D0/en active Pending
-
1992
- 1992-08-21 DE DE69225195T patent/DE69225195T2/en not_active Expired - Lifetime
- 1992-08-21 EP EP92307642A patent/EP0541216B1/en not_active Expired - Lifetime
- 1992-08-27 ZA ZA926505A patent/ZA926505B/en unknown
- 1992-10-30 AU AU27449/92A patent/AU2744992A/en not_active Abandoned
- 1992-11-02 JP JP4293599A patent/JPH05224921A/en not_active Withdrawn
-
1994
- 1994-10-24 US US08/328,575 patent/US5530816A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0541216A3 (en) | 1993-10-20 |
| ZA926505B (en) | 1993-03-04 |
| DE69225195T2 (en) | 1998-09-24 |
| GB9123271D0 (en) | 1991-12-18 |
| AU2744992A (en) | 1993-05-06 |
| DE69225195D1 (en) | 1998-05-28 |
| JPH05224921A (en) | 1993-09-03 |
| EP0541216A2 (en) | 1993-05-12 |
| US5530816A (en) | 1996-06-25 |
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