JPS58127227A - Synchronous data bus having automatically changeable data speed - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD The present invention relates to bus systems for data transmission, and more particularly to digital data buses for communication within digital data processing systems.

Description of the Prior Art A digital data bus is a data bus for communicating digital data between a data processing device and one or more peripheral devices, such as a disk drive memory, terminal, or other data processing device. used in processing systems. Generally, the data buses used in such systems are either synchronous, in which data transfers occur in synchronization with a clock signal, or asynchronous, in which setup signals are synchronized with the transceiver.

In a synchronous data bus system, all data transfers are performed synchronously with a clock signal. That is, the operation of the transmitting and receiving device is synchronized with respect to the clock. Such systems use a single frequency clock or multiple or variable frequency clocks.Single frequency clock systems allow the use of a single clock circuit, but the data transfer rate and Overall system operation is limited by the data processing speed of the slowest element in the data processing system. In multiplex or L11 variable clock speed systems, the clock speed is selected to be the speed of the slower transmitting or receiving device then in communication. However, the data speed is
It can be selected to be the fastest rate achievable by the particular device being communicated with. Multiple or variable data rate synchronization systems are generally more complex than single clock rate systems because the clock circuitry must be able to generate many frequencies.

Also, before data communication takes place, the transmitting and preparing device must cycle through 1d to select a clock speed.

In an asynchronous data bus system, the previous step
1. Data transfer between the transmitting device and the receiving device is synchronized by a setup signal. That is, the transmitting device places data on the bus and sends a set-up signal to the receiving device to indicate that the data is on the bus. When the receiving device is ready to receive data, it accepts the data and sends a setup signal to the transmitting device to indicate that the data has been accepted. Asynchronous data bus
The system thereby allows a relatively large amount of data rate flexibility, and the data rate can be the highest selected between a particular transmitter and receiver pair. However, because of the requirement to exchange setup signals between transmitting and receiving devices, asynchronous data bus systems are generally more complex than synchronous systems. Additionally, maximum data rates are unattainable due to the requirement to resynchronize the data transferred at the transmitter and receiver. That is, data must first be sent from, for example, a disk drive to a sending device, then from the sending device to a receiving device, and finally from the busy receiving device to, for example, a data processor. This causes further delay in data transfer at the transmitting end of the bus when data is transferred from the peripheral element to the transmitting device 1U and from the receiving device to the bus. This delay is due to the fact that the data transfer between the peripheral element and the transmitter is
This occurs because the data transfer to the bus is not synchronized.

At the same time, since the reception of data by the receiving device 1d is not synchronized with the data transfer between the receiving device and the data processing device,
Another data transfer delay occurs on the receiving side.

The present invention consists of 1. The present invention provides solutions to these problems of the prior art, as discussed in detail below.

SUMMARY OF THE INVENTION The present invention relates to a digital data bus system that operates synchronously with a fixed clock rate and has a variable data rate selected by transmitting and receiving devices. The master controller is located, for example, in a data processing device. A peripheral controller is located on every other device or peripheral element of the data processing system. Peripheral elements include devices, intelligent terminals, and other data transmission links. The master controller and all peripheral controllers are connected via one bus. The master controller and peripheral controller each have an interface between the data processing device, the peripheral elements, and the bus. A fixed frequency clock is generated by a master controller and distributed to all peripheral controllers via a single clock line. In addition to the AT9 reply/data line, the signal line includes a single setup signal line called the hold line by the master controller and peripheral controllers. All data transfers are performed on clock pulses, but the data transfer rate is controlled by the particular transmitting and receiving devices. The transmitting device will place information, eg, addresses or data, on the bus in synchronization with the clock. If the receiving device is ready to receive this information, this information is transferred to the receiving device following the same clock and e-bus. If the receiving device is not ready to accept the information on the bus, it will force a hold signal on the hold line. The transmitting device responds with a hold signal (() when it holds the information sent on the bus 7 for each clock period for which the hold signal is forced. When the receiving device is ready to receive the information, the hold signal This information is sent out simultaneously with the next clock pulse. In this way, all information transfers are synchronized to a single frequency, i.e., fixed duration clock. However, the actual data transfer rate is variable and automatically determined by the particular transmitter and receiver to yield the maximum rate achievable by the particular transmitter and receiver pair.

Thus, the present invention can be used in a digital data bus system to automatically cause data transfers between two devices to occur at the maximum speed achievable by the devices of the two systems. It is advantageous to stay inside. The present invention is also useful in data bus systems since all data transfers are performed in synchronization with the data bus clock, thereby increasing the data transfer rate by de-synchronizing the data at the transmitting and receiving devices. It is further advantageous to incorporate the Since the present invention enables the aforementioned advantages with minimal hardware complexity, it is further advantageous to incorporate the present invention into a data bus system.

OBJECTS OF THE INVENTION It is therefore an object of the present invention to provide an improved data bus
Al to provide the system.

Another object of the invention is to provide an improved data bus system with automatically variable data transfer rates.

Yet another object of the present invention is to provide an improved data bus having automatically variable data transfer rates in which all data transfers are performed synchronously with a single fixed speed clock.
It is in the provision of the system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Other objects and advantages of the present invention will become apparent to those skilled in the art upon reference to the detailed description of the preferred embodiments and drawings herein.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 61. The structure and operation of a data processing system including a digital data bus using a preferred embodiment of the present invention will first be described, followed by a more detailed description of the structure and operation of the present system. System (FIG. 1) In FIG. 1, a block diagram of a data processing system including a Nomis system embodying the present invention is shown. The main components of this data processing system are a data processing unit (DP) 10 and one or more peripheral units (PU).
12, a system bus (SYSBUS) 14 that connects DPlo and all POs 12.

For example, the DPIO includes a central processing unit (CPU) 16,
It includes a main memory (MM) 1B and a bus system master controller (Mc) 2o. CPU 16 has a bidirectional interface to external components such as operator terminals via an input/output (Ilo) bus 22. CPU16 and MMlB are dual-purpose main memory devices, ? interconnected via a base (MMB) 24,
It has a bidirectional connection between MCCO2MMB24 and 5YSBUS14.

To explain the PO 12, each PU 12 has a peripheral element (PB) connected to it via a bidirectional peripheral node (PB) 30.
PD) 26 and a peripheral controller (PC) 2B. Each pc2B has bidirectional inputs and outputs connected to 5YSBUS14.

The bus system of the present invention is 5YSBUS14. ! l-1
It consists of MC20 and one or more PC2B.

Looking again at DPlo, data processing operations are generally performed by CPU 16 based on data stored in MMIB and according to instructions stored in MMIB.

There are two paths by which details and instructions can be written and read on the MMIB. The first path goes through I10 bus 22, CPU 16 and MMB 24. Second
The route is from PO12 via 5YSBUS14, MC20 and MMB24.

Generally, the path via I/O and ts 22 is
It can be used for low speed data transfers such as between LO and operator terminals. The path via 5YSBUS 14 can be used for high speed data transfer directly to and from MM 18. In this regard, the PD 26 interfaces with devices such as high speed disk drives, live memory, other CPUs, intelligent terminals, or even other data processing systems. Generally, data or instructions can be directly transferred from PD 26 to MMIB via 5YSBUS i4 and MC 20, read from MIJ 13 via MMB 24 to CPU 16, and manipulated by CPU 16. The results of these operations are then CP
The result is read from U16 to MMlB via MMB24, and finally the result is sent from MMlB to MC20 and 5Y.
It is read into PD2 (S via SBUS14).

Although the overall structure and operation of the data processing system incorporating the female system of the present invention has been described, the MC2Q,
The bus system including the 5YSBUS 14 (and one or more) PO 28 will now be described in more detail.

2. Bus system (Figure 2, Figure 2A, Figure 3) 2nd
With respect to Figures 1 and 2A, these figures are joined to form a block diagram of the bus system of the present invention. As mentioned above, such a bus system is
Includes BUS 14 and one or more POs 28.

a, system bus 14 (2L) As shown in FIGS. 2A and 2A, the 5YSBUS 14 includes address/data lines 32 and clock and control lines. The signals appearing will be discussed individually below, followed by a discussion of MC 20 and PC 2B, and finally some features of the operation of the bus system.

Regarding the address/data lines and clock and control lines of the 5YSBUS 14: (a) The address/data (A/D') line 32 is bidirectional and conducts both address and data. Further, as explained below, data transfer is performed by PO28.
It is started by a control word 9 which is applied unidirectionally to the MC 20 by. The control word contains an address that specifies the location in the MMIB where data is to be written or read. After control word Z1 is transferred, A
/D line 32 is used in both directions, MC20 and PC2
A data word is transferred between B and B. In this embodiment of this bus system, all data words sent out are 16 bits wide. A/D line 62 has individual 1
Six lines are included so that a complete data word can be transferred onto A/D line 62 in a single operation.

However, the address is larger than 16 bits, in which case A/D line 32 can be used to convey the lower 16 bits of the address.

(b) Regarding extended address (EA) line 34,
In systems where the MMIB address is larger than 16 bits, EA line 64 is used to convey another address bit. In this embodiment of the present bus system, the EA line 64 is 4 lines wide, so that pc2B is 2 lines wide in the MM1B
Addresses up to 0 bits can be used.

(C) For map-enabled (ME) lines 36, the MMIB's address space is larger than the address space directly addressable by the pc2B, or each PD 261 in the data processing system has an individual address space in the MMIB's address space. It is desirable to allocate portions. In this case, at9-less mapping is performed, i.e. p
The address given by c2s< is converted to the corresponding address in MMlB. When performing mapping, a mappable (ME) signal is provided by PC 28 to MC 20 on ME line 36 to begin data transfer.

(a) Word Count (WE) For line 3B, data transfers between PC 28 and MMlB consist of one or more data words. In this case, the control word provided by PC 28 to MC 20 to initiate the data transfer of multiple words 9 includes a word count number (wcN) that defines the number of data words to be transferred. The address provided on A/D line 32 as part of the control word defines the location in MMlB of the most likely data word of the sequence of data words 9 to be transferred. In this embodiment of the bus system, WGN is an 8-bit number and WC line 68 is an 8-bit number.
It consists of a line of books. In this example, VII
CN specifies the number of words to be transferred minus one, for example a WON of zero indicates that one data word should be transferred, a WCN of 8 indicates that 9 Gator Powers 9 should be transferred. Show that.

This conversion is performed for data up to 256 8-bit WCN.
- Enables you to define word data transfers.

(,3) Regarding the data-in (D'I) line 40, the PC 28 indicating DT transfer is connected to the data-in (D'I) line 40.
) is provided to the MC 20 as part of the control word that initiates a signal data transfer. This DI signal indicates whether data is transferred from the associated PD 26 of this PC 28 to the MMIB or from the MMIB to the associated PD 26.
Show which one will be forwarded to.

(f) Request (RQ) lines 42 include individual request lines for each pc2B and associated PD 26 of the data processing system. Each pc2B has one output connected to its corresponding request line and inputs connected from all request lines of R9 line 42. MC 20 has inputs connected from all request lines of R9 line 42.

Whenever a particular PD 26 requests access to MM1BK, the associated pc2B generates a request (RQ) signal on its associated request line. As explained further below, MC 20 and individual pc2Bs respond to the RQ multiplication signal on RQ line 42 by granting access to MMlB to the PD 26 with the highest priority. In this embodiment of the bus system, R9
Lines 42 include eight individual request lines so that up to eight PDs 26 and associated PCs 28 can access the MMlB via the bus system.
(g) The available (RDY) line 44 is a signal line connected from the output side of the MC 20 to the input side of each PC 28 of the data processing system. Whenever MC 28 receives an RQ double signal on any of the RQ lines 42 and access to the MMlB can be granted to the requesting PD 26, MC 20 sends a ready (F(DY) signal to R
It is generated on the DY line 44. PD requested with highest priority
26 and related PC2B are connected to this PD26 and MMl
It responds to the RDY signal by initiating data transfer between B and B.

(F parity in (PI) line 46 and parity out (po) line 48 are unidirectional single lines for conveying parity signals from PC2B to MC20 and M(:520 to PC28, respectively). These parity signals are used for the transmission of data or control words from the PC 28 to the MC 20, and for the transmission of data or control words from the PC 28 to the MC 20,
Error detection is performed every time a data word is transmitted from G2B to PC28.

(1) The aborted (AB) line 50 is a single wire, unidirectional line connected from the output side of each PC 28 of the data processing system to the MG 200A power side. The PD 26 and associated PC 28 currently executing the data transfer can terminate the transfer by forcing an abort (AB) signal to the MC 20 on this AB line 50. AB
Line 50 will respond to the AB signal input by terminating the data transfer.

(j) The error (ER) line 52 is a single-wire, unidirectional line connected from the output side of the MC 20 to the input side of each PC 2B. The MC 20 generates an error (E
R) will give a signal.

(k) The bus clock (BC) line 54 is a single-wire unidirectional line connected from the output side of the MC 20 to the input side of each PC 2B. BC line 54 transmits the bus clock from MC 20 to MC 28 in the data processing system. As further explained below, the bus
All data or control word 9 transfers to the system are performed synchronously with this bus clock signal.

(1) The holding line (HLD) 56 is connected to the MC 20 and each P
It is a single-wire bidirectional line connected to the input and output sides of C2B. During the transfer of control or data words, the receiving device, i.e. MC20 or pc2B, is placed on 5YSBUS14 by the use of the transmitting side by forcing a hold (HLD) signal on LD line 56. Indicates that the sending device is not yet ready to receive a word. and respond.

l), Master controller 20 (Figure 2) MC20
Specifically, connected between the A/D line 32 and the MM824 are an address/data driver/receiver (A/D/R') 5B and a data register (DTR).
) 60 and an address register (ADH) 62.

A/D/R 58 is a 16-bit line driver and receiver on the Honmaru side. The DTR60 has input and output sides connected with respect to the bidirectional input/output side of the A/D/R58 and the bidirectional MMB24.
It is a 6-bit register. ADH 62 is a 20-bit register that connects the 16-bit input/output side of register storage to the bidirectional input/output of A/D/R 58 and MMB 24. The remaining 4-bit input of ADH 62 is connected to Extended Address Line Receiver (EAR) 6404.
Connected from the bit output side. The 4-bit input of EAR64 is connected from EA line '54. ADH
The remaining 4-bit output of 62 is connected to MMB24. The control inputs of A/D/R 58, DTR 60, and ADH 62 are connected to the output of a master controller (MOC) +54, which will be further described below.

M~ via A/D/R58, DTR60 and ADH62: Address and data word transmission path between B24 and 5YSBUS14 and BA line 34 to EA
The extended address bit transmission path through R64 and ADH62 to MMB24 is indicated by an arrow. As mentioned above, in this embodiment, the transmission of the address word V, which is part of the control word prior to each data transmission, is unidirectional from PC 2B to MC 20 and MMlB.

However, the flow of data words 9 is bidirectional, i.e. data words can be sent from pc2B to MC20 and written to MMi3 indicated by the address word portion of control word P. , or from the location in MMIB indicated by the address word and transmitted from MC 20 to PO 28.

First, considering the transmission route of the address and part of the control word, the A/D line 32 and the EA line 6, respectively.
The 16-bit address placed by PO28 on A/D/R58 and the 4-bit address placed by PO28 on A/D/R58 and EAR6
Received by 4. At this time, the 16 bits of the address 9 which also receives the A/D line 62 is sent to the ADH via the MMB 24.
62 input side and stored. EA line'
54 to the ADH62 like the EAR64 and stored here. ◎After the recording, the 20 bits of the address stored in the ADH62 are transmitted to the MMB24 and the MMB24 is sent.
A location in the MIB can be addressed.

The data word appearing on A/D line 62 is
The received signal is sent by R58 to the input side of DTR6o, and is sent to the DTR6 (
). Data word 9 from MMlB to PO
2, 6, this data word is sent from MMlB via MMB24 to the input of DTR 60 where it is stored. The data word is then DT
R (sent from the output side of 5Q to MMB24, then PC
A/D/R58 to be received by A/D/R58.
D line 32 is busy.

As another embodiment of the invention, data word 9 is DT
A/D/R5 without buffering the memory in R6OK
8 can be directly transferred between the MMB 24 and the A/D line 32. In yet another embodiment, the EA lines 34, EAR 64, and ADR 62 can be configured as bidirectional transmission paths, such that the bus system of the present invention is fully bidirectional. address PO26.

Next, the word 9 count receiver (WCR) 66 and the word count counter (WCC) 68 will be described as described above (in this embodiment, the WC line 68 is a unidirectional line from the PO 28 to the MC 20). The WCN is received by 1R66 and sent to WCG68 for storage.
The N output is provided as the input voltage of the EAR64. As mentioned above and as further explained below, the WCN controls the data transferred between MM 18 and PD 26 during one data transfer.
Provided to MC 20 as part of the control word to indicate word count and initiate data transfer. The AT9 address given in the control word is then the initial abilise or starting AT9, which identifies the location in the MMlB of the first data word to be transferred.

Each data word 9 from PO26 to MM15:
Alternatively, since it is transferred from MMlB to PO26, EAR(54 decrements the WCN stored in wcc6BK, and correspondingly, the initial AT9 stored in ADH62
Increment response. ADR 62 thereby provides MMIB with a series of addresses indicating the location in MMIB of each data word transferred between MM 18 and PO 26.

Request game) (RQG) 70 is explained as RQ
G70 is a multiple input line register/ζ whose inputs are connected to each of the RQ lines 42. RQG7Q is the request (RQ) signal from pc2B in the data processing system.
When appearing on any of the Q lines 42, it will produce an output to the EAR 64.

As explained further below, the EAR64 is enabled when the MMIB is enabled for data transfer.

A ready (RDY) signal is placed on the RDY line 44 via the dynamic circuit (RD) 72 (and thereby RQC).

It will respond to the output of 70.

The remaining power elements of MC20 are EAR64 and SYSBUS1
4 line driver-receiver interfaces with the remaining control and clock lines. In this regard, map enable register <(MER) 74 and data in receiver (DIR) 76 are connected to the ME storage line and the DI line to the input of EAR 64, respectively. ξRetain in receiver: (P
IR)78 and ξRetain Out Driver (POD)
80 are connected from the PI line 46 to one input end of the EAR 64 and from the output side of the EAR 64' to the PO line 4B. Similarly, the truncated receiver f(A
H) 82 and error driver (ED) 84 are connected from AB line 0 to the input side of EAR64 and EAR6, respectively.
4 is connected to the ER line 52 from the output side.

It is connected to the BC line 54 via an i-clock driver (CD) 86 that outputs a 1R64 bus clock. A hold dry node (HI) 8B and a hold receiver (HR) 90 are connected from the hold output and hold input sides of the EAR 64 to a single bidirectional HLD helix 56, respectively.

Finally, speaking about EAR64, EAR64 is 5Y
Receives control signal input from PG 28 via SBUS14, and further sends a control signal to pc2 via 5YSBUS14.
B and Mc20 DTR60, ADR62 and WC
Provided for various elements such as C68. EAR64 is also M
It is a control interface between C20 and DPIO, and D
Coordination of P100 action and No2 system processing. For example, EAR (54 is the CPU 16 for data transfer between MMIB and PD 26 and access to MMIB).
requirements, so that MM 18 access time is used most effectively and contention between PD 26 and CPU 16 is avoided.

The specific clock and command interface between the EAR64 and DPIO is determined by the specific configuration and operation of the DPlo and is not described in the text. For example, the bus system shown in the text is synchronous, where all data transfers occur synchronously with a female clock signal provided on BC line 54, and where it is desirable for the bus clock to be synchronized with the MMIB's internal clock and timing. It is a type.

For some forms of DPIO, the MMlB can operate under the control of an internally generated clock.

)2 bus clock can be derived from this MMIB's internal clock, so that all data transfers via this bus system are synchronized with the MMIB's internal clock. In another form of DPlo, the CPU 16 provides the clock for the MMlB, so the bus clock can be provided from the CPU 16 clock 6-h, or synchronized with this clock. In yet another embodiment, the MMIB may include internal microcode circuitry to control its internal operations and data transfers. In this case, the EAR 64 would likely obtain control inputs from, and provide control outputs to, the MMlB's internal microcode circuitry. In yet another embodiment, MMlB is controlled directly or indirectly by internal microcode circuitry of CPU 16, so that EA
The control interface of R64 is to CPU16.

Similarly, regarding the internal structure and action of EAR64,
The configuration of such control circuits is well known to those skilled in the art and will not be described in detail herein. The functionality and constructional requirements of the EAR64's internal circuitry will be apparent to those skilled in the art from the description of the bus system provided herein.

C0 Peripheral Controller 28 (FIG. 2A) Referring to pc2B, as shown in FIG. 2A, PO 28 is similar to MC20 in almost all respects, so the only differences between PC2B and MC20 will be discussed below. I'll decide.

First, POG66 and HLD56, BC line 54, ER line 52, AB line 50, po line 48, PI line 46,
Regarding the interface of PO28 between RDY line 44, DI line 40 and ME line @56, MG2
Q includes line dry; or receiver pc2B
PO 28 is similar to MC 20 except that each includes a line receiver or driver. Therefore,
Holding function of PO28, t(HD) 94, holding receiver ()IR) 96, clock receiver (OR) 98
, an error receiver (ER) 100, an abort driver (AD) 102, and a parity out receiver (F
OR) 104 and parity in driver (PID
), 106, enable receiver (RR) 108, data in driver (DID) 110, map enable driver (MED) 112, and extended address driver (EAD) 114, respectively, of the HD9Q of the MC 20.
, HD88, CD86, ED84, and AF182
, POD80, ・PIR7B, RD72, DI
Corresponding to R76, MER74 and EART64 (
,ru.

PC:28 also has MC20's DTR60, A
A data register (DTR) 116 similar to the DR62 and A/D/R58, and an address register (ADH)
) 11B and an address/data tri-input/V receiver (A/D/R) 120. DTF of PO28 (
116, ADR 118 and A/D/R 120 are indicated by arrows and are similar to those of MC2Q, except for ADH 118. In PO28,
An address is given to pa2B by the associated PD 26 and stored therein.

In this example, the basic 16 address bits and four extended address bits are each ADR118.
The signal is transferred in one direction from the A/D line 32 to the EA line 34.

To explain the output of PC2B to the WC line 38, in this embodiment, PC2B outputs wctq in one direction.
is given to the MC 20, and unlike the MC 20, it is not necessary to generate a series of MMlB addresses. Therefore, the output of PO 28 to WC line 38 consists only of word count driver (van) 122.

That is, PC2B does not include registers/colors similar to wcc6B. In another embodiment of the invention where the bus system is completely bidirectional, PO28 is WC068
It has a word count register similar to . P.O.
28 WCC68 is MC2Q WCC68 and WCR6
6 and WGD 122 are bidirectional so that MC 20 can provide addresses to PO 28.

In this embodiment, the actions of ADH 52 and ADH 118 are similarly modified.

PO 28 includes a request driver (RQD) 124 connected from the output of PGG 92 to RQ line 42 associated with PO 28 and its associated PD 26 .

Whenever PD26 associated with PC2B requests access to MM1B, PO28 connects to associated RQ line 4.
2, an RQ multiplied signal is generated via the RQD 124. As mentioned above and as further explained below, the associated PD
MC 20 can respond at this time by allowing MMlB to access MMlB.

Associated with RQD 124 of PO 28 is Request Priority Gate (RQPG) 1:26. RQPG126
is a multi-input gate with an input connected to each RQ line 42 associated with a PD 26 that has a high priority for access to the MMlB. Whenever a double signal is placed, all PC2B RQPGs 126 associated with a lower priority PD 26 produce an output indicating that a higher priority request is present on the bus system. PCC 92 disables RQPG 126 by inhibiting its requested output via RQD 124.
In response to output like this from . The output of RQPG 126 also inhibits the ability of PO 28 to respond to RDY signals from MC 20 on RDY line 44. This effect is
that there is only one single-RQ signal at any time, that it is the highest priority PD requesting access to the RQ double signal MM1B, that all lower priority PDs 26 with requests for access to MM'18 are
It will be prohibited to respond to the RDY signal response 20 from C20. However, the highest priority response requesting the PD 26 to the RDY signal on the RDY line 44 is not prohibited;
D26 responds to the RDY signal of MC20 to
Data transfer is started by B.

Finally, to explain PCG92, MC20's EA
The statements made earlier in connection with R64 also apply to each PG28 P
This also applies to CC92. PCC in this perspective
The main difference between EAR92 and EAR64 concerns the bus clock. All PCs 28 in the bus system are connected to the BC line 54
, and its operations are synchronized with the bus clock. Data transfer between PC 28 and MM 18 can thereby be fully synchronized with the operation of MM 18. In a preferred embodiment of the invention, each pc2
B's PCC 92 provides a bus clock to the associated PD 26 so that the operation of the associated PD 26 can be synchronized with the bus clock. In this case, the data transfer is completely synchronized throughout and is the same as the bus clock.

Having described the structure and operation of the individual components of the bus system of the present invention, including 5YSBUS 14, uc20 and PC28, the overall operation of the system bus is described and summarized below.

d. Operation of the bus system (FIGS. 2, 2A, and 6) As described above (whenever a PD 26 requests access to the MM 18, the associated PC 28 of this PD 26 is connected to the associated RQ line 42). If a higher priority PD 26 requests access to the MM 18 at the same time, the request by the lower priority PD 26 and the RQ signal on the RDY line 44 of its associated pc2B are generated.
Responses to the DY signal are prohibited. MC2
0 is R when access to MM 18 is possible.
, DY responds to the RQ double signal appearing on RQ line 42 along with the RDY signal on Y line 44.

The PC 2B of the 5PD 26, which has made the highest priority request, connects the MC 2 on the RDY line 44 by starting data transfer.
It responds to an RDY signal of 0. In the first step, pc2B places control word 9 on 5YSBUS14. The control word includes a 16 bit address on A/D line 32 and a 4 bit extended address on EA line 64. The control word also includes, if mapping is to be performed, a WCN on WC line 38, a ME double signal on ME line 66, and a DI signal on DI line 4o indicating which direction data transfer is to occur. Includes 19
... have parity bits on the PI line 46 for error checking.

MC2Q and pc2B now begin data transfer by transferring data word 9 onto A/D line 32 in bus clocked synchronization. Each data word is routed to either PI line 46 or PO line 4 depending on the direction of data transfer.
It is accompanied by a parity bit at 8.

If the data transfer is from PC 28 to vc 20, and MC 20 indicates a ξRetility error in the received control word or f-ter word 9, then
MC:20 during consecutive bus clock cycles;
The ER multiplication signal will be forced onto the ER line 52. The sending side PC 2B prevents such E by forcing an AB double signal on the AB line 50 at the same time as finishing the data transfer.
It responds to the R times signal. MC 20 responds to the AB double signal by immediately terminating the current data transfer. If a retention error is detected in a pig transfer from MC 20 to PC 28, then the receiving PC
2B can be selected to terminate the data transfer by forcing K in the same way as the AB double signal.

Signal data transfers thereby consist of a control word and one or more data words. The transmission and reception of control or data words are each performed on the bus clock, so that the operation of the bus system is synchronized.

As mentioned above, DPlo and each P of the data processing system
D26 can have different data rate capabilities. However, it is desirable that the period of the bus clock be that of whichever element, DPlo or PD26, has the fastest data transfer capability. In most cases, the period of the bus clock is determined by DPlo. Operation of the synchronous bus system is accomplished through the use of a hold (HLD) signal, along with the ability to automatically adjust the data transfer rate to the lower of the pair of communicating devices in the data processing system. .

As mentioned above, by forcing the HLD signal onto HLD 56, the device receiving the data transfer, either MC 20 or PC 28, is not yet ready to receive a control or data word placed on 5YSBUS 14. Can be displayed. The sending device receives the HLD signal by holding the control or data word then issued on 5YSBUS14 until the HLD signal is terminated.
Responds to the LD signal. Completion of the transfer of the held control or data word will occur simultaneously with the next female clock after the HLD signal terminates.

In Figure 5, MC2 for varying data rates
0, PC2B and HLD signals are shown.

The top line in FIG. 6 shows a bus route with an I/F period. The next two lines, case A, illustrate the behavior of a bus system in which both the sending and receiving devices have data rate capabilities equal to or greater than the bus clock. As shown in case A,
The HLD signal is not forced and the data word P or control word is transferred simultaneously with each bus clock pulse.

Referring to the second pair of lines in Figure 3, Case B&C, the behavior of a system bus in which either the sending or receiving device has a data rate capability of half the clock rate is shown. . In this case, the word N
Referring to the period shown as , the HLD signal is forced during the first, one bus clock period and released at the end of this bus clock period. The data control word being transferred, word KN, is held on 5Y8BUS14 by the sending device during the first and second bus clock periods. The transfer of control or data word r is completed at the end of the second bus clock period and the next data word r or control word 9 is placed on the third bus, 5YSBUS14, at the beginning of the clock period. At the beginning of the third bus clock period, the HLD signal is re-forced and remains forced during the sixth bus clock period, such that the transfer of the second word occurs during the fourth bus clock period. It will be completed at the end.

The last two lines in Figure 6, Case G, indicate that the data transfer rate between the pair of sender and receiver devices is 7/3 of a missed clock. Transfer is shown. Data or force words are transferred at the end of equal time intervals where each time interval is equal to one bus clock period, so that the data transfer rate is equal to -3/3 of the bus clock speed. .

This effect is accomplished by forcing the HLD signal during the first two bus clock periods of each of six bus clock time intervals.

As can be seen by comparing cases A, B, and C in Figure 6,
The data transfer speed of case B is half that of case A,
The data transfer rate in case C is -third of that in case A. However, in each case, all data transfers occur synchronously with the bus clock. The data transfer rate is automatically adjusted by the sending and receiving devices to that of the lower power of the sending and receiving device pair by the action of the HLD signal.

The invention of the bus system described above thereby enables a fully synchronous data bus with automatically adaptable and changeable data transfer rates.

The bit system described herein thereby allows data transfers between sending and receiving devices to be performed at the maximum speed achievable by each device while maintaining synchronous operation.

The invention may be embodied in other specific forms without departing from its spirit or inherent characteristics. - By way of example, the above-mentioned bus system can be applied to data "systems other than those mentioned in the text, i.e. in any case where the transfer of digital data is required. - The system can be modified to be fully bidirectional in both data transfer and addressing. As such, the embodiments herein should be considered illustrative in all respects and not restrictive. Rather, the scope of the invention is indicated by the appended claims rather than by the description in the main text, and it is therefore intended to embrace all modifications that come within the meaning and range of the claims.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data processing system including a data bus system, FIGS. 2 and 2A are block diagrams of the data bus system shown in FIG. FIG. 3 is a timing diagram illustrating the operation of the data bus system shown in FIG. 10---DP, 12---PU, 14---8Y
SBUS. 16---CPU, 18---MM, 20---Mo. 22--I 10 bus, 24-11++MMB, 26
---PD. 2B---Pp, 3O---PB, 32---A/D line, 34---EA line, 36---M/E line,
38---WeH line, 4Q---DI line, 42---
RQ line, 44---RD Y times 1.46--P
I line, 4 B---PO line, 5Q---AB line, 52---ER line, 54---80 line, 56---
-HLD, 58---A/ID/R, 6O---DTR
. 62---ADR164---EAR16 Low-VO
R16B---WCC170---RQG, 72---
RD, 74---MER. 7low-DIR, 78--PIR, 8O--PO
D. 82---AR, 84---ED, 86---CD, 8
8---HD, 90--HR, 92--PCC, 9
4---HD, 96---HR, 98---OR110
0---ER. 102---AD, 104---POR, 106---
PID, 108---RRlilQ---DID, 11
2---MED. 114-1-EAD, 116--DTR1118--
-ADR. 119---ADRll 2O---A/D/R, 12
2---WC:D, 124---RQD, 126---
RQPG. Patent applicant Data General Corporation (
4 persons) Mr. Kazuo Wakasugi, Official of the Patent Office 1. Display of the incident 1982 Patent Application No. -271717 2, Name of the invention (1-f Kael'ft is raised by hard-hearted η and F game Tama L duck ha (1〕-〕4-sito=11+'+day 2'Relationship with the amended person's case - Patent applicant's address, design, child's office, corporation! V-ense'/
4. Agent 5. Subject of amendment

Claims (1)

Scope of Claims: (1) A processing device that processes data, a main memory that stores at least the data, at least one peripheral device, information including an address of the main memory, and a main memory that stores the data. In a data processing system including a data processing system including a storage device and a plurality of said peripheral devices, a bus device is provided, said bus device having a plurality of addresses/data for transmitting said information. With data recovery. a master controller device comprising a clock line for transmitting a clock signal and a hold line for transmitting a hold signal, the mask controller device being connected to the clock line for providing a clock signal having a fixed period of time; a clock device connected between the address/data line and the main memory for storing the information in response to the clock signal and transmitting the information to the address/data line and the main memory; a master register device that transfers data in synchronization with the clock signal, and an output connected to the holding line and an input connected to the holding line; (b) providing a hold signal on the hold line in response to operation of the main memory during each of the clock signal periods during which the peripheral device is not ready to receive the information provided on the address/data line; providing control signals to the master controller device and the main memory device in response to the hold signal provided on the hold line by a peripheral controller device associated with the peripheral device device during the period of the clock signal; and the information stored in the previous 11C master register device for transfer to the peripheral device device on the address/data lines during the clock signal period. a master holding control device for maintaining the address/data lines and associated with each of the peripheral device devices; said clock line Lf) is connected between said clock line Lf) to store and hide said information in response to said clock signal; , a peripheral register device for transferring said information, an input connected to said holding line, and an output connected to said holding line; A hold signal is output on the hold line during each of the periods when the device is not ready to receive the information provided on the address/data line by the master controller device. :I+E, (b) During the period of the clock signal, the master -
In response to the hold signal provided on the hold line by a controller device, a control signal is provided to the associated peripheral device device and the peripheral controller device to maintain the address/data during the clock signal period. a peripheral holding control device that maintains the information stored in the peripheral register device for transfer to the master controller device on a line. 2. The bus device further comprises: transmitting a request signal from the related peripheral controller device to the master controller device when the related one of the peripheral device devices requests access to the main memory device; a plurality of request lines, each associated with a corresponding one of said peripheral device devices; and an availability line for transmitting an enable signal from said master controller device to each of said associated peripheral controller devices. The main controller device further comprises: in response to the troughs of the request signal appearing on each of the request lines and the action of the main storage device, the main storage device a request response device for providing an enable signal on said one enable line when enabled for transferring said information to and from said peripheral device requesting access to said peripheral device; The above-mentioned valleys of peripheral controller devices are historically 1. - having an output connected to said associated one of said request line, responsive to the action of said associated peripheral element device when said barrier peripheral element device requests access to said main storage device; a request generating device for providing a request signal on said associated one of said request lines; said peripheral element device having an input connected from each of said request lines and having a relatively high priority; When the other party requests access to the main memory, 11!I Ar':
a request priority device for inhibiting access of the associated peripheral device to the main memory in response to the request signal provided thereon by another of the peripheral controllers associated with the other of the peripheral device devices; In response to the enable signal and the operation of the request priority device, when the associated peripheral device has the highest priority of the peripheral device requesting access to the main memory, the associated 2. The bus system device according to claim 1, further comprising a transfer control device for providing a control signal for inhibiting said transfer of said information between said peripheral device and said main memory device. 3. The information is transferred between the main memory and the peripheral device in the form of words, each of the words containing an equal number of information bits, and one transfer of the information said bus device further comprises a word count representing the number of said words 9 transferred between said peripheral device device and said main memory device in said one transfer of said information. said peripheral register device of each said peripheral controller device associated with said peripheral device device includes a plurality of word count lines for transmitting data lines from said associated peripheral device device to said peripheral device device; the first one of said words to be transferred
a peripheral start availability register device for storing and transmitting a starting address representing a location in said main memory to said address/data line; and said word count from said associated peripheral device device; a peripheral word count register device connected to the line for storing said word count number representative of said number of words to be transferred and transferring it to said word count line; the master register device includes: a master starting address device connected by the address/data line to store the starting address and transfer it to the main memory; and a word count number. a master word count register device for receiving and storing a master word count register device, the master controller being responsive to the word count stored in the master word count register device and the clock; and maintains a line signal to the main memory when said corresponding successive words are transferred between said main memory and said peripheral device. an address control device for providing control signals to the master starting address register device to sequentially increment the stored addresses so as to provide successive addresses representing successive locations in the main memory; The bus according to claim 2, characterized in that:
System equipment. 4. The No. 2 device further includes the master controller device and the peripheral device device 9.
a parity line device connected between each of said address and data lines for transmitting a parity signal regarding said information present on said data line; and said respective of said peripheral element devices from said master controller device. an error line for transmitting an error signal to the master controller; and an abort line for transmitting an abort signal from each of the peripheral device devices to the master controller device, the master controller device further comprising: a) in response to said information being transferred from said X-star controller device to said one of said peripheral, component devices, providing a parity signal to said parity line device regarding said information to be transferred; 1)) in response to said information and said associated parity signals received on said address, data line and said parity line devices from said each of said peripheral device devices;
a parity device for providing said error signal on said error line when an error exists in said received information; and said parity device in response to an abort signal provided on said abort line by said one of said peripheral device devices. an abort control device for providing control signals to the master controller device and the processing device to terminate the current transfer of information, each of the peripheral controller devices further comprising: In response to said information being transferred to a master controller device,
a parity device providing a parity signal on the parity line device regarding the information to be transferred; and a parity device receiving and receiving the information and the parity from the master controller device on the address/data line and the parity line device. In response to a signal, a control signal is sent to the peripheral device to indicate when a nominality error exists in the received information and to terminate the current transfer of the information; 7. The bus system device according to claim 6, further comprising an abort device for selectively applying the abort signal to the bus system. 5. said information is transferred between said main memory device and said peripheral device device in the form of words, each said word containing an equal number of information bits, and one transfer of said information the bus device further comprises a word count number representing the number of words transferred between the peripheral device device and the main memory device in the one transfer of the information; Contains a plurality of word count lines for transmitting 1. . The peripheral register device of each of the peripheral controller devices associated with the peripheral device is connected to the address/data line from the associated peripheral device to register the word to be transferred. a peripheral start address register device for storing a starting address representing a location in one of said main memory devices and transferring it to said address/data line; - a peripheral word, count register device connected to a counting line for storing said word 9 count representing said number of words to be transferred and transferring it to said word counting line; the master register device includes: a master start address device connected through the address/data line to store the start address and transfer it to the main memory; and a master start address device connected through the word count line. a master word count register device connected to receive and store said word count number, said master controller device further comprising: said word count register device connected to said word count register device; - said master starting address register device for holding said signal in response to a count number and said clock when said corresponding successive words are transferred between said main memory device and said peripheral device device; 5. providing control signals to said master starting address register device to sequentially change said stored addresses so as to provide said main memory with consecutive addresses representing consecutive locations in said main memory; 3. The system of claim 2, further comprising an address control device that increments the number of addresses. 6. The bus device further comprises: when the related one of the peripheral device devices requests access to the main memory device 111c, the bus device receives the information from the master controller from the related peripheral controller device;
A request signal is transmitted to the controller device. a plurality of request lines, each associated with a corresponding one of said peripheral device devices; and an enable line for transmitting an enable signal from said master controller device to each of said associated peripheral controller devices. and the main controller device further comprises: in response to the request signals appearing on each of the request lines and the operation of the main memory, the device Aλ.
a request response device that provides an enable signal on the enable line when the device is available for transferring the information between the main memory device and the peripheral device device requesting access to the main memory device; and each of said associated peripheral controller devices further has an output connected to said associated one of said request lines, said associated peripheral device device having access to said main memory device. a request generator for providing a request signal on said associated one of said request lines in response to action of said associated peripheral device device when making a request; and an input connected from each of said request lines; , when the other of the peripheral devices of relatively high priority requests access to the main memory, the request signal provided thereon by the other of the peripheral controllers associated with the other of the peripheral device devices; a request priority device responsive to inhibiting access of the associated peripheral device to the main memory; and a request priority device responsive to the enable signal and the action of the request priority device. has the highest priority of the peripheral device requesting access to the main memory, a control signal inhibiting the transfer of the information between the associated peripheral device and the main memory. 6. The bus system device according to claim 5, further comprising a transfer control device that provides a transfer control device. 7. The bus device further comprises a parity bus connected between the master controller device and each of the peripheral device devices to transmit a parity signal regarding the information present on the address 7,.' data line. a line device, an error line for transmitting an error signal from the mask controller device to each of the peripheral device devices, and an error line from each of the peripheral device device to the mask controller device; an abort line for transmitting an abort signal; , transmits a parity signal regarding the information to be transferred to the parity
(b) in response to said information received on said address/data line and said parity line device from said each of said peripheral device devices and said parity line device; a parity device for providing said error signal on said error line when an error exists in said received information; and said information in response to an abort signal provided on said abort line by said one of said peripheral device devices. an abort control unit for providing control signals to said master controller unit and said processing unit to terminate the current transfer of said peripheral controller units, each of said peripheral controller units further including one transfer from said associated peripheral element unit to said master controller unit; - In response to the information being transferred to a controller device, transmitting a parity signal regarding the information to be transferred to the parity controller.
a parity device for providing a parity device on a line device; a control signal to the peripheral device to indicate the point in time present in the received information and to terminate the current transfer of the information; and to the abort line, the abort signal. 7. The bus four-stem system of claim 6, further comprising a selectively providing truncation device. 8. The bus device is further connected between the master controller device and each of the peripheral device devices to transmit a signal regarding the information present on the address 7/f-even line. a parity line device; an error line for transmitting an error signal from the master controller device to each of the peripheral child devices; and an error line for transmitting an error signal from each of the r+iJ peripheral device devices to the master controller device. and an abort line for transmitting an abort signal to one of the peripheral element devices, the master controller device further comprising:
In response to said information being transferred to said node, said node transmits a parity signal regarding said information to be transferred.
(b) detecting a parity error in response to said information and said associated parity signal received on said address/data line and said parity line device from said each of said peripheral device devices; a parity device for providing said error signal on said error line when present in said received information; and said parity device for providing said error signal on said abort line when present in said information in response to an abort signal provided on said abort line by said one of said peripheral device devices. an abort control device for providing control signals to the master controller device and the processing device to terminate the transfer of the data, each of the peripheral controller devices further comprising: in response to said information being transferred to a device, providing a parity signal on said parity line device regarding said information to be transferred; and on said address/data line and said parity line device; in response to the information received from the master controller device and the parity signal, indicating the point in time when a ξ parity error exists in the received information, and terminating the current transmission of the information. Claim 1Ee further comprising: an abort device that selectively applies a control signal to the peripheral element device and selectively provides the abort signal to the abort line.
J's No. 2 system device. 9. The bus device further comprises: when the related one of the peripheral device devices requests access to the one-day storage device, sends a request signal from the related peripheral controller device to the mask controller device; a plurality of request lines, each associated with a corresponding one of said peripheral device devices, for transmitting an enable signal from said master controller device to each of said associated peripheral controller devices; an available line, and the main controller device further comprises: in response to each of the request signals appearing on each of the request lines and the operation of the main memory, a request response device for providing an enable signal on the enable line when enabled for transferring the information to and from the peripheral device requesting access to main memory; Each of said controller devices further has an output connected to said associated one of said request lines, wherein said associated peripheral element device requests access to said main memory device. a request generating device for providing a request signal on said associated one of said request lines in response to action of a peripheral element device; When the other one of the peripheral device devices requests access to the main memory device, the one of the peripheral device devices in response to the request signal applied by the other one of the peripheral controllers associated with the other peripheral device device; a request priority device that inhibits access of an associated peripheral device to the main memory; and in response to the enable signal and the operation of the request priority device, the associated peripheral device device accesses the main memory. between the associated peripheral device and the main memory when the peripheral device has the highest priority requesting access to. 10. The bus system device according to claim 8, further comprising a transfer control device that provides a control signal for inhibiting the transfer of the iJ information. 10. The information is in the form of a word. and the main storage device -I
I peripheral device device, each of said words containing an equal number of information bits, one transfer of said information comprising a transfer of at least one said word, said bus device further comprising: a plurality of word count lines for transmitting a word count representing the number of words transferred between the peripheral device device and the main memory device in the one transfer of the information; The peripheral register device of each peripheral controller device associated with a peripheral device is connected to the address/data line from the associated peripheral device to register the first word of the word to be transferred. a peripheral starting address register device for storing and transferring a starting address representing a location in one of said main memory devices onto said address/data line; and said word nine count from said associated peripheral device device. a peripheral word count register device connected to the line for storing said word count number representative of said number of words to be transferred and transferring it to said word count line; The master register device is connected by the word count line to a master start address device connected by the address/data line to store the start address and transfer it to the main memory device. a master word count register device for receiving and storing the word count number, the master controller further comprising:
The master word count register device is stored in the master word count register device and holds the signal in response to the word count number and the clock so that the corresponding successive word counts are stored in the main memory. When transferred between a device and the peripheral device device, the master starting address register device provides to the main memory device successive addresses representing successive locations in the main memory device. 10. A bus system as claimed in claim 9, including an IP address controller for providing control signals to a master starting address register device to successively increment the stored address. .