JP3137581B2 - A system that changes the video size in real time with a multimedia-capable data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to video signal processing, and more particularly to a data processing system for providing digital signals of video and graphics information, and more particularly to a data processing system that supports multimedia. Real-time scaling of video and graphics information stored in

[0002]

2. Description of the Related Art In video signal processing technology, there is usually one central processing unit having control of a bus, and all other attached components are connected to the central processing unit by a bus. As a result, the possible transactions are significantly limited because only one processing unit executes the application and controls the graphics subsystem. This works well for low resolution graphics applications only. There are add-on cards that allow some acceleration in the graphics control chip. Such an improvement saves bandwidth and allows some high-level commands to be offloaded to the graphics subsystem. For example, the central processing unit may send a command to draw a line or a rectangle and just send the coordinates to the graphics subsystem. This speeds up the process compared to sending information on a pixel-by-pixel basis. This approach works fine for low-resolution graphics. However, for applications with higher resolution, the load on the central processing unit may increase. Thus, at higher graphics resolutions, it was possible to add acceleration to accelerate some graphics operations, but ultimately the computer system could not maintain the actual bus bandwidth of a typical bus, or It has reached a point where it is not possible to maintain extremely high update rates for graphic images. This is further complicated by the addition of video. Video must be updated at 30 frames per second, and the graphics subsystem may require 5 to 9 megabytes per second of sustained bandwidth on some buses.

To achieve the goal of achieving an integrated video and graphics system, there is a need for a system market texture that balances the requirements often encountered in the video and graphics subsystems. For example, increasing the horizontal and vertical resolution is useful for graphic images,
Increasing the horizontal and vertical resolution in the video subsystem can be quite expensive, and the image quality may not change appreciably. Similarly, in a graphics subsystem, pixel depth and the number of colors that can be used simultaneously are important, but not in a video system. While 16-bit semi-pure pixels are suitable for video systems, it may be advantageous to use 24-bit pixels for graphics systems.

Also, realizing real-time video usually requires changing the video size, especially for multimedia applications. Real-time video requires bandwidth downscaling and video downscaling to accommodate the various video compression algorithms typically used to store and transfer video. In addition, video decompression (decompression) requires upscaling (enlargement) or zooming of the video during display to improve visibility. Decimation by pixel drop is video downscaling
And interpolation by pixel duplication is one method of upscaling.

A typical video capture / playback adapter is NTSC (national television system committ).
ee) / PAL (phase alternation line) analog
It is composed of a video decoder that converts and decodes a video signal into its digital components Y, U and V. After the signal is converted to its digital components, downscaling occurs because the input / output bus cannot support the data rate of the real-time video. Next, video codec
In the (compression / decompression) stage, the bandwidth of the input data is compressed by a lossy compression algorithm and stored in a buffer. After compression has been performed, the bus interface device sends the compressed data to system memory for storage or to a local area network (LAN) adapter for transmission. The video data is then sent from the system memory over the YUV bus to a graphics adapter or video encoder for monitoring. During playback of the compressed video data,
Data is read from system memory to a buffer by the bus interface device. This is then decompressed into field memory by the video CODEC. The decompressed YUV bus data can be displayed on a display or NTSC monitor. Since the data has been downscaled and compressed, it must be upscaled on a YUV bus. This is because the decompressed image is one-fourth or one-eighth of the maximum size and needs to be upscaled or zoomed for display.

The largest image frame has a square pixel resolution of 640.times.480 for NTSC signals and 768.times. For PAL or SECAM (sequential color avec memoire or sequential color with memory) signals.
576. Many multimedia systems use the JPEG format, which is an ISO (International Organization for Standardization) standard for still image compression, as a video CODEC for compressing the bandwidth of input video data. The JPEG engine is also used for decompression during playback of compressed video data. This adapter is supported by many multimedia adapters. Specifically, IBM's UMS / 6000 (Ultimedia
Services / 6000). J
Compressing full-size images with PEG maintains good image quality but increases the data rate of digital image processing. For example, it is difficult to handle full-time data rates on a conventional I / O bus or LAN. Therefore, it is necessary to reduce the data rate on the source side. Maximum resolution square pixel video image is converted to CIF (common int
ermediate format) size (320 × 24 in NTSC)
0, PAL or SECAM to 384 x 288) and compressing even or odd fields only reduces the data rate to 150K bytes per second. Also U
MS / 6000 processes CIF size images seamlessly, and MPEG / Px64 and other video compression standards use CIF
You need to enter a size. During playback, the decompressed CIF size image can be upscaled to the maximum screen resolution to enhance visibility.

[0007] To provide upscaling and downscaling capabilities within the aforementioned multimedia platform, the scalar chip is typically a video chip.
It is added after the decoding circuit. Typically, scalar chips are expensive and even more expensive, depending on the flexibility and their capabilities that imply continuous scaling.
Unfortunately, data processing systems that perform full-size video image processing are expensive, in part because of the additional cost of scalar chips.

Accordingly, compression and decompression of the video image processing unit of the data processing system without the need for additional circuitry such as scaling chips, buffers, and other associated interface logic required to add the scaling chip. There is a need for a system that allows video downscaling and upscaling during playback.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to implement video signal processing.

It is another object of the present invention to provide a digital signal of video and graphics information.

Another object of the present invention is to provide real-time scaling of video or graphics information that can be displayed and stored in a multimedia enabled data processing system.

[0012]

SUMMARY OF THE INVENTION The foregoing objects are attained as described herein. In accordance with the present invention, a video adapter for use in a multimedia computer data processing system is disclosed. Video adapters can change video size in real time during compression and decompression playback within multimedia computer data processing systems. The video adapter performs this resizing by selectively clocking the individual video signal components in a predetermined sequence.

Typically, a data processing system includes a central processing unit, an input / output bus, and a system memory for transmitting or storing data from a video adapter and a memory controller for controlling a level two cache. The video adapter further includes a video signal input and a decoder connected each time to convert and decode the analog video signal to a digital signal. The digital signal includes digital components Y, U, and V. The video adapter also includes a video encoder connected to a video decoder;
The U and V digital components are converted and encoded into analog video signals for display on a display or video monitor that completes a multimedia data processing system. The video adapter also has a field memory and is connected to a video decoder. This allows for write and read operations and aids in the upscaling and downscaling functions performed by the video adapter.

The video adapter also includes bus enable logic connected to the video decoder, video encoder, and field memory, which are the components of the video adapter that perform video upscaling and downscaling. . Also included is a video pass-through feature that allows compression and decompression of full resolution images without the need for upscaling or downscaling. The bus enable logic includes a clock buffer connected to the U clock signal, a U or V of the digital video signal connected in parallel with the clock buffer.
A first enable gate for passing the component and a second enable gate connected to the Y component of the digital video signal. The second enable gate is enabled by the Y enable signal, and the bus enable logic is active in two consecutive clock cycles of the Y component, and during one cycle, the 1 is enabled while the two Y components are sent. U, so that one U component and one V component are sent,
It operates so that the V component alternates in the next two consecutive clock cycles. A video compression / decompression or codec element is also provided for compressing and decompressing the digital signal.

The present invention performs real-time resizing of digital video, such as upscaling and downscaling of video pixel formats. Scalers reduce the maximum resolution image to CIF size or CI
Upscale an F-size image to a full-resolution image. The adapter also has a pass-through mode, which compresses the highest resolution image during capture and decompresses it during playback. Downscaling is performed by the other party by manipulating the pixel clock before storing the video in field memory for compression and capture. Upscaling is performed by duplicating the pixels using the master timing signal from the video decoder and the synchronous reading from the field memory. This allows uniform playback on the TV monitor or computer display, while simplifying scaling and synchronization functions without the need for additional scalar chips, buffers, or interface logic.

[0016]

FIG. 1 is a block diagram of a data processing system 10 having a video capture / playback system. Data processing system 10 further includes a central processing unit (CPU) 12. CPU 12 is further connected to memory controller 14 through a system bus. The level two cache system 16 is also connected to the memory controller 14 and the CPU 12. The memory controller 14 includes a cache 16 and a system memory.
Control memory functions and operations. The memory controller connects the CPU and memory system to other components through the I / O bus 20. The bus 20 is, for example, a PCI, Micro Channel, ISA, or other bus system corresponding to the environment of a personal computer or a workstation.

The video capture / playback system includes a video adapter 22, a TV camera 24, and a TV monitor 2.
6. Image processing information is recorded through the TV camera 24 and processed by the video
It is displayed on the V monitor 26. Video information may also be obtained from system memory 18 or any other user input.
Data processing system 10 also includes a graphics adapter 28 connected to I / O bus 20 and further to display 30. An audio adapter 32, a LAN adapter 34, and a basic input / output (I / O) adapter 36 are also connected to the I / O bus 20. The adapter 36 further stores data information for a long time, and the video adapter 22. Can be connected to a disk device 38 which can temporarily store information used by the server. The basic I / O adapter 36 provides a user input and the data processing system 10
Returns a response to the user. Video adapter 22 is shown in greater detail in the block diagram of FIG.

FIG. 2 is a block diagram showing details of the video adapter 22 and the data flow between elements within the video adapter 22. Video capture / playback adapter 22 further includes a video decoder 40, NTSC
/ PAL analog video signal with its digital component Y,
It is converted to U and V, decoded, and further connected to a video encoder 42 through a YUV bus 44. The video encoder 42 converts the digital components Y, U, V into NTSC / PA
Convert to L analog video signal, encode
Display on the monitor. Video decoder 40 is also YUV
It is connected to a field memory 46 through a bus 44. The synchronization signal from video decoder 40 is also sent to the field memory through field memory write / downscale logic 46a or field memory read / upscale logic 46b. These synchronization signals are also shown in the timing diagrams of FIGS.
Therefore, it is described in detail.

The field memory 46 stores a video CODE.
Connect to C48. The CODEC 48 performs compression or decompression (decompression), whereby the bandwidth of the input data is reduced by a lossy algorithm and the data is stored in the buffer 50. The buffer 50 further includes I /
It is connected to the O bus interface module 52. Module 52 sends the compressed data to system memory 18 or LAN adapter 34 for transfer.
Video data on the YUV bus 44 can also be sent to the graphics adapter 28 for monitoring.

During playback of the video data decompressed by video adapter 22, the data is read from system memory 18 to buffer 50 by bus interface module 52. It is then decompressed by video CODEC 48 into field memory 46. YU
The decompressed data on the V bus 44 can be displayed on a display or TV monitor 26. Since the decompressed image is only 1/4 or 1/8 of the maximum size, means are provided for upscaling or zooming and displaying the decompressed image. This is YUV bus 44
Connect to

The upscaling (enlargement) means is YUV
Bus enable logic 54 connected to bus 44
Executed in The bus enable logic 54 includes a clock buffer 56 and two enable gates 58,
60 inclusive. Clock buffer 56 receives U_clk clock signal 62. The Y component gate 60 is always enabled by the Y_en signal 64, and the U or V component data is connected to the YUV bus 44 in parallel through the clock buffer 56 and the gate 58, only one of which is used for all pixel signals. The clock signal (PCLK) is enabled by the UV_en signal 66. Y-component gate 60 transfers the data from field memory 44 to an 8-bit
Received through bus 70, the output of gate 60 is returned to YUV bus 44 by an 8-bit video output 72. UV
The component data is passed through an 8-bit bus 68 to the field
Received from memory 46, the output of clock buffer 56 and gate 58 is Y-bit by 8-bit video output 74.
Return to the UV bus 44.

The video adapter 22, in this embodiment, also provides a pass-through mode in which digital video data is stored in the field memory 46 without downsizing and data is read from the field memory 46 without upscaling. I do. In this mode, compression and decompression of images at the maximum resolution is possible. The actual operation of the size change logic will be described in detail below. Video adapter 22 provides pixel clocking of the YUV data of the temporally interleaved digital video components without the need for separate scaling chips, separate buffers or associated interface logic, It is a function to change the size immediately. This allows the data processing system to downscale the maximum size video to CIF size during compression and upscale video from CIF size to maximum size during playback.

The output of the video decoder 40 is in YUV 4: 2: 2 pixel format. video·
The decoder 40 also outputs timing signals associated with the U and V components that are temporally interleaved to the buffer 50 and the tri-stateable gates 58 and 60. Eight bits of Y data and eight bits of U or V data are output for each pixel clock (PCLK). Therefore, one of the lines
The 6-bit output sequence is represented by Y0 U0, Y1 V0, Y2 as shown in the clock timing diagram of FIG.
U1, Y3 V1,. . . And so on. FIG. 3 is a clock diagram showing the timing function of the video decoder output data. In FIG. 2, the double pixel clock frequency is PCLK2
X, the pixel data modification signal is CREF.

FIG. 4 is a timing diagram showing the sampling of video data for downscaling. Before we talk about downscaling,
A brief introduction to the 6-bit pixel stream. The 16-bit pixel stream for a line is Y0 U0, Y1 V0, Y2 U1, Y3 V1,
Y4 U2, Y5 V2. . . Becomes What is important here is that the number of U and V components is YUV per line:
This is half of the Y component output in the 2: 2 format. Full size NTSC images have a square pixel resolution of 640 pixels per line and 480 lines per frame. Since the TV source is interlaced, two resolution fields are generated, each 640 pixels / line X 240 lines / field. C
IF size images have the same vertical resolution or number of lines as fields, but only half the horizontal resolution or number of pixels. Thus, the pixel sequence after downscaling with simple decimation is: Y0 U0, Y2 V0, Y4 U2, Y6 V
2,. . .

This sequence converts the Y data into a half pixel
Sampling at the clock frequency (PCLKB2)
V data can be generated by sampling with a 1/4 pixel clock frequency (PCLKB4) at the PCLK gate. Downscaled Y,
UV data is stored in the field memory. PC
YUV data sampling for downscaling at LK and gate PCLKB4 (GPCLKB4) is shown in FIG. Y sampling is performed for each GPCLKB4
Occurs in the positive phase of the clock cycle and outputs the required pixel sequence.

Now, referring to the timing chart of FIG.
A description will be given of a video upsizing of a maximum resolution from a CIF size image. The process of upscaling from CIF size to full size resolution video is more complicated than just changing the number of samples for the Y, U, V components as done in the downscaling part of the present invention. During playback, the decompressed CIF pixel size sequence in field memory for a line is as follows: Y0 U0, Y2 V0, Y4 U2, 6 V
2,. . .

Y after going through simple resizing logic
The upscaled full size video pixel sequence on the UV bus is as follows: Y0 U0, Y0 V0, Y2 U0, Y2 V0, Y
4 U2, Y4 V2, Y6 U2, Y6 V
2,. . .

Further, this output sequence is used to prevent uneven display artifacts from appearing on the display after encoding the digital components into NTSC / PAL signals.
It is also synchronized with the pixel timing of the video encoder. Uneven artifacts occur when partial fields from different frames are displayed in one frame time. As shown in FIG. 5, the synchronization logic involves the read timing of the field memory with respect to the encoder timing. Y component pixel is Y
Read from field memory to Y field memory with _FMRE ^* signal. U and V components of pixel are UV
Read to UV field memory with _FMRE ^* signal. The first read pulse of a line cannot be generated at the pixel clock timing because Y0 and U0 must be obtained before active video starts. Thus, two separate pulses (dashed box in FIG. 5) are generated just before the active video and combined with the regular FMRE ^* signal. The FMRE ^* signal is generated from the signals PCLK, PCLKB2 and PCLKB4.

Upscaling also involves Y
The bus enable logic 54 of FIG.
Is executed by As mentioned above, bus enable logic 54 includes a clock buffer 56 and two enable gates 58,60. The Y component gate 60 is always active on line 64 and the U or V component data line 68 is connected to the bus 44 through a parallel buffer 56 and gate 58. Buffer 56 and gate 58 are PCL
It becomes effective alternately every K. When signal U0 is read, it is stored in buffer 56 and is also valid for the bus through the buffer, as shown in the timing diagram of FIG. When V0 is read, buffer 56 is disabled, gate 58 is enabled and V0 is output on bus 44.

The next two consecutive pixel clocks
In the cycle, no reading is performed from the read logic 46b of the UV field memory, but the buffer 56 is enabled, the gate 58 is disabled and U0 is output again in the first cycle. Then the buffer is disabled and the gate is enabled. Therefore, V0 read from field memory read logic 46b is output again. This sequence is repeated for all lines within a line, thus producing a full resolution image.

The resizing logic also has a pass-through mode in which digital video data is output to the field memory without size reduction and data is read from the field memory without upscaling. This mode allows full resolution images to be compressed and decompressed.

In summary, the present invention discloses a method and system for performing upscaling and downscaling of a video pixel format and for changing digital video size in real time. Scalers reduce full resolution images to CIF size in various multimedia applications, or
Upscale the F size image to a full resolution image. Such applications include IBM's Ultime
Some have a dia video I / O adapter. In the pass-through mode, a full-resolution image is compressed during capture and decompressed during reproduction. Downscaling is performed by decimation by manipulating the pixel clock before storing in field memory in video compression and capture. Upscaling is performed by duplicating pixels using the master timing signal from the video decoder and the synchronous readout from the field memory. Synchronous reproduction is performed evenly on a TV monitor or computer display. The scaling and synchronization functions are easily performed without the need for costly scalar chips, separate buffer functions, or interface logic.

Scaling in the native video pixel format reduces the amount of data compared to the scaling of standard RGB pixels commonly used in modern digital video systems. Simple resizing logic can be used on all graphics adapters to upscale data as it is read from the frame buffer, and is usually
It can be integrated into a digital-to-analog conversion (DAC) chip that is designed to support V / RGB color space conversion.

In summary, the following matters are disclosed regarding the configuration of the present invention.

(1) A central processing unit, an input / output (I / O) bus connected to the central processing unit, and a video size of a digital video signal connected to the input / output bus and having a plurality of components. A video adapter for selectively clocking the individual components in a predetermined sequence. (2) The computer data processing system according to (1), wherein the video resizing includes video downscaling and upscaling during compression or decompression playback. (3) the video adapter, a video signal input, and a video decoder connected to the video signal input for converting and decoding an analog video signal received from the video signal input into the digital video signal component; ,
The computer data processing system according to the above (1), comprising: (4) The computer data processing system according to (3), further comprising a video encoder connected to the video decoder, for converting a digital video signal component into an analog video signal, encoding the encoded video signal component, and displaying the analog video signal on a video monitor. . (5) The computer data processing system according to (3), further including a field memory connected to the video decoder and performing a function of writing and reading and a function of upscaling and downscaling for a target signal. (6) The computer data processing system according to (5), wherein the video decoder and the field memory are synchronized by a synchronization signal from the video decoder. (7) A video CODEC connected to the field memory and compressing or decompressing the target signal
(5) The computer data processing system according to the above (5). (8) The computer data processing system according to (1), wherein the video adapter is connected to a video decoder and a video encoder and includes bus enable logic for performing video upscaling and video downscaling. (9) The computer data processing system according to (8), wherein the bus enable logic performs video pass-through to enable compression and decompression of full resolution images. (10) The bus enable logic includes a clock buffer connected to a U clock signal, and a first enable gate connected in parallel to the clock buffer and passing a U component or a V component of the digital video signal. Connected to the Y component of the digital video signal;
A second enable gate enabled by an enable signal, wherein the Y component is active in two consecutive clock cycles and the U, V components alternate in the next two consecutive clock cycles. , The computer data processing system according to (8). (11) The invention according to (1), wherein the plurality of digital signal components include Y, U, and V digital components. (12) A video adapter used in a multimedia computer data processing system, wherein a video signal input and an analog video signal connected to the video signal input and received from the video signal input are converted into a digital signal. A video decoder for converting and decoding, and connected to said video decoder, by selectively clocking the individual components in a predetermined sequence during compression or decompression of a video of a digital video signal having a plurality of components. And a bus enable logic for upscaling and downscaling in real time. (13) The invention according to (12), wherein the digital signal includes Y, U, and V digital components. (14) The invention according to (13), further including a video encoder connected to the video decoder, for converting a digital component into an analog video signal, encoding the video signal, and displaying the converted video signal on a video monitor. (15) The invention according to the above (12), further including a field memory connected to the video decoder and performing a function of writing and reading, and a function of upscaling and downscaling for a target signal. (16) The invention according to (15), wherein the video decoder and the field memory are synchronized by a synchronization signal from the video decoder. (17) A video CODE connected to the field memory for compressing or decompressing the target signal
The invention according to the above (15), wherein C is contained. (18) The invention according to (12), wherein the bus enable logic performs video pass-through to enable compression and decompression of a full-resolution image. (19) The bus enable logic includes a clock buffer connected to a U clock signal, and a first enable gate connected in parallel to the clock buffer and passing a U component or a V component of the digital video signal. Connected to the Y component of the digital video signal;
A second enable gate enabled by an enable signal, wherein the Y component comprises two consecutive clock signals.
Active in the first cycle, the U, V components alternate in the next two consecutive clock cycles,
2) The described invention. (20) The upscaling is performed by pixel duplication, and the master timing signal from the video decoder, the video decoder and the bus enable
The invention according to the above (12), wherein the reading is performed using the contents of synchronous reading from the field memory connected to the logic. (21) The invention according to (12), wherein the downscaling is performed by decimation with a pixel clock operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data processing system having a video capture / playback system according to a preferred embodiment of the present invention.

FIG. 2 is a block diagram illustrating details of the video adapter and data flow between elements within the video adapter.

FIG. 3 is a clock diagram of a timing function of video decoder output data.

FIG. 4 is a timing diagram illustrating sampling of video data for downscaling.

FIG. 5 is a diagram showing a field and an encoder timing.
FIG. 4 is a diagram of synchronization logic related to memory read timing.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Data processing system 12 Central processing unit (CPU) 14 Memory controller 16 Level 2 cache system 18 System memory 20 I / O bus 22 Video adapter 24 TV camera 26 TV monitor 28 Graphic adapter 30 Display 32 Audio adapter 34 LAN Adapter 36 Basic Input / Output (I / O) Adapter 38 Disk Device 40 Video Decoder 42 Video Encoder 44 YUV Bus 46 Field Memory 46a Field Memory Write / Downscale
Logic 46b Field memory read / upscale
Logic 48 Video CODEC 50 Buffer 52 I / O bus interface module 54 Bus enable logic 56 Clock buffer 58, 60 Enable gate 62 U_clk clock signal 64 Y_en signal 66 UV_en signal 68, 708 Bit bus 72, 74 8-bit video output

Continued on the front page (72) Inventor Kevin Lynn Hill, United States 78759, Sweet Shade Lane, Austin, Texas 11504 (56) References JP-A-7-191660 (JP, A) JP-A-6-195468 ( JP, A) JP-A-6-282640 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/76-5/956 G09G 5/36 510 G09G 5/36 520

Claims (16)

(57) [Claims] A central processing unit; an input / output (I / O) bus connected to the central processing unit; and an up / down scale video size of a digital video signal connected to the input / output bus. A video decoder and video encoder, a clocked buffer connected to a U clock signal, and a parallel connected to the clocked buffer to pass the U or V component of the digital video signal. A first enable gate; and a second enable gate for passing a Y component of the digital video signal, wherein the Y component is active for two successive clock cycles; And V components alternate between the next two successive clock cycles, a multimedia component. Pewter data processing system. 2. The computer data processing system according to claim 1, wherein said video resizing includes video downscaling and upscaling during compressed or decompressed playback. 3. The computer data processing system includes a video signal input for receiving an analog video signal, and wherein the video decoder converts and decodes the analog video signal into the digital video signal component. The computer data processing system according to claim 1. 4. The video encoder according to claim 1, wherein said video encoder is connected to said video decoder and converts and encodes digital video signal components into analog video signals for display on a video monitor. 4. The computer data processing system according to 3. 5. The computer data processing system according to claim 1, further comprising a field memory connected to said video decoder for performing write and read and upscaling and downscaling functions for a signal of interest. 6. The video decoder and the field decoder.
The computer data processing system according to claim 1, wherein the memory is synchronized by a synchronization signal from the video decoder. 7. A video CO connected to the field memory for compressing or decompressing the target signal.
2. The computer data processing system according to claim 1, comprising a DEC. 8. The computer data processing system according to claim 1, wherein said first and second enable gates provide video passthrough to enable compression and decompression of full resolution images. 9. A video adapter for use in a multimedia computer data processing system, comprising: a video signal input; and an analog video signal connected to the video signal input and received from the video signal input. A video decoder for converting to a video signal; a clock-driven buffer connected to a U-clock signal; and a second parallel-connected to the clock-driven buffer for passing the U or V component of the digital video signal. One enable gate and a second enable gate for passing a Y component of the digital video signal, wherein the Y component is active for two successive clock cycles; The V component alternates between the next two successive clock cycles and A video adapter wherein real-time upscaling and downscaling are performed by clocking said components during compression and decompression playback using said first and second enable gates. 10. An analog signal connected to said video decoder for displaying digital components on a video monitor.
10. The video adapter of claim 9, comprising a video encoder that converts and encodes to a video signal. 11. The video adapter of claim 9, further comprising a field memory connected to said video decoder for performing write and read and upscaling and downscaling functions on a signal of interest. 12. The video adapter according to claim 9, wherein said video decoder and said field memory are synchronized by a synchronization signal from said video decoder. 13. A video C connected to said field memory for compressing or decompressing said target signal.
10. The video adapter of claim 9, including an ODEC. 14. The clock-driven buffer according to claim 1, wherein:
10. The video adapter of claim 9, wherein the enable gate and the second enable gate provide video passthrough to enable compression and decompression of full resolution images. 15. The upscaling includes: a master timing signal from the video decoder, synchronous reading from a field memory connected to the video decoder, the clock-driven buffer, and the first enable. 10. The video adapter of claim 9, wherein the video adapter is performed by pixel replication using a gate and the second enable gate. 16. The method according to claim 16, wherein said downscaling is performed on a pixel-by-pixel basis.
10. The video adapter of claim 9, wherein the video adapter is performed by decimation with clock operations.