JPH04260950A - Cache memory device - Google Patents

Abstract

PURPOSE:To speed up processing when writing operation is continued at the time of hitting the writing operation. CONSTITUTION:The cache memory device is provided with a 1st and 2nd address registers 101, 102 for a tag memory and a data memory, a tag entry decoder 103, and a data entry decoder 105 and constituted so that the lower 6 bits of the register 101 are transferred to the register 102 through a transfer route 112 at the time of writing operation and tag comparison and the writing of preceding compared result data are processed in parallel by the same clock.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device built into a microprocessor, and more particularly to a technique for increasing the speed of data writing to a data cache memory.

0002

[Background Art] A cache memory built into a microprocessor stores frequently used data and instructions in the main memory, so that the CPU can access these data and instructions at high speed. This is what I did. The cache memory built into the microprocessor includes data cache memory (hereinafter abbreviated as data cache).
and instruction cache memory (hereinafter abbreviated as instruction cache)
There is. The cache memory is composed of a tag memory section that stores addresses in the main memory where data and instructions exist as tag information, and a data memory that stores data and instructions in correspondence with the tag information. Instruction cache operations include reading tags, comparing tags, and determining hit/miss.
In the case of a hit, the instruction corresponding to the tag is read, and in the case of a miss, the instruction is re-registered from the main memory. Data cache operations include reading tags, comparing tags, and reversing hit/miss; in the case of a hit, the data corresponding to the tag is read (read) or written (write); in the case of a miss, data is written from the main memory. Consists of re-registration.

The configuration of a cache memory device built into a conventional microprocessor will be explained with reference to the block diagram shown in FIG. In the figure, 101 is an address register, and when a new address is input via an address bus (not shown), the address register 101 temporarily stores it. Further, the number of rows selected in the lower part of the address is called the number of entries. The lower part of this address is input to an entry decoder 103 provided in common to the data memory 106 and the tag memory 104. The entry decoder 103 selects an entry in the tag memory 104 and the data memory 106, and selects an entry by decoding the lower part of the address. Further, the upper part of the address is given to the tag memory 104 or the comparator 107. Comparator 107
is also provided with tag information in the tag memory 104 of the selected entry, which is compared with the upper part of the input address. This comparison result is given to the gate 108, and the gate 108 receives the data memory 2 according to the comparison result.
It is determined whether to output the information output from the selected entry to the arithmetic unit (not shown) as valid data or to write data from the arithmetic unit to the selected data memory 106.

The conventional cache memory device configured as described above operates as shown below. An entry decoder 103 decodes the lower part of the address in synchronization with a certain clock, and selects an entry in the tag memory 104. Tag information is read from the selected tag memory 104 entry during the clock period. The read tag information is compared with the upper part of the input address by the comparator 107, and if the values match, the cache is said to have hit, and a hit signal is generated. If the values do not match, the cache is said to have missed it. Especially in the case of a write operation, a cache hit is called a write hit, and a cache miss is called a write miss.

FIG. 9 is a timing chart of a write operation of a conventional data cache. When the data cache performs a write operation, if the tag comparison results in a cache hit (write hit), the data is written to the data memory 106 of the entry corresponding to the tag information. That is, tags are read and compared in synchronization with a certain clock, a hit signal is generated, and data is written to the data memory 106 in the row corresponding to the hit tag information via the gate 108 at the next clock. I do. In the example of FIG. 8, for example, tag information is read from the third row (third entry) of the tag memory 104 in a certain clock cycle, and as a result of comparing it with the upper part of the address by the comparator 107, the hit signal becomes active. Become. Then, in the next clock cycle, the data memory 104
When data is written to the third line (third entry) and tag information is read from the tag memory 104, data cannot be written to the data memory 106. Also, when writing data to the data memory 106, the tag memory 10
It was not possible to read tag information from 4.

[0006]

[Problems to be Solved by the Invention] As described above, in the write operation of the conventional built-in cache memory, as shown in FIG. It took one clock and two clocks in total to rewrite the data. Therefore, when write hits occur continuously, two clocks are always required, resulting in a problem that data access becomes slow. Generally, a cache memory is used to transfer data between an external storage device and a microprocessor at high speed. When the cache memory is external, data transfer from the cache memory to the microprocessor requires more cycles than the microprocessor's internal processing time due to delays between these devices. Therefore, even if write operations are continuous, the cache memory delay does not affect the overall functionality much, but if the cache memory is built into a microprocessor,
Since the delay required for data transfer from the cache memory to the microprocessor is small, the delay required for internal processing of the cache memory reduces the calculation speed of the microprocessor, resulting in a reduction in overall functionality.

The present invention has been developed in view of the above circumstances, and by providing separate entry decoders for tags and data, and overlapping tag comparison and data writing, it is possible to prevent consecutive write hits. It is an object of the present invention to provide a cache memory device that can perform write operations continuously and speed up write operations to a cache memory.

[0008]

[Means for Solving the Problems] A cache memory device according to the present invention includes a first entry decoder and a first address register dedicated to a tag memory and a data memory, respectively, and a second entry decoder and a second address register dedicated to a tag memory and a data memory, respectively. In addition to providing an address register, a path is also provided for transferring part of the storage address of the main memory taken into the first address register to the second address register.

[0009]

[Operation] In the present invention, during a read operation, the storage address is taken into the first address register and the second address register at the same time, the same entry is selected by the first and second entry decoders, and the comparison result is If there is a match, the information in the data memory of the selected entry is read out. On the other hand, during a write operation, the storage address is loaded only into the first address register, and a comparison is performed by a comparator. If the comparison results match, a part of the storage address loaded into the first address register is transferred to the second address register. When the next storage address is transferred to the address register, the first address register outputs a part of the next storage address to the first entry decoder, and at the same time, the second address register outputs a part of the next storage address to the first entry decoder. A part of the entry decoder is output to the second entry decoder. Therefore, different entries are selected in the tag memory and the data memory, and data writing and tag information comparison can be performed in the same cycle, thereby speeding up the write operation.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments thereof. FIG. 1 is a block diagram showing the configuration of a microprocessor according to the present invention. This microprocessor is roughly divided into 10 blocks, which are instruction fetch unit (IFU) 47, instruction decode unit (DU)
40, 1st micro ROM section (IROM) 43
, second micro ROM unit (FROM) 44 , operand address calculation unit (AU) 41 , PC calculation unit (
PCU) 42, integer operation unit (IU) 45, floating point operation unit (FPU) 46, operand access unit (O
AU) 48, Bus interface unit (BIU) 5
It is 0. The bus interface section 50 controls data input/output to/from external memory using a 32-bit command bus, a 64-bit data bus, and a 32-bit address bus. Each block will be explained in more detail below.

(1) Instruction fetch unit The instruction fetch unit 47 includes an address conversion mechanism for instruction addresses, an 8K byte built-in instruction cache, and a 64-entry instruction TLB for converting logical addresses into physical addresses.
, two 32-byte instruction queues and their control units. The instruction fetch section 47 converts the logical address of the next instruction to be fetched into a physical address, fetches the instruction code from the built-in instruction cache, and outputs it to the instruction decoding section 40 . Furthermore, when the built-in instruction cache misses, the instruction fetch unit 47 outputs a physical address to the address input/output unit in the bus interface unit 50, requests access to external memory, and
The instruction code is fetched through the instruction input section in 0 and registered in the built-in instruction cache.

[0012] The instruction cache is 16 bytes when fetching the instruction code from the instruction bus and when fetching the instruction code by operating the data bus with a width of 32 bits.
It operates with a configuration of e x 128 entries x 4 ways, and when operating the data bus with a 64-bit width to fetch instruction codes, it requires 32 bytes x 128 entries x 2 w.
It works with the ay configuration. The TLB always has a 16 entry x 4 way configuration regardless of the operating bus mode. One of the two instruction queues prefetches and queues the instruction code following the conditional branch instruction, and the other prefetches and queues the instruction code of the branch destination. The logical address of the instruction to be fetched is calculated by a dedicated counter. When a jump occurs,
The logical address of a new instruction is transferred from the operand address calculation unit 41, the PC calculation unit 42, and the integer calculation unit 45 via the JA bus. The internal control circuit of the instruction fetch unit 47 also performs address conversion by paging and update of the instruction TLB when the instruction TLB misses. Also, while this microprocessor is performing a bus snoop operation, it monitors the address on the address bus through the address input/output section, and invalidates the corresponding entry in the built-in instruction cache if necessary.

(2) Instruction decoding section The instruction decoding section 40 basically decodes instruction codes in units of 16 bits (halfwords). This block receives the first decoder that decodes the first half of the opcode included in the first halfword, the addressing mode decoder that operates simultaneously with the first decoder to decode information specifying the addressing mode, and the decoding results of the first decoder. The second part decodes the second half of the operation code and outputs the entry address of the micro ROM.
Contains a decoder. The instruction decoding unit 40 includes a sub-decoder that decodes an instruction following the instruction decoded by the main decoder consisting of a first decoder, an addressing mode decoder, and a second decoder in parallel with the main decoder. Instructions that can be decoded by the sub-decoder are inter-register operation instructions that have no data dependency with the instructions decoded by the main decoder, and instructions decoded by the sub-decoder are executed under microprogram control. executed under hardwired control at the same time. This microprocessor employs a superscalar architecture in which hardware automatically selects instructions that can be decoded by the sub-decoder.

The instruction decoding unit 40 also includes a branch prediction mechanism for predicting branches of conditional branch instructions, and a scoreboarding register for checking data hazards during operand address calculation and interlocking the pipeline. In the instruction decoding section 40, an instruction fetch section 47
0 to 8 bytes are decoded per clock. Of the decoding results, integer operation section 4
Information regarding the calculation in 5 is stored in the IROM section 43, information regarding the calculation in the floating point calculation section 46 is stored in the FROM section 44, information related to the operand address calculation is stored in the operand address calculation section 41, and information related to the PC calculation is stored in the operand address calculation section 41. PC
Each is output to the calculation unit 42.

(3) IROM section The IROM section 43 includes a micro ROM storing various micro program routines for controlling the integer calculation section 45, a micro sequencer, a micro instruction decoder, and the like. Microinstructions are read from the microROM once per clock, and one microinstruction reads one
Since operations are performed between two registers, instructions such as transfer, comparison, addition/subtraction, and logical operations are completed in one clock. In addition to sequence processing for executing microprograms related to instruction execution, the microsequencer also accepts exceptions, interrupts, and traps (these three are collectively called EIT), and performs sequence processing for microprograms corresponding to each EIT. . The IROM unit 43 also receives external interrupts that do not depend on instruction codes and microprogram branch conditions based on the results of integer arithmetic operations.

(4) FROM section The FROM section 44 includes a micro ROM storing various micro program routines for controlling the floating point arithmetic section 46, a micro sequencer, a micro instruction decoder, and the like. Micro instructions are micro ROM
is read out once per clock, and one floating-point operation can be completed with a minimum of two microinstructions. In addition to sequence processing indicated by the microprogram, the microsequencer also handles exceptions related to floating point operations, and requests exception handling to the IROM unit 43 when an unmasked floating point exception is detected. When a floating point arithmetic instruction is decoded by the microinstruction decoder, the decoding result is simultaneously output to the IROM section 43 and the FROM section 44, and for the first microstep, both the integer arithmetic section 45 and the floating point arithmetic section 46 Operate. However, the micro sequencer of the FROM section 44 and the IROM
Since they are controlled independently of the microsequencer of the section 43, the integer operation section 45 and the floating point operation section 46 operate independently from the second step onwards.

(5) Operand Address Calculation Unit The operand address calculation unit 41 is hard-wired controlled by control information relating to operand address calculation output from the addressing mode decoder of the instruction decoding unit 40. In this block, address calculations for operands other than memory access for memory indirect addressing and jump destination addresses for jump instructions are performed. The indirect address fetched during memory indirect addressing is transferred from the operand access section 48 to the operand address calculation section 41 via the AG bus. The calculation result of the operand address is output to the integer calculation section 45. In advance jump processing at the end of operand address calculation, the calculation result of the jump destination address is output to the instruction fetch section 47 and the PC calculation section 42 through the JA bus. The immediate operand is output to an integer arithmetic unit 45 and a floating point arithmetic unit 46. Upper 32 of 64-bit immediate value
Bits are transferred on the AG bus. The values of general-purpose registers and program counters necessary for address calculation are stored in the integer calculation section 4.
5 and the PC calculation unit 42 via the IX bus.

(6) PC calculation unit The PC calculation unit 42 calculates the P output from the instruction decoding unit 40.
Hardwired control with information related to C calculation,
Calculate the PC value of the instruction. Microprocessor instructions are variable length instructions, and the length of the instruction cannot be determined until the instruction is decoded. The PC calculating unit 42 calculates the instruction length output from the instruction decoding unit 40 by calculating the PC of the instruction being decoded.
Calculate the PC value of the next instruction by adding to the value. The calculation results of the PC calculation unit 42 are output as the PC values of each instruction together with the decoding results of the instructions, and flow through the pipeline at the same time as the instructions. In the preceding branch processing at the instruction decode stage, the address of the preceding branch destination instruction is calculated. Jump instructions to absolute addresses are also processed at the instruction decode stage. In addition, the PC calculation unit 42 has a PC stack that holds a copy of the return destination PC value from the subroutine that is pushed onto the stack when a jump instruction to the subroutine is executed. By reading the destination PC, destination return processing is performed to generate the address of the return destination instruction. The jump destination address due to the preceding branch and preceding return is transferred to the instruction fetch via the JA bus.

(7) Integer operation section The integer operation section 45 is controlled by a microprogram stored in the micro ROM of the IROM section, and the operations necessary to realize the functions of each integer operation instruction are stored inside the integer operation section 45. It is executed using a certain register file and arithmetic unit. The register file contains general-purpose registers and work registers. The computing units include the main ALU, main barrel shifter, priority encoder, etc., and the sub ALU.
and a sub-processing unit including a sub-shifter, and the main processing unit and sub-processing unit are each connected to a register file by three buses. The sub-operation unit not only operates on instructions decoded by the sub-decoder of the instruction decoding unit 40, but also can be controlled by a microprogram. With this function, the integer arithmetic unit 45 uses 2
It executes instructions at high speed by simultaneously performing two operations and transferring data between two registers.

When the operand to be operated on by the instruction is an address or an immediate value, the immediate value or the calculated address is input from the operand address calculation section 41. Furthermore, when the operand to be operated on by the instruction is data on memory, the address calculated by the operand address calculation unit 41 is output to the operand access unit 48 through the AA bus, and the operand fetched from the built-in data cache or external is input to the integer calculation unit 45 through the DD bus. When it is necessary to read the built-in data cache or external memory during an operation, the address is output to the operand access unit 48 through the AA bus according to instructions from the microprogram, and the target data is fetched from the DD bus. When it is necessary to store the calculation result in the built-in data cache of the present invention or an external memory, the address and data are outputted to the operand access unit 48 via the AA bus and the DD bus according to instructions from the microprogram. At this time, in the PC calculation unit 42, the PC value of the instruction that performed the store operation is held in the latch corresponding to the store buffer. When the integer operation section 45 obtains a new instruction address by processing an external interrupt or exception, it outputs this to the instruction fetch section 47 and the PC calculation section 42 through the JA bus.

(8) Floating point arithmetic unit The floating point arithmetic unit 46 is controlled by a microprogram stored in the micro ROM of the FROM unit 44, and performs floating point arithmetic operations necessary to realize the functions of each floating point arithmetic instruction. It is executed using the register file and arithmetic unit inside the unit. The floating point arithmetic unit 46 includes a multiplier, which executes floating point multiplication at high speed and also performs multiplication for integer multiplication instructions. The floating point arithmetic unit 46 includes a floating point arithmetic mode control register (FMC) that sets the rounding method for floating point arithmetic operations and the permission to detect floating point arithmetic exceptions.
and a floating point arithmetic status word (FSW) consisting of flags for floating point arithmetic results and status bits indicating the occurrence status of floating point exceptions. When the operand to be operated on by the instruction is an immediate value, the immediate value output from the operand address calculation unit 41 is transferred via the S1 bus (lower 32 bits) and the AG bus (upper 32 bits). In addition, if the operand to be operated on by the instruction is data on memory, the operand address calculation unit 4
The address calculated in step 1 is output to the operand access unit 48 via the AA bus, and the operand fetched from the built-in data cache or external memory is once transferred from the DD bus to the integer operation unit 45, and then transferred via the S1 bus and the S2 bus. It is input to the floating point arithmetic unit 46.

When it is necessary to store the operand in the built-in data cache or external memory, the data is transferred once to the integer calculation section 45 via the D1 bus and D3 bus according to instructions from the microprogram, and then transferred from the integer calculation section 45 to the DD bus. The data is output to the operand access unit 48 through the In the store operation, the floating point arithmetic unit 46 and the integer arithmetic unit 45 work together, and the integer arithmetic unit 45 outputs an address to the operand access unit 48 through the AA bus, and the floating point arithmetic unit 46 outputs data. be done.

(9) Operand Access Unit The operand access unit 48 includes an address translation mechanism for operand addresses, an 8 KB built-in data cache of the present invention, 6
There is a 4-entry data TLB, a 2-entry operand prefetch queue, a 3-entry store buffer, and a control unit for these. The built-in data cache has 3 configurations.
2 bytes x 64 entries x 4 ways, TLB
The configuration is 16 entries x 4 ways. In the data loading operation, the logical address of the data to be loaded outputted from the operand address calculation unit 41 and the integer calculation unit 45 is converted into a physical address, the data is fetched from the built-in data cache, and the integer calculation unit 45 and floating point calculation are performed. It outputs to section 46. If the built-in data cache misses, it outputs the physical address to the address input/output section in the bus interface section 50, requests data access to the outside, and registers the data input through the data input/output section in the built-in data cache. do.

In the data store operation, the logical address of the data to be stored outputted from the integer calculation unit 45 is converted into a physical address, and the data outputted from the integer calculation unit 45 and the floating point calculation unit 46 is stored in the built-in data cache. At the same time as storing, the physical address is output to the address input/output section, and the data is outputted from the data input/output section to the outside via the store buffer. The store buffer manages data to be stored, its address, and the address of the instruction that performed the store operation as a set. Store operations in the store buffer are managed on a first-in, first-out basis. The internal control circuit of the operand access unit 48 also performs address conversion by paging and updating of the data TLB when the data TLB misses. A check is also made to see if the memory access address falls within the memory mapped I/O area. Furthermore, while the microprocessor is performing a bus snoop operation, it invalidates the entry in the built-in data cache that is hit by the physical address input through the bus interface section 50.

(10) Bus Interface Section The bus interface section 50 consists of an address input/output section, a command input section, and a data input/output section. The address input/output section outputs the addresses output from the instruction fetch section 47 and the operand access section 48 to the outside of the microprocessor. Address output is performed according to the bus protocol defined by the microprocessor. Control of the bus protocol is performed by an external bus control circuit located within the address input/output section. The external bus control circuit also accepts bus access exceptions and external interrupts. In addition, an external device other than this microprocessor is the bus master, and when the microprocessor is performing bus snooping, it captures the address output on the address bus when the external device executes a data write, and takes in the address output to the address bus when the external device executes data write. The data is transferred to the operand access unit 48. Address capture operation occurs when the DS signal is asserted during the data write cycle (clock asynchronous, edge sense) and when the MREQ
This is done when the MS signal is asserted while the signal is asserted (clock synchronous level sensing).

The instruction input section inputs instruction codes to the microprocessor every 32 bits (or 64 bits) from an instruction bus (or data bus). Instruction cache access methods include a standard bus cycle in which a 32-bit (or 64-bit) instruction code is fetched only once per address, and a standard bus cycle in which a 32-bit (or 64-bit) instruction code is fetched only once per address;
There is a block transfer bus cycle in which a 32-bit (or 64-bit) instruction code is fetched consecutively. The instruction input unit transfers the fetched instruction code to the instruction fetch unit 47. The data input/output unit takes in data from the data bus during an operand load operation and transfers it to the operand access unit 48. During the operand store operation, the operand output from the operand access unit 48 is output to the data bus. Access methods for external memory such as data cache include standard bus cycles that access 64-bit data for one address, and four consecutive 64-bit or 32-bit accesses for one address.
There is a block transfer bus cycle for accessing bit data, and in both cases, the data input/output section inputs/outputs data exchanged between the operand access section 48 and the external memory.

Next, the pipeline processing mechanism of the microprocessor will be explained. This microprocessor operates at high performance by pipeline processing of instructions through various types of buffer storage and efficient access to memory using an instruction bus and a data bus. The contents will be explained in detail below. - Pipeline mechanism Figure 2 shows the pipeline diagram of the microprocessor. Instruction fetch stage (IF
21. Decode stage (D stage) to decode instructions 22. Operand address calculation stage (A stage) to calculate operand addresses
23. Micro ROM access (especially called R stage) 24, operand prefetch (especially called OF stage) 25, operand fetch stage (F stage) 26, execution stage (which executes instructions)
Pipeline processing is performed in a six-stage configuration including a store stage (E stage) 27 and a store stage (S stage) 28 that stores memory operands. The S stage 28 has three stages of store buffers.

Each stage operates independently of the other stages, and in theory the six stages operate completely independently. S
Each stage other than stage 28 can perform one process in at least one clock. The S stage 28 can perform one operand store process in a minimum of two clocks. Therefore, if there is no memory operand store processing, ideally pipeline processing proceeds one after another every clock. This microprocessor has instructions such as memory-to-memory operations and memory indirect addressing that cannot be processed by just one basic pipeline process, but the microprocessor uses a pipeline process that is as balanced as possible for these processes as well. is designed to be able to do so. For instructions with multiple memory operands, the instructions are decomposed into multiple pipeline processing units (step codes) at the decoding stage based on the number of memory operands, and pipeline processing is performed.

The information passed from the IF stage 21 to the D stage 22 is the instruction code itself. D stage 2
There are three types of information passed from 2 to the A stage 23: information related to the operation specified by the instruction (hereinafter referred to as code), information related to operand address calculation (hereinafter referred to as A code), and the program counter value of the instruction being processed. It is. The information passed from the A stage 23 to the F stage 26 includes an R code that includes the entry address of the microprogram routine and parameters to the microprogram, an F code that includes operand addresses and access method instruction information, and information about the instruction being processed. There are four values: a program counter value and a stack pointer value. The information passed from the F stage 26 to the E stage 27 consists of four types: an E code that includes arithmetic control information and literals, an S code that includes operands and operand addresses, and the program counter value and stack pointer value of the instruction being processed. be. The S code consists of an address and data. The information passed from the E stage 27 to the S stage 28 is the W code, which is the operation result to be stored, and the program counter value of the instruction that outputs the operation result. The W code consists of an address and data.

An EIT detected at a stage before E stage 27 does not start EIT processing until its code reaches E stage 27. Only the instructions being processed in the E stage 27 are in the execution stage, and the instructions being processed in the IF stages 21 to F stages 26 have not yet reached the execution stage. Therefore, E stage 27
For EITs detected previously, the detection is simply recorded in the step code and transmitted to the next stage. EIT detected at S stage 28 is EIT detected at E stage 27
When the instruction being processed is completed or the processing of the instruction is canceled, the instruction is accepted, and the process returns to the E stage 27 to be processed.

- Processing of each pipeline stage The input/output step codes of each pipeline stage are named for convenience as shown in FIG. In addition, the step code performs processing related to the opcode, and the micro R
There are two series: a series that becomes an OM entry address or a parameter for the E stage 27, and a series that becomes an operand to be processed by the E stage 27. Furthermore, the program counter value of the instruction being processed is passed between the D stage 22 and the S stage 28, and the stack pointer value (and even the scoreboard register value) is passed between the A stage 23 and the E stage 27. .

- Instruction Fetch Stage In the instruction fetch stage (IF stage) 21, the instruction fetch section 47 operates. Figure 3 shows F stage 21 and D stage 2.
FIG. 2 is a block diagram showing the relationship between FIG. An instruction is fetched from the built-in instruction cache 71 or externally, inputted to one of the two instruction queues A72 and B73, and then executed at D stage 2.
2, the instruction code is output in units of 2 to 6 bytes. The inputs of the instruction queues 72 and 73 are input to the instruction cache 71.
If there is a hit, it is done in aligned 16-byte units, and if it is a miss, it is done in aligned 4-byte units. Instruction queue A7
2 and B73 exist in order to fetch both the instruction following the conditional branch instruction and the branch destination instruction. When fetching an instruction from the outside in standard access mode, a minimum of two clocks are required for every four aligned bytes. Burst mode requires a minimum of 5 clocks per 16 bytes. When the instruction cache 71 hits, an instruction is fetched in one clock for every 16 aligned bytes. The output unit of the instruction queues A72 and B73 is variable every two bytes, and a maximum of six bytes can be output during one clock. Conversion of logical addresses of instructions to physical addresses, control of the instruction cache 71 and instruction TLB, management of prefetch destination instruction addresses, and instruction queues A72 and B73
This control is also performed by the IF stage 21.

- Instruction decode stage The instruction decode stage (D stage) 22 decodes the instruction code input from the IF stage 21. Decoding is performed by the FHW decoder and NFHW decoder of the instruction decoding section 40,
The instruction decoder 75 such as the addressing mode decoder is used to perform the decoding once per clock, and one decoding process consumes 0 to 6 bytes of instruction code (step code including the return address of the return subroutine instruction). No instruction code is consumed during output processing, etc.) In one decoding, the A code, which is address calculation information, and D, which is the intermediate decoding result of the operation code, are sent to the A stage 23.
Output the code. At the D stage 22, the PC of each instruction
It also controls the calculation unit 42 and outputs instruction codes from the instruction queues 72 and 73. In the D stage 22, advance jump processing (D stage advance jump) is performed in response to a jump command. Except for conditional branch instructions, no D code or A code is output for a jump instruction that performs a preceding jump, and instruction processing ends at the D stage 22.

When a conditional branch instruction is decoded, the D stage 22 instructs the IF stage 21 to fetch instructions from both the branch destination and non-branch destination. The instruction to be decoded following the conditional branch instruction is determined according to the result of branch prediction. In other words, after a conditional branch instruction that is predicted to branch, the instruction output from the instruction queue A72 is decoded to fetch the branch destination instruction, and for a conditional instruction predicted not to branch, a non-branch destination instruction is fetched. The instruction code output from the instruction queue B73 is decoded.

Operand Address Calculation Stage The operand address calculation stage (A stage) 23 is roughly divided into two processes. One is the instruction decoding section 40
This process uses the decoder 75 of the operand address calculation unit 4 to perform subsequent decoding of the operation code.
This is a process in which the operand address is calculated in step 1. The subsequent decoding process of the operation code takes the D code as input and outputs the R code, which includes register and memory write reservations, the entry address of the microprogram routine, parameters for the microprogram, and the like. The purpose of register and memory write reservation is to prevent the contents of the register or memory referenced in address calculation from being rewritten by a preceding instruction on the pipeline, resulting in incorrect address calculation.

Operand address calculation processing is performed by inputting the A code, and according to the A code, the operand address calculation unit 41
Calculate the address of the operand with , and send the calculation result to F
Output as code. In addition, for a jump instruction, a jump destination address is calculated. A write reservation is checked when reading a register during address calculation, and if it is indicated that there is a reservation because the preceding instruction has not finished writing to the register or memory, the preceding instruction executes the write processing at the E stage 27. Wait until it finishes. In the A stage 23, advance jump processing is performed for jump instructions that did not perform a advance jump in the D stage 22 (
A stage advance jump). An A stage advance jump is performed for register indirect jumps and memory indirect jumps. No R code or F code is output for the instruction that performed the A stage advance jump, and the processing of the instruction ends at the A stage 23.

Micro ROM Access Stage The operand fetch stage (F stage) 26 is also roughly divided into two processes. One is access processing of the micro ROM, especially called the R stage 24. The other is operand prefetch processing, especially called OF stage 25. The R stage 24 and the OF stage 25 do not necessarily operate at the same time, and their operation timings differ depending on data cache misses and hits, data TLB misses and hits, and the like. The micro ROM access process, which is the process of the R stage 24, is the following E for the R code.
These are micro ROM access and micro instruction decoding processing to create an E code, which is an execution control code used for execution in stage 27.

When processing for one R code is decomposed into two or more microprogram steps, IRO
The M section 43 and FROM section 44 may be used in the E stage 27, and the next R code may be waiting for access to the micro ROM. The micro ROM for the R code is accessed in the micro ROM at the E stage 27.
This is when no access is made. In this microprocessor, many integer arithmetic instructions are executed in one microprogram step, and many floating point arithmetic instructions are executed in two microprogram steps, so in reality, microROM accesses to the R code are often performed one after another. . In the processing of the R stage 24, only the IROM section 43 is accessed for an instruction that does not use the floating point arithmetic section 46, and the FROM section 44 is not accessed. For instructions that use the floating point arithmetic unit 46 (floating point arithmetic instructions, integer multiplication/division instructions, etc.), the IROM unit 4
3 and FROM section 44 are both accessed.

- Operand Fetch Stage The operand fetch stage (OF stage) 25 performs operand prefetch processing of the above two processes performed in the F stage 26. Operand fetch stage 25
Now, convert the logical address of the F code to a physical address using the data TLB, access the built-in data cache with that physical address, fetch the operand, and combine that operand with the logical address transferred as the F code. Output as S code. One F code may cross an 8-byte boundary, but specifies an operand fetch of 8 bytes or less. The F code also includes a specification of whether or not to access the operand, and when transferring the operand address itself or immediate value calculated in the A stage 23 to the E stage 27, operand prefetch is not performed and the contents of the F code are is transferred as an S code.

- Execution stage The execution stage (E stage) 27 operates with E code and S code as input. This E stage 27 is a stage for executing instructions, and all processes performed in stages before the F stage 26 are preprocessing for the E stage 27. When a jump is executed or EIT processing is started at E stage 27, all processing from IF stage 21 to F stage 27 is invalidated. The E stage 27 is controlled by the microprogram and executes instructions by executing a series of microinstructions starting from the entry address of the microprogram routine indicated in the R code.

The E code includes a code for controlling the integer calculation section 45 (especially called the EI code) and a code for controlling the floating point calculation section 46 (especially called the EF code). can be output independently, and at this time, in the E stage 27, the integer arithmetic unit 45 and the floating point arithmetic unit 46 operate in parallel. For example, when the floating point arithmetic unit 46 executes a floating point arithmetic instruction that does not have a memory operand, the floating point arithmetic unit 46 starts from the operation of the second microstep to the integer arithmetic unit 4.
5 and operates independently and in parallel with the integer calculation section 45. Note that for all instructions including floating point arithmetic instructions, the integer arithmetic unit 45 executes at least one microinstruction (even for floating point arithmetic instructions, the integer arithmetic unit 45 always operates during the first clock). In both integer arithmetic and floating point arithmetic, micro ROM reading and microinstruction execution are performed in a pipelined manner. Therefore, when a branch occurs in a microprogram, one microstep becomes available. In the E stage 27, the write reservation for registers and memory made in the A stage 23 is canceled after the operand is written.

[0042] Various interrupts are processed at E stage 2 at the end of instructions.
7, and the necessary processing is executed by the microprogram. Processing of other various EITs is also
This is done in stage 27 by a microprogram. When it is necessary to store the result of the operation in the memory, the E stage 27 outputs the W code and the program counter value of the instruction to perform the store processing to the S stage 28. Operands are stored in memory in the order logically specified by the program, regardless of the results of integer operations or floating-point operations. When storing data from the floating point arithmetic unit 46 to the memory, the integer arithmetic unit 45 continues until the instruction is completed (until moving to the store stage).
Do not execute all subsequent commands.

Operand Store Stage The operand store stage (S stage) 28 converts the logical address of the W code into a physical address using the data TLB, and stores the data of the W code in the built-in data cache at that address. At the same time, the W code and program counter value are input to the store buffer, and the W code data is stored in an external memory using the physical address output from the data TLB. The operation of the operand store stage 28 is performed by the operand access unit 48,
It also performs address conversion processing and internal data cache replacement processing when the data TLB or built-in data cache misses. If EIT is detected during operand store processing, EIT is notified to the E stage 27 while the W code and program counter value are held in the store buffer.

- State control of pipeline stages Each stage of the pipeline has an input latch and an output latch, and basically operates independently of other stages. At each stage, when the previous processing is completed, the processing result is transferred from the output latch to the input latch of the next stage, and when the input latch of the own stage has all the input signals necessary for the next processing, the next stage is started. start processing. In other words, in each stage, all input signals for the next process output from the previous stage are valid, and when the current processing result is transferred to the input latch of the subsequent stage and the output latch becomes empty, the next Start processing. All input signals must be available at the timing immediately before each stage starts operating. If the input signals are not aligned,
The stage enters a waiting state (waiting for input). When performing a transfer from the output latch to the input latch of the next stage, the input latch of the next stage must be in the free state, and even if the input latch of the next stage is not free, the pipeline stage will wait. state (waiting for output). Furthermore, if a cache or TLB misses or data interference occurs between instructions being processed in the pipeline, multiple clocks are required to process one stage, causing a delay in pipeline processing.

In addition to the basic pipeline processing shown above, this microprocessor uses a superscalar architecture that decodes and simultaneously executes two instructions in some cases, such as when two integer operation instructions between registers are consecutive. Take. In order to realize this function, this microprocessor has an instruction decoding section 40 including a main instruction decoder and a sub-instruction decoder, and an instruction execution section including a main arithmetic unit and a sub-instruction unit. The register of the integer arithmetic unit 45 and the two arithmetic units are each coupled by three buses. FIG. 4 is a block diagram showing the bus connection relationship between the registers and the arithmetic units of the integer arithmetic unit 45 of the microprocessor, and the connection relationship between the integer arithmetic unit 45 and the floating point arithmetic unit 46. S1,
Each of the S2, S3, S4, D1, D3, and IX buses is 32 bits, and the DD bus is 64 bits. Main processor 9
3 fetches data from the register file 92 via the S1 bus and the S2 bus, and writes back the operation result via the D1 bus. The sub-operation unit 91 fetches data from the register file 92 via the S3 bus and the S4 bus, and writes back the operation result via the D3 bus. The S1 bus, the S2 bus, the D1 bus, and the D3 bus are an integer operation unit 45 and a floating point operation unit (FPU) 4
When communicating data with 6, the two are connected and operate as a 64-bit bus.

Next, blocks related to the data cache of the microprocessor will be explained in detail. Figure 5 shows the operand access unit (hereinafter referred to as OAU) of the microprocessor.
48 is a block diagram showing the configuration of a computer. O
AU 48 is operand address calculation stage 25 and E
The access request is received from stage 27 and processing is started. OAU 4 from operand address calculation unit 41
There are two types of access requests sent to 8: one is an operand fetch request, and the other is an indirect reference to external memory for address generation. Also, requests for fetching and storing operands come from the E stage 27. In this case, the address is stored in the AA register 59 and sent from there to the address converter 54.

The processing sequence of the OAU 48 when receiving an access request from the address calculation stage will be described. OAU 48 is address calculation stage 23
When the OAU 48 detects an access request from the F stage 26, which is a buffer for storing addresses for operand fetching, even if the OAU 48 is in the middle of a previous process, the logical address is taken in if the F stage 26 is available. Then, after the previous process is completed, a request is accepted from the F stage 26. The logical address sent to the address translation unit 54 in this way first refers to the TLB 55, and then
If the LB is hit and a physical address is generated, the physical address is output to the data cache 56. T
If the LB 55 misses, the address translation unit 54 sends an external bus access request to the address translation table on the external memory to the bus interface unit 50.
is output to. Then, the reference to the address translation table is completed, and the generated physical address is stored in the data cache 56.
is output to. If the data cache 56 is hit,
Data read from the data cache 56 is registered in the S code register 60, which is an operand prefetch queue. The E stage 27 reads the operand from the S code register 60 and processes it. When a cache miss occurs, the bus interface unit 50
Sends a registration request for the missed block to S, inputs the data imported from the outside into the data cache 56, and
It is also input to the code register 60.

The processing sequence when a store request is sent from the E stage 27 will be explained. The E stage 27 stores store data in the DD register 58 and stores the store address in A.
Write to the A register 59 and output an access request. When the access request is accepted by OAU 48,
Similar to the processing sequence after receiving access from the address calculation stage 29, the address conversion unit 54 and the TLB 5
5. Operate the data cache 56. However, in the case of store processing, when the data cache 56 is hit, store data must be written to the data cache 56 next. When data cache 56 misses, nothing is done. In addition, the data cache 56 of the microprocessor uses a write-through method,
It is also necessary to write data to external memory. Since external bus cycles are generally slower than microprocessor machine cycles, store buffer 57 is provided to prevent internal processing from being rate-limited by external bus accesses. The store buffer 57 has three entries, so that even if the store data sent from the E stage 27 straddles a word boundary, it can be registered in the store buffer 57 in one go.

FIG. 6 is a block diagram showing the configuration of the data cache 56 of the present invention. This data cache 56
operates in a 4-way set associative system with 0 to 3 ways, and the number of entries for each way is 64. The data cache 56 includes a first address register 101 that temporarily stores an address given via the address bus;
A second address register 102 that temporarily stores part of the address (lower 6 bits), a transfer path 112 that connects the first address register 101 and the second address register 102, and a transfer path 112 that decodes the lower 6 bits of the address. A tag entry decoder 103 that selects an entry in the tag memory 104 , a data entry decoder 105 that selects an entry in the data memory 106 , a data memory 106 , and a comparator 107
and a gate 108.

As a result of processing the command, the external storage device 110
When performing the process of reading data from , the address of the data to be read is sent to the data cache 56 via the address bus 100, and the full bit width (32 bits) address is stored in the first address register 101 for the tag memory 104. , the lower 6-bit address is stored in the second address register 102 for data. and first and second address registers 101, 102
The address of the lower 6 bits is the tag entry decoder 103 for the tag memory 104 and the data memory 106.
are sent to data entry decoders 105 for 6, respectively.
A signal is generated to select one of the four entries. Next, the tag memory 104 reads the four tag information from the selected entry, and the comparator 107 compares the four tag information with the upper bits of the first address register 101 excluding the lower 6 bits. The gate 108 selects the data read from the data memory 106 corresponding to the way, and outputs the data to the arithmetic unit. When reading data from the data cache 56 in this way, the tag and data entry decoder 1
03 and 105 perform the same operation.

Next, as a result of processing the command, the external storage device 1
10 will be described. In the case of write processing, the address sent through the address bus 100 is stored in the first address register 10.
1 only. Then, similar to the reading process, the tag memory 104 is searched. If the data read from the tag memory 104 and the upper bits of the first address register 101 match, the first address register 101
The lower 6 bits of the address are transferred to the second address register 102, and if an address for write processing is sent again next time, that address is taken into the first address register 101. Next, data memory 106
Then, the transferred lower address is decoded by the data entry decoder 105 to generate a signal for selecting one of the 64 entries. Then, based on the matched way information in the tag memory 104, the corresponding data memory 1
06, data is written from the internal data bus 111. On the other hand, the tag memory 104 searches for an address corresponding to the next write process, and if they match, similarly transfers the lower 6 bits of the first address register 101 to the second address register 102.

FIG. 7 shows a timing chart of a microprocessor incorporating the data cache 56 of the present invention. FIG. 7 shows a case where the first time is a read and the second to fourth times are writes. First of all, the first time is a lead, so
The address is simultaneously written into the first address register 101 for the tag memory 104 and the second address register 102 for the data memory 106. Then, since write processing has come, the address is written only to the first address register 101 for the tag memory 104, but not to the second address register 102 for the data memory 106. If the write address matches the tag information (cache hit), the address is transferred to the second address register 102. At this time, since there is no need to write to the data memory 106 of the data cache 56 in the case of a cache miss, the address for the next read process may be taken into the first address register 101 and the second address register 102. By doing so, cache accesses can be overlapped in one clock both for successive writes in the case of cache hits and misses, and for reads subsequent to writes in the case of cache misses.

Entry decoders 103 and 10 are provided independently for the tag memory 104 and the data memory 106.
5, bus snoop operations can also be performed in parallel with cache writes. When a microprocessor is connected to other microprocessors on an external bus and accesses a common external storage device (main memory), it is necessary to maintain the consistency of each data cache 56, so that other microprocessors When updating the main memory, the blocks in the data cache 56 that have that area must be invalidated. Therefore, the first address register 101 for the tag memory 104 must have the function of inputting an address from inside, as well as monitoring and fetching an external address. In this microprocessor, even if the first address register 101 and the tag entry decoder 103 are used for bus snooping in such a case, the second address register 102 and the data entry decoder 105 are also provided in the data memory 106. Therefore, writing to the data memory 106 can be executed simultaneously.

[0054]

As explained above, in the present invention, address registers and entry decoders are provided separately for tags and data, and a part of the storage address of the first address register is transferred to the second address during a write operation. Since data can be transferred to a register, tag comparison and data write operations can be processed in parallel (overlap), and write operations can be processed continuously. Therefore, when write operations are continuous, they can be processed in one clock, in the same time as the arithmetic processing of the microprocessor, and without delay, and the cache memory and microprocessor can operate at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a microprocessor incorporating a cache memory according to the present invention.

FIG. 2 is a block diagram of the pipeline mechanism of a microprocessor.

FIG. 3 is a block diagram showing the relationship between an F stage and a D stage.

FIG. 4 is a block diagram showing a connection relationship between an integer calculation section and a floating point calculation section.

FIG. 5 is a block diagram showing the configuration of an operand access unit.

FIG. 6 is a block diagram showing the configuration of a data cache which is a cache memory of the present invention.

FIG. 7 is a timing chart showing a data cache access operation of a microprocessor incorporating a data cache according to the present invention.

FIG. 8 is a block diagram showing the configuration of a conventional cache memory.

FIG. 9 is a timing chart of a conventional cache memory access operation.

[Explanation of symbols]

101 First address register 102 Second address register 103 Tag entry decoder 104 Tag memory 105 Data entry decoder 106 Data memory 107 Comparator 110 External storage device

Claims (1)

[Claims] 1. A data memory that stores information stored in a main memory, a tag memory that stores tag information related to a storage address of the information, and a part of the storage address that is decoded to generate an entry. an entry decoder; and a comparator that compares the tag information stored in the generated entry of the tag memory with part or all of the remaining storage address, and an instruction that accesses the main memory is connected thereto. When the cache memory device reads and writes the data memory according to the comparison result of the comparator, the cache memory device includes a first address register that takes in the storage address, and a part or part of the storage address. A second address register that captures all of the data, a path that transfers part of the storage address captured by the first address register to the second address register, and a decode part of the storage address captured by the first address register. and a second entry decoder that selects an entry of the data memory by decoding a part of the storage address taken in by the second address register. , when the instruction is an instruction to write information to the main memory, only the first address register takes in the storage address, and the first address register takes in the storage address and the first
A cache memory device characterized in that part or all of the storage address taken by the second address register is transferred to the second address register via the path.