DE1965506A1 - Device and method for program control of an electronic digital computer - Google Patents

Description

IBM Germany Internationale Büro-Maschinen Gesellschaft mbH

Bob1Ingen, '^ f .Dec-jmber I>-6> *

Applicant:. \ - ■ international business machines

Corporation, .irinonk ,. N .. ί. 10 j> ü-f

, Aktenzelohen: .. new registration

.d .rüinelderin: Docket xO y6ö 040

Device and method for program control of an electronic digital computer . -

The invention relates to a device and a method for program control of an electronic digital computer, with a main memory, an instruction unit, a arithmetic unit "and" several working memory registers.

In today's modern high-speed electronic computers Instruction processing is one of the largest Time consuming surgeries carried out by the Rachner must be carried out in order to carry out a certain task. which are usually used for both instruction retrieval and also for the retrieval of data when carrying out a loading. specific program are required. Because of the great

0098297U42 BATH ORIGINAL

rortnehritte, which in the 'modern η. Technologically, it has been possible to improve the speed of various logic circuits, including arithmetic units, so that they are much greater than the speeds of magnetic memories, which are universally used for storing large amounts of information, aie both from the Instruktionsetrom and tius dan data .us amme ns etze n-, can be used. i> jrner .- / ground working registers in the arithmetic unit i'for the transmission and storage of data read out from the memory and in the instruction unit η '"they are used to store individual instructions, because they are processed and executed.

Various cysters are currently being used to create a Perform IriKtruktionsvorausschau ·. n, v / ob for instructions P. effectively retrieved from the memory prematurely and looked up in short-term memories: while the current instructions are still being processed. Then there is some overlap

. - ._ .. ■ - "- ■". ·.,. - ". . ■ ■. . -. ■; -. '■ .- ■: _, ir .. · ..:' -.-Der Operation is sooner possible if such instruction

Foresight techniques are used / ended.

However, once the instructions are in the instruction, register are located, then it is necessary to decode them and retrieve various data segments from memory which is to be acted upon. Therefore, for example

009829 / U42

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BAD iA ^ ^{: r} ^ ^B

In a normal two-operand operation, such as multiply, the operands are called up separately from the memory, stored in working registers, the multiplication is carried out and then the result is then stored again in the memory. Therefore, before the multiplication can take place, the operands are fetched and the result stored before the next instruction can be decoded and executed. This situation is much more difficult with loop-like operations since, for example, a certain arithmetic operation has to be repeated several times. Therefore, each time the loop is to be executed, the instructions specifying the various stages of the loop must be fetched. The data specified by this must also be called up, the operation carried out and the result stored back in the memory. This sequence of operations must essentially be continued until certain loop criteria occur,

Sp. Various devices have now become known for temporarily storing the complete set of loop instructions in a high-speed working memory in order to somewhat reduce delays in returning to the head of the loop where they are re-entered. Anyway, dit require; Most have become known so far newer _J1 stones the specification of new data from the

009829/1442

BATH

1965508

Memory will be fetched every time the loop is iterated. The instructions that execute this instruction must therefore be decoded each time the loop is run through, after the memory address of the new one
Calculated data and retrieved the data for the registers
can be. The same situation arises for the restoring of the calculation results in the memory. ™ In programs with long instruction loops, these properties of the known devices are extremely disadvantageous. 3s is therefore the object of the invention to avoid these disadvantages and in particular to specify a device that is improved with regard to the effectiveness of the arithmetic operations. ν _

For a device for program control of an electronic digital computer with a main memory, a
^ Instruction unit, an arithmetic unit and

several working memory registers, the invention consists
in that a device is provided for initially loading the work memory register with data and address generating information;
data stored in the working memory registers
another part of the machine and for that. Control of the loading of this "", rfc ^ itsspulchorregiste-r in the main memory,

Q09829 / U

BATH

is provided from an address formed from the address-generating information contained in it and that finally another one of the only ones mentioned Instruction-controlled device for controlling the Storage of the result of this instruction in the working memory registers as well as in the main memory at an address that is determined by the address generating. Information is intended, is provided.

For a method for program control by means of the above Device, the invention is that in an instruction stream, before it enters a program loop, an initialized work memory content, consisting of data and address generating information to be loaded into the main memory, be specified that further within the program loop a certain working memory register whose " Transferring content to a processing part of the computer is specified, where the address generating Information in the specified working memory register. is used for the formation of a main memory address and that the main memory is also controlled at this address, and new address-generating information is generated the one currently stored in this memory food-generating information is formed and this new * address generating information specified in this

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Docket YO 968 040 ■

BAD ORIGINAL · ..

Working memory register is restored.

In this context, it is essential for the invention, that when performing loop-like operations, in particular time savings are achieved by providing a special instruction, decoding circuit and additional memory fields in very fast working memory registers for operands and results,
where specific or explicit load and store operations can be taken out of the loop and effectively injected into the instruction stream before the program enters the loop. For this purpose, a mechanism is provided in the main memory for the automatic, ibruf and automatic storage of data while the previous operation is being carried out.

A method is also essential to the invention provide by specifying the effective Address calculation from the real load and store instructions is separated, which, for example, can be coded very kqfcpakt with an arithmetic operation.

This also includes the advantage of the present invention, to accelerate the execution of instructions in a computer system, with very little additional circuitry required.

_rQ , 009829/1442
Docket ϊθ 968 040 - '

BADORFOLNAL

Another very significant benefit with the present Invention is achieved is that dia The length of certain so-called instructions is essential is reduced "

In the following the invention is based on a through drawings explained in more detail. Show it:

Pig.1 is a block diagram to illustrate the function of an instruction unit improved by the invention Data processing system? which is shown in detail in Pig.2;

2 shows a view of the mutual arrangement Figures 2A-2D;

Fi-g.2A- a combined functional and. logical ■: 2D

Vision diagram of a preferred embodiment

example of the invention ;

Fi £ .3 is a flow diagram of the workflow of the

preferred embodiment of the invention according to the Fi ^. 2 ^ -2B.

009829 / UA2

rojkv-t ":" v. "Jc ii CC
BATH

1965508-

The objects of the present invention become general realized in a data processing system that consists of a main memory, an instruction processing unit, an arithmetic unit and a number of working memory registers, and one arrangement for the initial loading of the mentioned working memory registers with data and information on address generation.

m The aforementioned Instruktiohsverarbeitungseinheit consists of an assembly which is set by a single AusfUhrungsInstruktion in activity, said instruction to another Τ controls the transfer of data that is currently stored in said Arbeitspeieherregistern "11 of the system and also causes these registers are loaded from the main memory according to the information contained in them for address generation * According to a further aspect of the invention, this

Fe single -n-executable instruction cause the Result of the instruction mentioned both in the mentioned main memory and in the main memory can be stored in a location that depends on the information for address generation ov π t> lmint becomes.

^ ■ urexi dia V rr ^ ndun; ^ der · vorli ^, v, n.'Iyn ^ rfiridun _e ". Can therefore in particular. ^ Roj.Tarainsohl ^ ifr-n v / epecially shortened weraon, whereby simultaneously the work -: jitsaufv; and- des program icrftrp and

uXUhrun ^ E time shortened.

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C -.- C

PAD

It should be noted, however, that the conventional operation of the Data processing system are not compromised by the additional circuit arrangements of the invention. So the instructions are essentially the same retrieved and processed as it did when it worked the arithmetic and logical units and the main memory the case is. The main difference is in the way the present data processing system works in that it is not necessary, explicitly the Retrieve and store instructions within a, loop to be specified once the working registers of a "pre-instruction" for the loop sequence has been loaded. The programmer must, however, provide a suitable instruction structure and cause the data sequence accessible within memory using various address index values and effective address values required by the particular circuit configuration used.

The following example illustrates the advantages of the data processing system characterized according to the invention. Suppose a system is three-address arithmetic is used, i.e. two operands · and both a result as well as an operation code is used. It is also assumed that the basic arith-. me tical instructions half a word and the loading /

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Docket YO 968 040 "

BATH

T9655Ö6

- ro -

Save instructions take up a full word * Then would create a program loop that does, for example, the following Operation would have the following form

⁰ I ¹ I.

The above operation would take three load instructions with three machine words, one store instruction with one machine word, one I-luitiplii: £ utionr- and one / -dc! 11 ζ or: f- instruction frit half a word and a "valid and branching" instruction. However, if the implicit loading and storage technique of the present;.; Rr-ind-ur _ie 5 v.-ird is used, the following procedure is applicable:

1. Use separate registers for A FiV, B [i T, c [i * \ and D [i].

2, Specify reloading of registers for

B [i] and C Γ ij in the multiply instruction

5 · Specify the reloading of the register for D 'i' ¹ and the storing of the register for A Γ ij in the addition instruction.

Nimmi; one implies that "counting and branching" is also a full word claimed, then the length of the inner

. * ■ 009829/1442

Docket YO 968 04.0. »

BATHROOM>

T9655ÖS

Loop reduced from six words to two words, ie one word; for the multiplication and addition instructions and one word for the "counting and branching" instruction which evaluates the indicator Fi "j. This saving is bought by an increase in the number of instructions necessary for the initialization of the loop and by the possible fact that that an unnecessary set of memory fetches must be made on the last iteration of the "loop. - -. _;

In the example above, a 66, -JIge savings is offered urki although this example is set, it is assumed that many loops show a similar reduction in length, but not necessarily that size. Time savings are also possible> although they are with different instruction formats, for example "a Zvieiadressformat are not so big.

The following diagram describes the format of the preferred form of instruction in order to explain the invention:

add | p.-
i ^x i k

In the obl ^^ n instruction bozjiciinet that with i kiertä field, theausi'ül'ir ^ next .. 'Gp -.- ration. The ones with I

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Cover lC 9C0 Q-tO - .. ",;.,

u marj and k

designated fields are specifications of the work sspeiöiier

register, in which the operands (i> j) and the result; ^s ' (k) to be saved are «The small fields F., F. and it indicate whether the relevant register should be reloaded or automatically stored together with the operation of the arithmetic unit. The instruction word format above, which uses the operation code add, performs the following operation: - - -

R _k

This instruction causes the operands to be ongoing in registers i and j of the main memory (see Fig * 1) appear, connected to the arithmetic unit in which an addition operation is performed * After this operation, the result will be returned to the Transfer k register. If one assumes that all F-fields' have been set to "1", the following results:. · - ..

First, the data stored in the i - work register as the first operand in the arithmetic unit. switches »At the same time one is in this register position stored address which is the storage address of the next Operands for the loop specified by the working register retrieved and this relevant /. address is controlled and displayed Operand in the i-register and the current address. the

009829 / UΛ 2

o- ^: c

BATH

brought up to date, according to an index that, from which Programmer is specified (usually increased by 1). The special way in which this address information produced in accordance with the specific details of the invention will now be described. For the moment Discussion, however, a generalized addressing technique is described since the specific... Address generation can be carried out on very different tfelse, with both address generation and diagnostic information and the like is intended. The operand stored in the j register is added in a similar way arithmetic unit and the address stored there in the working registers is used to similarly the next operand from main memory which is entered into the now effectively empty j-register will.

The arithmetic unit finally performs the operation and the instruction in the instruction register states that the result in the k register of the working memory register should be entered. While therefore the first sentence of Operand is processed in the arithmetic unit, the call takes place essentially at the same time of a following set of operands.

009 8 29 / U4 2

Docket £ 0 968 040

BATH ORIGINAL

1965SOB

Assuming that F i has been set to 1, then will The result is first transferred to the data field of the K register and, at the same time, the address stored there .; information checked, modified and used to also store the result of the operation on the address;? the is specified in the address part of the k register. After the save operation, the address part is modified (incremented) and back to the address section of the 1clke "gisfcer transferred to a. for the next result that uses this register in the relevant loop operation To open storage area.

The above description of the instruction word format for the Perform a typical run operation that includes the Concept of the present system, used, explained: the basic operating methods of the present invention * So the reloading of registers i and j becomes automatic caused by the subject matter of the invention without this being expressly ordered. In a similar rfeise is also the storage of the K register automatically by the present Instruction causes without the aforementioned transfer is called especially. However, the initial loading of the working memory registers must be carried out by suitable means Programming can be carried out, which the programmer controls himself, so that the loading of the necessary initial data and address information is enabled.

1085506

It should be mentioned that there are also more than three working registers in the . System / can be used. Two operands and one R $ attitatregister, these are registers 1, j and k

, for example to convey the teaching of the invention explained <,. Six, eight or ten such registers can also be used in the system and called by the programmer whenever necessary, bearing in mind that the registers called for an operation are initialized first must, before they are inserted into a loop or another subroutine that uses these registers to provide both the necessary initial data and the effective address and address increments.

The invention is explained below with reference to the figures. . Pig.t shows in the form of a general functional Block diagram shows the essential functional elements of the Refer to Figures 2A-2D (hereinafter referred to as Figure 2) in more detail data processing system shown * The instruction register constructed in a conventional manner receives the program instructions sequentially from the main store 1ö.

These conventional data flow paths are in the present However, the invention is not shown, as it, as well as details of the operation of the system, are sufficiently known

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are. Only the essential control circuits are shown, which are necessary for the operation of the system. A line is therefore shown extending from the instruction register 10 to the arithmetic and logic unit leads over which only the operation code, i.e. adding, Subtracting, multiplying, and the like is transmitted to the arithmetic unit 12. The instruction register contains suitable bit field areas F., F. and F, for control of the operations in the various work registers, these are those marked in the instruction with i, j and k / Register. Your particular operation actually addressed and is described in detail below ". The extended Main memory register 14 (main memory) consist of the Working memory area for the operands and results and es is the automatic pre-loading of these registers and the storage of the result register, which is the essence of the present Make up invention. As mentioned earlier, these registers are used for the data word and the Information for address generation Allocated memory space or a data field. Whereby still an increment field and an effective address field in an address correction circuit 16 can be added to each other to produce the Address for a running Öperanea call and a running one Result storage to. Form and to address for successive Form retrieval and storage custom. The main memory 1o has a conventional structure as well

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only those data paths are shown here which relate to the invention, ie the fetching of the operands from the memory and the transfer of the same to the main memory 14 and for the storage of the "results" from the main memory 14 back into the main memory 18. The control unit 20 contains in FIG primarily the dedicated control system clock, which is in the Fig.2dargestellt · and its operation is explained in detail in connection with the '. timing diagrams.

It is precisely this unit that controls the sequence of operations in the Device according to the invention and initializes the Operation of the previously explained functional units, if this is necessary «

Fig.2 shows a combination of logical and functional Block diagrams that contain the fee status of the invention. This figure will now be explained in connection with the timing diagrams. 2A shows the instruction register 10 with the associated decoding controls and gates. Furthermore, Fig.2A shows the arithmetic and logical unit 12 (ALU), _ together with collecting lines, which illustrate the flow of data between these units and the working memory 14. The address correction circuit is generally shown in Figures 2B and 2D. and primarily contains incrementer 50, holding register 52

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BADQRIGINAi _-

and the adder j56-. The main memory 18 is shown in FIG. 2D together with its conventional memory address register (MAR) and a memory data register (MDR). The main part of the control unit is shown in Fig. 2C and consists essentially of a series of monostable multivibrators (SS) for generating the clock pulses CL-1 -CL-28. The operation of the monostable multivibrators is known per se. Their structure is such that when they are excited, generate a clock pulse and generating a turn-off after shutdown after _p iner fixed time period. In the present figures, the switch-on clock pulse is shown coming from above. The switch-off pulse runs via an output that leads out of the monostable multivibrator on the right.

Pig.5 shows a flow chart in which the ρ i, j and k registers are used. The left column of the processing steps comprises the main sequence of events when the instruction is evaluated and the data is passed into the ALU and from there back into the storage register. The steps that are required when evaluating the control fields F ^, F. and F ₁ also start in this column. The evaluation of these specific control fields initiates the implicit load and store operations, which are noted in the steps in the right-hand column. The three different step sequences A, B urid-G include the

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"Pre-fetching ^{11 of} the next operand from the main peidaer (this process is controlled by the address stored in the working register), and increasing the addresses so that the next operand is implicitly called by the system in the following cycle. The three rectangles in the sequence D denote the steps which are necessary to store the register K in the main memory at the address which is in each case in the address part of the register k. The address is thus passed from the register to the memory, the result is stored, then this address is brought up to date and stored again in the working memory in the corresponding address field for register k.

Different rectangles contain clock steps that are also necessary. The following is "- the exact operation of the The system is described using the timing diagrams from clock pulse to clock pulse.

ABIAUFDIAGRAMH -

CL-I Transmit i * field to the decoder,

. ■ transfer R ₁ to: ALU (data part), • continue to CIi-Si "_v;>.,.: -..-.

CL-2 : Check F ₁ -.- "■ -". "- .: Ry-:; .--

~ "4" - ,,; Further; after; CL-Ä

Dooket ^ C i? Cö C-Q

CL-J Transfer i-field to decoder 126,

Transfer the surcharge i to the adder, transfer the address field in R. to the adder, on to CL- ² I-.

CL-4 Start the retrieval access, further to CL-5

CL-5 is everything complete above? No, continue to CL-6 Yes, continue to CL-7

CL-6 delay,

back to CL-5.

CL-7 Transfer MDR to R ^,

transmit i-field to decoder 26,. . continue to CL-8.

CL-8 Transfer i-field to decoder 26,

Transfer the surcharge in R ^ to the incrementer, Continue to CL-9.

CL-9 Transfer the hold register to the increment field

InR ₁ , ..

transfer the i-field to decoder 26,

continue to CL-TO. -.-.

BATH

■■ - 21 -

CL-IO Transfer j-field to decoder 26, transfer R. to ALU (data part); start ALU operation, continue to OL-11.

CL-11 Check F., V.

if = "4", go to CL-12 if = "o", continue to CL-I9.

CL-12 Transfer j-field to decoder 26, transfer the addition in R. to the adder,

transfer address in R. to adder,

continue to CL-13 · .- ": .-

CL-13 Start polling access, continue to OL-14 .;

CL-T4 is everything complete above? - ■ "· .-. No, go to CL-15- »Yes, go to CL-16.

CL-I5 delay

back to CL-I4

CL-16 Transfer MDR by R, (data ^field); Transfer j-field to the decoder, further to CL-I7. ',. ^, V: -;

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Docket Ϊ0 968 040

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CL-17 Transfer j-field to the decoder,

transfer surcharge in R. to the iricrementer,

continue to CL-I8. .

CL-18 Transfer hold registers to R.

Transfer jF "ld to the decoder -, further to CL-I9.

ν GL-I9 Has the operation in the ALU been completed?

No, continue to CL-20,

Yes, on to CL-21.

CL-20 delay

back to CL-19

CL-21 Transfer k-field to the decoder

transfer the result to R ^ (data field), ^ on to CL-22.

CL-22 Check F ^,

if = "1", continue to CL-2j5, if = "O", continue to "END ¹¹ .

CL-23 Transfer k-field to the decoder,

Transfer surcharge field from R ^ to adder, transfer address field from R. to adder, transfer R, into the MDR '(data field), further to CL-24, λ, - "\ e. ■. .-.

ORIGINS.

Ί965SQ6

CL-24 start memory access ,. , -

continue to CL-25.

CL-25 Is everything complete above?
Nuin, on to CL-26,
yes, continue to CL-27. _:; ·

CL-26 delay,

back to CL-25. · '

CL-27 Transfer Ie field to the decoder, transfer surcharge field from R. to incrementer, on to CL-28. _; "

CL-28 Transfer k-field to the decoder,

Transfer hold register to the surcharge field of R ₁ , further to "EM3E".

It is now assumed that the working memory. 14 with Initial data and address information has been loaded in a suitable manner and that there is a Operation, which is an execution operation and the Using the three working registers i, j and k with the bits F., F. and F., which were set to "1", specify thereby implementing both the loading and storing of these registers during operation. The presence

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Docket YC 960 0-0, ;;. _{: ::} .: f ...-.

BATH

an execution instruction in the instruction register causes the decoder 21 to generate a pulse which causes the clock CL-1. This pulse is transmitted to the OR circuit 22 and the gate 24 in order to transmit the i-field of the instruction register to the decoder 26, which determines that the register R. is to be activated and transmits its contents to the output line of the main memory 14 target. The clock signal CL-1 is also applied to the gate 28 in order to transfer the contents of the data field register R ^ to the ALU. Switching off the CL-1 cycle triggers cycle CL-2. CL-2 is transmitted to the gate circuit JO to interrogate the F. field. If this is set to "1", the clock branches to CL-J. If this is set to "1", the clock branches to CL-10. It is now assumed that this field is set to ^I! 1 "is set, whereby an implicit load instruction is specified.

The CL-3 clock is transmitted to OR circuit 22 and gate 24 to restore the i field of the instruction register to switch through to the decoder 26, which again controls the main memory 14 in a register position R. The clock pulse CL-3 is also transmitted to OR circuit 32, ' who through the gate 34 to open the increment field {surcharge field) from register R to be transferred to adder 36. GL-3 also serves to switch through the OR circuit 39, which opens the gate circuit 41, by aaa eff * ktive

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1ST65506

Address field of the register R. to the adder 5'6. transferred to. The output signals of the adder ^ 6 are then transferred to the memory address register of the main memory 18. Switching off the CL-J? Clock pulse generates the CL-4 clock pulse.

This pulse is transmitted to the OR circuit 38 which starts a fetch access of the main memory 18 at the address specified by the MAR. It also sets flip-flop 40 to "1" which is reset to "θ" when the memory fetch is completed. The termination of the CL-4 clock generates the clock pulse CL-5. This is transmitted to the gate 42 and is used to determine whether the retrieval access has actually ended. If flip-flop 40 is still at "1", gate 42 will cause the system to transition to clock CL-6, which only provides a delay. The deactivation of this pulse is transmitted to the OR circuit 44, the output signal of which again generates the clock pulse CL-5. Assuming that the flip-F, lop 40 is now at "θ", then the system proceeds to the clock pulse CL-7.

This clock pulse is transmitted to the OR circuit 47, who puts through gate 49 to view the contents of the MDR on the To transfer memory data line. Simultaneously with this, the CL-7 clock pulse also becomes the OR

Docket / 0 968 040 0 0 i & V / f &

BATH ORIGINAL

Circuit 22 and the gate 24 in order to achieve that the content of the main memory data register is stored in the data field of the R. register. The shutdown of the clock pulse CL-7 generates the clock pulse CL-8.

This clock pulse is transmitted to the OR circuit 22, which opens the gate 24 in order to transmit the contents of the i-field of the instruction register again to the decoder 26, which controls the main memory at the register position R. At the same time, the clock pulse CL-8 is also transmitted to the OR circuit 46, which opens the gate 48 in order to switch the increment field of the R.-R register through to the incrementer, where its content is increased by 1, and transferred to the holding register 52 which is basically a delay and enables the clock CL-9 after the clock signal CL-8 has ended, CL-9 being transmitted to the OR circuit 55 which opens the gate circuit 57 to the incremented address im Transfer holding register 52 in the increment field of the register R ^ . As before, the i-field of the instruction register is transmitted by the CL-9 clock to the decoder 26, whereby the register R. is set. Turning off DL-9 completes the store operation in working register R. specified by the i field of the instruction register. The end of CL-10 ^ eite ^ t'eijcakt the same operation for the j-field of the InsWuAf & sregister and affects the evaluation of the J-field P ₁ . Subsequently

η, «. vn ma _n , _in 00982 ^ 71 ^ 2? - -

Docket YO 968 040

BATH ORIGINAL

the primary difference is the clock pulses CL-1Q - CL-I8 in that the clock pulses CL-10.01, -12.01, -16.01, -17 and CL-18 is transmitted to the OR circuit 54 which gate 56 opens to the j field of the instruction register to the decoder 26, which now controls the register position R. in the main memory 14. The remaining J

Operations are essentially identical to those already described, i.e., CL-12 becomes the OR circuits j> 2 and 39 Transferring the contents of the two address fields to the adder 56 as well as it with the pulses CL-3 # etc. was the case. Therefore, provided that there is a "1" in the F. field, it becomes the register position Usually assumed to be loaded with a new data word from the main memory after the clock pulse CL-18 has ended, whereby the clock pulse CL-19 is generated.

This clock pulse is transmitted to the gate circuit 58 in order to query the setting of flip-flop 60, which would be set to "1" when the ALU operation was completed. This took place with the help of the clock pulse CL-10. The completion causes the relevant operation in the ALU, that the line "operation complete" carries a signal, which resets the flip-flop 60 to "θ". When the operation is not yet complete, CL-20 is generated, which also only represents a delay and clocks back to CL-19 * When the operation is complete, CL-21 is generated.

Docket W 968 _oW 009 * 23/1 4t2 BAtJ ₇ DjJIGIl) IAL ₁

This TaKtimpuls is transmitted to the ODIiK circuit 60, which opens gate 64 to enter the K-PeId of the instruction

S to the decoder 26 to - the Rugister-

po.iition "R, of the main memory 14. CL-LiI is also transmitted to the port · 60, which contains the result the ALL in the data field of the R. '^ interposition R, transfers.

"Dar- switching off- CL ~ 21 causes CL - / - ^. This pulse ™ is transmitted to gate 69. If ... nn a" θ "is determined,

Then the current sequence of ροrations is ended and the

■ Transfer the next instruction into the instruction register ¹ , but if it is assumed that this P.jld is set to ^tr T ", then the clock goes to CL-23 via ^1. Servant clock pulse -. CL-23 becomes the ODjiR- Gate L <- , whereby gate 64 was switched through in order to transfer the K-PuId of the instruction logger again to the decoder 26 so that the working register position R. can be controlled with this ^ drjGßv. Qü-'d the -ODKR - Tor'- 32 and the Tor>{"to transfer the Incr jmentf.ild of the R. register position lik to Λ: -. m -tddiuryr ^ t to transfer. D:; r clock pulse CL-L: ^ ν, -is transmitted f- ^ in ^ r to the CD ^ R gate yj to the gate ^; . rG dui - ,: lizu: -t-ill ^ n "- thus represents · ff _^; ^ OIV ai'esi'e-Fold by DER i \ _fc .iptt, rpor: ition i _v .. Can be transmitted to d ^ rn / iddi-irai · 26. WIM -.v ^ an ^ rrignal-j d- ^ n..; di'-r ^ i ^l s are then diroi-ct.

- in there.;. ·. ^: ;.-.- 'i'eli'.; r? -idr - 'rronro;_; is, r iz main trpoich ^ rc 1w-; ji-

brews. ai ^ iuiiz: iti ,: v / ird . \: v I; .h & lt of the data fields ci-ii '.-. ji-ifiatvi-rporir ia-: i i ... through ai> .i 1 .rnchaltunr 70 "with help X : r -" i ^ k-tir ■ 'L-'c-- ;. Lva ^ n Say .i *: l- * tenr'j _; --ister d-jr H-xUpt-

0098 2 9 / U4 2

; Memory 18 surpassed.-D it. "Clock control then works over the clock CL-24.

üL-24- initiates access to the main memory.-.- JG for:; ine üipüichwr operation: and also sets the flip-flop 72 to "i". Switching off the clock pulse CL * -2h generates the clock pulse CL-2 ^. ..Di ·.-Nor checks with the gate: 7 / l- whether the .Memory access is complete. If this is not the case / the system goes to the clock pulse CL-26, which is used for the delay and when finished, returns to GL-c-'y «takes; "If you now assume that the access has been completely carried out, the system branches to the clock CL-27. This clock is transmitted via -". d-io ODisi-i circuit-: 02 to the gate 6'j - to be switched through, which now v / iedcjr the k-t? - .; ld of the instruction register to. the decoder Löübur, which v / iader controls the register position: R. ' Gluichzciti £ "is also transmitted CL-27." On the OR gate 40, jj "W-jlches the toi '^ b' - t, which in turn now has the inci'oment field of the register position R, over ¹ Incrementer i..ü, where diesor \ i-.jvt is increased by "1 - ^#r jrjrhöht in the holding register " _- .. ' above ". The end of the; clock pulse CL-2.7 calls the clock pulse CL-2c5 h-.U ¹ VOr ¹ J der au. " the OR gate 62 and the gate C ^] i üboi'tra ^ en -virird, so that the- k-E'üld of the instruction _{i ''t}; istera an ^. 'is controlled by the decoder 26 access to the working memory 'I ¹ I- at the register position R, to ■ _f \: lutt iiij wQ-lx-i the clock pulse CL-28 to the üDER circuit

■ Jj transfer-; rtragfjn and. the gate 57. is switched through. The η, f VnP, = n 00982.9 / U "42 '

Docket xO 9üb 0 lO - - '

Contents of the holding register ^ c? The RugisterpositLon R is now stored in the increment field in the working memory 1Λ. The cortex of the T .kt impulse CL- ^ ö indicates the current instruction sequence , after which the Cys-tom then again <■: Ina new instruction in the instruction register jirijibtj where, as previously explained, - the system control independent he follows.

The above description, together with the clock pulse diagram, completes the description of the present exemplary embodiment of the invention. The R. register addresses (i, j, k) could be replaced by other address designations that refer to other registers that are part of the working memory 14. Here, too, the decoder 26 would automatically decode the appropriate storage register positions and the controls explained for carrying out the loading and storing operations would also be automatically initiated and carried out by the dot ion fields beginning with F., P. and F ₁ are appropriately charged.

Furthermore, instead of a 1-bit field, for example, which is carried with every instruction address, a two-bit field can be used that leads to either a Load or store branch, might -which an even greater operational flexibility would result.

BATH ORIGINAL

However, this would require more circuitry accordingly., to perform the check and branch operations.

Finally, it should also be mentioned that with the present system normal instructions can also be processed in the usual V / t.ise, ie not loop instructions, whereby the ι ·; ins division by ¹ V; t <-uorbits on O a llebenrehlui; for the circuit * - * of the

create a lying system ». ^

There are also alternative methods for the B .. st Immune of the address, which would be used for the storage and retrieval operations of the present system, whereby, for example, dif- use is usually-- ·! ¹ indexr-. _{} j} ister to stop m Λ · ^ ν address information bew-Mviot w ^ id ^ xi could. Then. v / ürdi.-es in any case only notv;> iidi _t> . "-, in, in the ArbyitsnpL-i ·:! * Foldlänjen to be provided, di ^j in ä-v La _L e pind, -div".,. Uressen special index registers that are used nolluii, ;; uj

specify. Serve would-I. also additional Io _for : set up circuits and switches, but with the field length? the ii- _t "is the , xvb : itsGp-iich. ^! rr 1-τ verriiv ^ it could become.

0 09829 / 1A
BATH ORIGINAL

Claims (1)

goH, December 28th, 1969 jo-sk Fa t e η ta η r. ρ r ü ehe I. Device for program control of an electronic . Digital computer3, with a main memory, an instruction unit, an arithmetic unit and several working memory registers, characterized in that a device for initial loading of the work epuichuriv-ßiü-feer (i4; Fig.1) with data and addresses £ rzeu _t, int änder information provided further dais in the Inrtruktionseinheit (10) one of a, single - / usl'ührungs into trukt ion controlled. ... Equipment for the transfer of ce ^ en in the work memory '-' icherrcgictern gosstored data to 'vin in the other part of the d-is itüchnern and for the ..' ue the charge of this Arb'aitHspLlchü'i's from the ".'iUpt.-y icher (18), <;, up a'jx "Adre.f ^; fe formed ■ iU? d -.- r in it: contained adre. ^r ; senerzeu £ 'jnd'jn - information, before _t üSch'? r. is and that finally W'-itci- ¹ , called by ü'-i''-Π ^: incit ^r en insti'uktion ■; tfu-3rt-, r -inrichtung zur. .itou ^ rung d * .ri:; pt; iohu α ·. :: Γ, '- u-ultatc diesei "In.' / tx-u.-ctlcn both · in tion. \ rboit5;: - p'jich 'jrregistern, al ;; also in the main pe iehf-r an' jivr Adrenpf ;, uie dureL./lie adressenjrzfiüf _ \ - nde. 00 982 9 / U42 , t .υ .Ji.-. GC BAD ORIOIWAt - 33 -. ■■; ■■ - .; ". ■; ■ - ■■■; ■. _" .. Information is intended, is provided. Method for program control by means of a ^ inrlehtung, after - / aisprucii Ij icnnot that in .-- inom Incrti-utctionsstrom before it enters an initialized work- memory contents, are composed of DATAN and address '' producing information that will be return to load them into the -spezifiziert, that continue inside the .Programmschleife a particular ivrbeitsspeicherregister, the contents to a processing; ^ Stoll of the computer is transmitted, specified is, where the addressgenerateu. Information in the specified working memory register is used for the formation of the main memory address, and that finally the main memory at this - ■ "" ■ '"■ .-' ■" ■ "'ι Address controlled and a new one. food products ^ nde ^ Information aur the present: is formed in this jirboit memory ¹ stored address-generating information and this new address-generating information is stored back in this specified work memory register. 00982 9/1442
ⁿ BADORK3INAL