CN110020556A - Using physics can not reproduction technology tangle and fetch system - Google Patents

Abstract

The present invention discloses an entanglement and retrieval system using a physical non-copyable technology, comprising: an anti-fuse PUF memory cell array, which can generate at least one key; and a processing circuit connected to the anti-fuse PUF memory cell; wherein, during an entanglement action, the processing circuit receives a plaintext and the at least one key, and generates a ciphertext according to the plaintext and the at least one key; and during a retrieval action, the processing circuit receives the ciphertext and the at least one key, and generates the plaintext according to the ciphertext and the at least one key.

Description

Entanglement and Retrieval System Using Physically Unreproducible Technology

technical field

The present invention relates to a system, and more particularly, to an entanglement and recall system using a physically unclonable function (PUF for short).

Background technique

The physically unclonable function (PUF technology for short) is an innovative way to protect the data inside an integrated circuit chip (IC chip) and prevent the internal data of the integrated circuit chip from being stolen. According to the PUF technology, the integrated circuit chip can generate a unique random code. The random code can be used as a unique ID code on the integrated circuit chip.

In general, PUF technology utilizes the manufacturing variation of integrated circuit chips to obtain unique random codes. This manufacturing variation includes process variation of integrated circuit chips. That is, even if there are precise process steps to fabricate an integrated circuit chip, its random code is almost impossible to duplicate.

In other words, the ID codes of two integrated circuit chips produced by the same process cannot be exactly the same. Therefore, integrated circuit chips with PUF technology are generally used in applications with high security requirements.

U.S. Patent No. 9,613,714 discloses PUF techniques and related random code generation methods applied to program-once memory cells and memory cell arrays. The one-time programming memory cell is referred to as an OTP memory cell for short.

In this PUF technology, the process variation in the manufacture of antifuse-type OTP memory cells is used to make the programmed OTP memory cells generate unpredictable memory states, which can be used as a one-bit random code . Furthermore, the OTP memory cell used in the PUF technology can also be called an antifuse-type PUF cell, and the OTP memory cell array can also be called an antifuse-type PUF cell array. array).

Similarly, after the anti-fuse type PUF memory cell array is completed and undergoes a program action, a multi-bit random code has been recorded in the anti-fuse type PUF memory cell array. Furthermore, in the field of PUF technology, a program action and another program action (enroll action) have the same meaning. That is, the anti-fuse type PUF memory cell can be programmed, or it can be said that the anti-fuse type PUF memory cell can be programmed (enrolled).

SUMMARY OF THE INVENTION

The main purpose of the present invention is to provide an entanglement and retrieval system, comprising: an anti-fuse-type PUF memory cell array capable of generating at least one key; and a processing circuit connected to the anti-fuse-type PUF memory cell to generate at least one key; receiving the at least one key; wherein, during an entanglement action, the processing circuit receives a plaintext and the at least one key, and generates a ciphertext according to the plaintext and the at least one key; and during a retrieval action , the processing circuit receives the ciphertext and the at least one key, and generates the plaintext according to the ciphertext and the at least one key.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail with the accompanying drawings as follows:

Description of drawings

FIG. 1 is a schematic diagram of the entanglement and retrieval system of the present invention.

Figure 2A is a first embodiment of the entanglement and retrieval system of the present invention.

FIG. 2B and FIG. 2C are an example of the sequence adjustment procedure and the sequence recovery procedure performed by the sequential logic circuit of the first embodiment.

2D and 2E are schematic diagrams of the scrambled logic circuit and its operation.

Figure 3A is a second embodiment of the entanglement and retrieval system of the present invention.

FIG. 3B and FIG. 3C are an example of the sequence adjustment process and the sequence recovery process performed by the sequence logic circuit of the second embodiment based on asymmetric switching.

FIG. 3D and FIG. 3E are an example of the sequence adjustment process and the sequence recovery process performed by the sequence logic circuit of the second embodiment based on asymmetric exchange.

FIG. 3F is another example of the sequence adjustment process and the sequence recovery process performed by the sequence logic circuit of the second embodiment.

Figure 4A is a third embodiment of the entanglement and retrieval system of the present invention.

4B and 4C are an example of an encryption process and a decryption process performed by the encryption logic circuit of the third embodiment.

4D and 4E are another example of the encryption process and the decryption process performed by the encryption logic circuit of the third embodiment.

【Symbol Description】

100, 200, 300, 400: Entanglement and random code generators

110, 210, 310, 410: Antifuse PUF memory cell array

120: Processing Circuits

130, 240, 340, 440: storage circuits

220, 320, 420: sequential logic circuits

222, 224, 232, 234, 321, 322, 323, 324: registers

230, 330, 430: Disrupting logic circuits

325, 326, 327, 328: registers

329: Comparison table

450: Encrypted Logic Circuit

452, 454: Register

456: Data Encryption Standard Circuit

458: Advanced Encryption Standard Circuit

800～831, 900～931: XOR gate

Detailed ways

Please refer to FIG. 1 , which is a schematic diagram of the entanglement and retrieval system of the present invention. The entanglement and retrieval system 100 is disposed in an integrated circuit chip (IC chip). The system 100 includes an anti-fuse type PUF memory cell array 110 and a processing circuit 120 . Among them, the anti-fuse-type PUF memory cell array 110 has been programmed enrollment.

According to an embodiment of the present invention, the anti-fuse PUF memory cell array 110 can output a key to the processing circuit 120 during the entanglement operation and the retrieval operation. For example, during the entanglement operation, the processing circuit 120 receives the plain text and the key and generates the cipher text. The ciphertext can be stored in the storage circuit 130 . For example, the storage circuit 130 may be a non-volatile memory or a hard disk. Of course, the storage circuit 130 may also be included in the system 100 .

Furthermore, during the retrieval operation, the processing circuit 120 receives the ciphertext output by the storage circuit 130 . Next, the processing circuit 120 generates the plaintext according to the ciphertext and the key.

According to an embodiment of the present invention, the anti-fuse type PUF memory cell array 110 is composed of a plurality of anti-fuse type OTP memory cells. Due to process variation, the memory state of the antifuse PUF memory cells in the enrolled antifuse PUF memory cell array 110 cannot be predicted. Therefore, the antifuse-type PUF memory cell array 110 in the integrated circuit chip can provide unpredictable and unique keys to the processing circuit 120 .

That is, since the key of the system 100 is generated by the anti-fuse PUF memory cell array 110 inside the integrated circuit chip, the outside of the integrated circuit chip cannot easily know the content of the key. Therefore, even if the ciphertext in the storage device 130 is obtained, since the key generated by the antifuse PUF memory cell array 110 cannot be known, the ciphertext cannot be cracked.

In other words, the ciphertext generated by the entanglement and retrieval system 100 of a specific integrated circuit chip can only be retrieved as plaintext by the specific integrated circuit chip. Other integrated circuit chips with similar structures cannot retrieve the ciphertext generated by a specific integrated circuit chip as plaintext due to different key contents.

Please refer to FIG. 2A , which shows a first embodiment of the entanglement and retrieval system of the present invention. The entanglement and retrieval system 200 is disposed in an integrated circuit chip (IC chip). The system 200 includes an anti-fuse-type PUF memory cell array 210 and a processing circuit. The processing circuit includes a sequence logic circuit 220 and a randomize logic circuit 230 .

During the entanglement action and the retrieval action, the anti-fuse PUF memory cell array 210 can output the first key KEY1 to the scrambled logic circuit 230 . For example, during the entanglement action, the sequential logic circuit 220 receives the plaintext Data_p. The first data Data_s is generated after a sequence adjustment process is performed. Next, the scrambled logic circuit 230 receives the first data Data_s and the first key KEY1 and generates the ciphertext Data_c. The ciphertext Data_c can be stored in the storage circuit 240 .

Furthermore, during the retrieval operation, the scrambled logic circuit 230 receives the ciphertext Data_c and the first key KEY1 and generates the first data Data_s. Next, the sequence logic circuit 220 receives the first data Data_s and performs a sequence reversing process to generate the plaintext Data_p.

According to the first embodiment of the present invention, the sequence logic circuit 220 designs the sequence adjustment procedure and the sequence recovery procedure based on symmetric swapping. Please refer to FIG. 2B and FIG. 2C , which illustrate an example of the sequence adjustment procedure and the sequence recovery procedure performed by the sequential logic circuit of the first embodiment.

As shown in FIG. 2B , the sequential logic circuit 220 includes two registers 222 , 224 . The register 222 receives the plaintext Data_p, and the plaintext Data_p is divided into four parts P1-P4. For example, assuming that the plaintext is 32 bits (bits), it can be divided into 4 bytes (bytes). That is, the contents of the addresses A31 to A24 in the register 222 are the first part P1 of the plaintext, the contents of the addresses A23 to A16 are the second part P2 of the plaintext, and the contents of the addresses A15 to A8 are the third part P3 of the plaintext, The content in addresses A7 to A0 is the fourth part P4 of the plaintext.

When the sequence logic circuit 220 performs the sequence adjustment procedure, the first part P1 and the second part P2 are swapped, and the third part P3 and the fourth part P4 are swapped to generate the first data Data_s and store it in the register 224 . Therefore, after the sequence adjustment procedure, the contents of addresses A31 to A24 in the register 224 are the second part P2 of plaintext, the contents of addresses A23 to A16 are the first part P1 of plaintext, and the contents of addresses A15 to A8 are plaintext The content in the fourth part P4 and addresses A7 to A0 is the third part P3 of the plaintext.

As shown in FIG. 2C , the register 222 receives the first data Data_s, and the first data Data_s is the second part P2 , the first part P1 , the fourth part P4 and the third part P3 of the plaintext in sequence. That is, the contents of the addresses A31 to A24 in the register 222 are the second part P2 of the plaintext, the contents of the addresses A23 to A16 are the first part P1 of the plaintext, and the contents of the addresses A15 to A8 are the fourth part P4 of the plaintext, The content in addresses A7 to A0 is the third part P3 of the plaintext.

When the sequence logic circuit 222 performs the sequence recovery procedure, the second part P2 and the first part P1 are swapped, and the fourth part P4 and the third part P3 are swapped, and the plaintext Data_p is generated and stored in the register 224 . Therefore, after the sequential reply procedure, the contents of the addresses A31 to A24 in the register 224 are the first part P1 of the plaintext, the contents of the addresses A23 to A16 are the second part P2 of the plaintext, and the contents of the addresses A15 to A8 are the plaintext. The content in the third part P3 and addresses A7 to A0 is the fourth part P4 of the plaintext. In other words, after the sequential reply procedure, the first data Data_s can be restored as plaintext Data_p.

As can be seen from the above description, when the sequence adjustment procedure is performed, the first byte is swapped with the second byte, and the third byte is swapped with the fourth byte. Therefore, after the sequence adjustment procedure, the sequence of the first data Data_s is the second byte, the first byte, the fourth byte and the third byte of the plaintext in sequence. Furthermore, after the sequential reply procedure, the first data Data_s can be restored as plaintext Data_p.

Of course, the above sequence adjustment procedure and sequence recovery procedure are only one embodiment of the present invention. Those skilled in the art can also design other sequence adjustment procedures and sequence recovery procedures based on symmetric swapping. For example, during the sequence adjustment process, the fourth part P4 of the plaintext Data_p is swapped with the first part P1, and the third part P3 and the second part P2 are swapped. After that, the first data Data_s are generated. During the sequence reply procedure, the first data Data_s is returned as plaintext Data_p.

FIG. 2D and FIG. 2E are schematic diagrams of the scrambled logic circuit and its operation. The scrambled logic circuit 230 includes two registers 232 and 234 and a plurality of XOR gates 900 to 931 . After the scramble logic circuit 230 performs an XOR operation on the first data Data_s and the first key KEY1, the ciphertext Data_c is generated.

For example, the first data Data_s received by the register 232 is 32 bits, that is, s31-s0; the first key KEY1 received by the register 234 is 32 bits, that is, k31-k0. As shown in FIG. 2D , after the bit s0 of the first data Data_s and the bit k0 of the first key are XORed by the XOR gate 900, the bit c0 of the ciphertext is generated. Using the same operation method, other bits c31-c1 of the ciphertext Data_c can also be generated.

In addition, the scrambled logic circuit 224 generates the first data Data_s after XOR operation is performed on the ciphertext Data_c and the first key KEY1. As shown in FIG. 2E , the register 232 receives the ciphertext Data_c, that is, c31˜c0; the register 234 receives the first key KEY1. Furthermore, the bit c0 of the ciphertext Data_c and the bit k0 of the first key are XORed by the XOR gate 900 to generate the bit s0 of the first data. Using the same operation method, other bits s31˜s1 of the first data Data_s can also be generated.

Furthermore, those skilled in the art can also make modifications according to the entanglement and retrieval system 200 of the first embodiment. For example, during the entanglement operation, the scrambled logic circuit 230 is used to receive the plaintext, and the first data is generated according to the plaintext and the first key KEY1. Next, after the sequence logic circuit 220 performs a sequence adjustment procedure on the first data, a ciphertext is generated. During the retrieval operation, the sequence logic circuit 220 is used to perform a sequence recovery procedure on the ciphertext and generate the first data. Next, the scrambled logic circuit 230 receives the first data and the first key KEY1 to generate plaintext.

Please refer to FIG. 3A , which shows a second embodiment of the entanglement and retrieval system of the present invention. The entanglement and retrieval system 300 is disposed in an integrated circuit chip (IC chip). The system 300 includes an anti-fuse-type PUF memory cell array 310 and a processing circuit. The processing circuit includes a sequential logic circuit 320 and a shuffling logic circuit 330 .

During the entanglement operation and the retrieval operation, the anti-fuse PUF memory cell array 210 can output the first key KEY1 and the second key KEY2 to the sequential logic circuit 320 and the scrambled logic circuit 330 . For example, during the entanglement operation, the sequence logic circuit 320 generates the first data Data_s after receiving the plaintext Data_p and the first key KEY1 and performing the sequence adjustment procedure. Next, the scrambled logic circuit 330 receives the first data Data_s and the second key KEY2 and generates the ciphertext Data_c. The ciphertext Data_c can be stored in the storage circuit 340 .

Furthermore, during the retrieval operation, the scrambled logic circuit 330 receives the ciphertext Data_c and the second key KEY2 and generates the first data Data_s. Next, the sequence logic circuit 320 receives the first data Data_s and the first key KEY1, and after performing the sequence reply procedure, generates the plaintext Data_p.

Compared with the first embodiment, the sequence logic circuit 320 of the second embodiment can perform the sequence adjustment procedure and the sequence recovery procedure based on asymmetric swapping or symmetric swapping. Only the sequential logic circuit 320 will be described below, and the operations of other circuits will not be described again.

Please refer to FIG. 3B and FIG. 3C , which illustrate an example of the sequence adjustment procedure and the sequence recovery procedure performed by the sequential logic circuit of the second embodiment based on asymmetric switching. The sequential logic circuit 320 includes two registers 321 and 322, wherein the register 321 is a circular shift register. For example, the plaintext Data_p received by the register 321 is 32 bits, that is, p31-p0; and the first key KEY1 received by the register 322 is 32 bits. When the sequence logic circuit 320 performs the sequence adjustment procedure, the register 321 is shifted right, that is, shifted from left to right (L→R). The value of the first key KEY1 is used to determine the number of bits by which the register 321 is shifted to the right.

Furthermore, when the sequence logic circuit 320 performs the sequence recovery procedure, the register 321 performs a shifted left operation, that is, a shift from right to left (R→L). Furthermore, the value of the first key KEY1 is used to determine the number of bits by which the register 321 is shifted to the left.

As shown in FIG. 3B, the register 321 receives the plaintext Data_p. Assuming that the value of the first key KEY is "10", the register 321 is shifted to the right by 10 bits. Therefore, after the sequence logic circuit 320 performs the sequence adjustment procedure, in the register 321, the bit p9 of the plaintext Data_p becomes the most significant bit (MSB) of the first data Data_s, and the bit p10 of the plaintext Data_p becomes the least significant bit (LSB) of the first data Data_s.

As shown in FIG. 3C, the register 322 receives the first data Data_s, and the value of the first key KEY is "10". When the sequence logic circuit 320 performs the sequence recovery procedure, the first data Data_s in the register 321 can be recovered as plaintext Data_p according to the first key KEY.

Please refer to FIG. 3D and FIG. 3E , which illustrate an example of the sequence adjustment process and the sequence recovery process performed by the sequence logic circuit of the second embodiment based on asymmetric switching. The sequential logic circuit 320 includes three registers 323 - 325 and a plurality of XOR gates 800 - 831 .

When the sequence logic circuit 320 performs the sequence adjustment procedure, the register 323 receives the 32-bit plaintext Data_p, that is, p31-p0. Register 325 receives the first key KEY1. Furthermore, the addresses A31˜A0 of the register 323 are XORed with the first key KEY1 to form a new address. The sequence logic circuit 320 adjusts the sequence of the plaintext Data_p according to the new address, and stores the plaintext Data_p in the register 324 to become the first data Data_s.

Furthermore, when the sequence logic circuit 320 performs the sequence recovery procedure, the register 323 receives the first data Data_s. Register 325 receives the first key KEY1. Similarly, the addresses A31 to A0 of the register 323 will be XORed with the first key KEY1 to form a new address. The sequence logic circuit 320 adjusts the sequence of the first data Data_s according to the new address and stores it in the register 324, and the content of the register 324 is the plaintext Data_p of the reply.

The sequence adjustment procedure and the sequence recovery procedure are described below by taking the first key KEY1 as "10101" as an example.

As shown in FIG. 3D, during the sequence adjustment procedure, the register 323 receives the plaintext Data_p. Furthermore, the addresses A31˜A0 of the register 323 are XORed with the first key KEY1 to form a new address.

For example, the address A31 ("11111") is XORed with the key KEY1 ("10101") and the new address is A10 ("01010"), so the content p31 of address A31 of register 323 will be stored in register 424 Inside address A10. The new address after the XOR operation between the address A30 ("11110") and the key KEY1 ("10101") is A11 ("01011"), so the content p30 of the address A30 of the register 323 will be stored in the address A11 of the register 424. The new address after the XOR operation between the address A1 (“00001”) and the key KEY1 (“10101”) is A20 (“10100”), so the content p1 of the address A1 of the register 323 will be stored in the address A20 of the register 424 . The new address after the XOR operation between the address A0 (“00000”) and the key KEY1 (“10101”) is A21 (“10101”), so the content p0 of the address A0 of the register 323 will be stored in the address A21 of the register 424.

Therefore, after the sequence adjustment procedure is performed, the content in the register 324 is the first data Data_s. That is, the contents stored in the addresses A31 to A0 in the register 324 are sequentially p10, p11, p8, p9, p14, p15, p12, p13, p2, p3, p0, p1, p26, p27, p24, p25, p30 , p31, p28, p29, p18, p19, p16, p17, p22, p23, p20, p21.

As shown in FIG. 3E, the register 323 receives the first data Data_s during the sequence recovery procedure. Furthermore, the addresses A31˜A0 of the register 323 are XORed with the first key KEY1 to form a new address.

For example, the address A31 ("11111") is XORed with the key KEY1 ("10101") and the new address is A10 ("01010"), so the content p10 of address A31 of register 323 will be stored in register 424 Inside address A10. The new address after the XOR operation between the address A30 ("11110") and the key KEY1 ("10101") is A11 ("01011"), so the content p11 of the address A30 of the register 323 will be stored in the address A11 of the register 424. The new address after the XOR operation between the address A1 ("00001") and the key KEY1 ("10101") is A20 ("10100"), so the content p20 of the address A1 of the register 323 will be stored in the address A20 of the register 424. The new address after the XOR operation between the address A0 ("00000") and the key KEY1 ("10101") is A21 ("10101"), so the content p21 of the address A0 of the register 323 will be stored in the address A21 of the register 424.

Therefore, after the sequence reply procedure is performed, the content in the register 324 is the plaintext Data_p. That is, the contents stored in the addresses A31 to A0 in the register 324 are sequentially p31 to p0.

Of course, the above sequence adjustment procedure and sequence recovery procedure are only one embodiment of the present invention. Those skilled in the art can also design other sequence adjustment procedures and sequence restoration procedures based on symmetric swapping and asymmetric swapping.

Please refer to FIG. 3F , which is another example of the sequence adjustment procedure and the sequence recovery procedure performed by the sequential logic circuit of the second embodiment. The sequential logic circuit 330 includes three registers 326 , 327 , 328 and a lookup table 329 . The register 326 receives the plaintext Data_p, the register 328 receives the first key KEY1, and the register 327 generates the first data Data_s. Furthermore, the operation mode used by the sequential logic circuit 320 is recorded in the comparison table 329 .

For example, according to the content of the comparison table 329, when the value of the first key KEY1 is an odd number, the sequence logic circuit 320 performs the sequence adjustment procedure and the sequence recovery procedure shown in FIG. 3D and FIG. 3E based on the symmetry exchange. In addition, when the value of the first key KEY1 is an even number, the sequence logic circuit 320 performs the sequence adjustment procedure and the sequence recovery procedure shown in FIG. 3B and FIG. 3C based on the asymmetric exchange.

Of course, the content of the look-up table 324 is not limited to only two operation modes. Those skilled in the art can design more operation modes to be applied to the sequential logic circuit 320 .

Likewise, the entanglement and retrieval system 300 of the second embodiment can also be modified. For example, during the entanglement operation, the scrambled logic circuit 330 is used to receive the plaintext, and the first data is generated according to the plaintext and the first key KEY1. Next, the sequence logic circuit 320 performs a sequence adjustment procedure according to the second key KEY2 and the first data, and generates a ciphertext. During the retrieval operation, the sequence logic circuit 320 is used to perform the sequence recovery procedure according to the second key KEY2 and the ciphertext to generate the first data. Next, the scrambled logic circuit 330 receives the first data and the first key KEY1 to generate plaintext.

Please refer to FIG. 4A , which shows a third embodiment of the entanglement and retrieval system of the present invention. The entanglement and retrieval system 400 is disposed in an integrated circuit chip (IC chip). The system 400 includes an anti-fuse-type PUF memory cell array 410 and a processing circuit. The processing circuit includes a sequential logic circuit 420 , a scrambled logic circuit 430 and an encryption logic circuit 450 .

During the entanglement action and the retrieval action, the anti-fuse PUF memory cell array 410 can output the first key KEY1, the second key KEY2, and the third key KEY3 to the sequential logic circuit 420, the scrambled logic circuit 430 and the encryption Logic circuit 450 . For example, during the entanglement operation, the sequence logic circuit 420 generates the first data Data_s after receiving the plaintext Data_p and the first key KEY1 and performing the sequence adjustment procedure. Next, the scrambled logic circuit 430 receives the first data Data_s and the second key KEY2 and generates the second data Data_r. Next, the encryption logic circuit 450 receives the second data Data_r and the third key KEY3 and generates the ciphertext Data_c. The ciphertext Data_c can be stored in the storage circuit 440 .

Furthermore, during the retrieval operation, the encryption logic circuit 450 receives the ciphertext Data_c and the third key KEY3 and generates the second data Data_r. Next, the scrambled logic circuit 430 receives the second data Data_r and the second key KEY2 and generates the first data Data_s. Next, the sequence logic circuit 420 receives the first data Data_s and the first key KEY1, and performs a sequence reversing process to generate the plaintext Data_p.

The operation principles of the sequential logic circuit 420 and the shuffling logic circuit 430 of the third embodiment are the same as those of the second embodiment. Only the encryption logic circuit 450 will be described below, and the operations of other circuits will not be described again.

Please refer to FIG. 4B and FIG. 4C , which illustrate an example of the encryption process and the decryption process performed by the encryption logic circuit of the third embodiment.

For example, as shown in FIG. 4B , the encryption logic circuit 450 includes two registers 452 and 454 and a data encryption standard circuit (DES circuit for short) 456 . The register 452 receives the second data Data_r, and the register 454 receives the third key KEY3. When the encryption logic circuit 450 performs the encryption process, the data encryption standard circuit 456 generates the ciphertext Data_c after receiving the second data Data_r and the third key KEY.

As shown in FIG. 4C, the register 452 receives the ciphertext Data_c, and the register 454 receives the third key KEY3. When the encryption logic circuit 450 performs the decryption process, the data encryption standard circuit 456 generates the second data Data_r after receiving the ciphertext Data_c and the third key KEY.

Of course, the above encryption program and decryption program are only one embodiment of the present invention. Those skilled in the art can also design other encryption programs and decryption programs. Please refer to FIG. 4D and FIG. 4E , which illustrate another example of the encryption process and the decryption process performed by the encryption logic circuit of the third embodiment.

For example, as shown in FIG. 4D , the encryption logic circuit 450 includes two registers 452 and 454 and an advanced encryption standard circuit (AES circuit for short) 458 . The register 452 receives the second data Data_r, and the register 454 receives the third key KEY3. When the encryption logic circuit 450 performs the encryption process, the advanced encryption standard circuit 458 generates the ciphertext Data_c after receiving the second data Data_r and the third key KEY.

As shown in FIG. 4E, the register 452 receives the ciphertext Data_c, and the register 454 receives the third key KEY3. When the encryption logic circuit 450 performs the decryption process, the advanced encryption standard circuit 458 generates the second data Data_r after receiving the ciphertext Data_c and the third key KEY.

Furthermore, the sequence logic circuit 420 in the third embodiment is designed with asymmetric swapping to design the sequence adjustment procedure and the sequence recovery procedure. Those skilled in the art can also design other sequence adjustment procedures and sequence recovery procedures based on symmetric swapping. At this time, the sequence logic circuit 420 does not need to receive the first key KEY1.

Similarly, those skilled in the art can also arbitrarily modify the sequence of actions of the sequential logic circuit 420 , the scrambled logic circuit 430 , and the encryption logic circuit 450 according to the entanglement and retrieval system 400 of the third embodiment. It will not be repeated here. Furthermore, both the scrambled logic circuit 430 and the encryption logic circuit 450 have the characteristic of scrambled the received data, so the encryption logic circuit 450 can also be regarded as another scrambled logic circuit.

As can be seen from the above description, the present invention proposes an entanglement and retrieval system using a physically non-replicable technology. In this system, an unpredictable and unique key is provided by an anti-fuse-type PUF memory cell array, and the processing circuit can convert the plaintext into ciphertext. Since the key content in the antifuse PUF memory cell array cannot be known, the ciphertext cannot be cracked.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the appended claims.

Claims (31)

1. An entanglement and retrieval system comprising: an anti-fuse-type PUF memory cell array capable of generating at least one key; and a processing circuit connected to the anti-fuse PUF memory cell to receive the at least one key; Wherein, during the entanglement action, the processing circuit receives the plaintext and the at least one key, and generates a ciphertext according to the plaintext and the at least one key; and during the retrieval action, the processing circuit receives the ciphertext and the at least one key a key, and the plaintext is generated according to the ciphertext and the at least one key. 2 . The entanglement and retrieval system of claim 1 , wherein the anti-fuse type PUF memory cell array is a programmed anti-fuse type program-once memory cell array. 3 . 3. The entanglement and retrieval system of claim 1, further comprising a storage circuit to store the ciphertext. 4. The entanglement and retrieval system of claim 1, wherein the processing circuit comprises: sequential logic circuits; and A scrambled logic circuit is connected to the sequential logic circuit and the anti-fuse type PUF memory cell array. 5. The entanglement and retrieval system as claimed in claim 4, wherein during the entanglement action, the sequential logic circuit receives the plaintext and performs a sequence adjustment procedure to generate first data; and the scrambled logic circuit receives the first data data and the first key, and generate the ciphertext according to the first data and the first key; and, during the retrieval operation, the scrambled logic circuit receives the ciphertext and the first key, and The first data is generated according to the ciphertext and the first key; the sequence logic circuit generates the plaintext after receiving the first data and performing a sequence reply procedure. 6. The entanglement and retrieval system of claim 5 , wherein the scrambled logic circuit generates the ciphertext after performing an XOR operation on the first data and the first key; and the scrambled logic circuit generates the ciphertext The first data is generated by performing the XOR operation on the ciphertext and the first key. 7. The entanglement and retrieval system of claim 5, wherein the scrambled logic circuit generates the ciphertext after performing an encryption procedure on the first data and the first key; and the scrambled logic circuit generates the ciphertext The first data is generated after the decryption process is performed between the text and the first key. 8. The entanglement and retrieval system of claim 4, wherein the sequential logic circuit is connected to the anti-fuse PUF memory cell array; during the entanglement operation, the sequential logic circuit receives the plaintext and the first gold generating the first data after performing the sequence adjustment procedure; and the scrambled logic circuit receives the first data and the second key, and generates the ciphertext according to the first data and the second key; and, in the During the retrieval action, the scrambled logic circuit receives the ciphertext and the second key, and generates the first data according to the ciphertext and the second key; the sequential logic circuit receives the first data and the first data The plaintext is generated after a key and a sequential reply procedure. 9. The entanglement and retrieval system of claim 8, wherein the scrambled logic circuit generates the ciphertext after performing an XOR operation on the first data and the second key; and the scrambled logic circuit generates the ciphertext The first data is generated by performing the XOR operation on the ciphertext and the second key. 10. The entanglement and retrieval system of claim 8, wherein the scrambled logic circuit generates the ciphertext after encrypting the first data and the second key; and the scrambled logic circuit generates the ciphertext The first data is generated after the decryption process is performed between the text and the second key. 11. The entanglement and retrieval system of claim 4, wherein during the entanglement operation, the scrambled logic circuit receives the plaintext and the first key, and generates the first key according to the plaintext and the first key data; the sequence logic circuit generates the ciphertext after receiving the first data and performing a sequence adjustment procedure; and, during the retrieval operation, the sequence logic circuit receives the ciphertext and performs a sequence reply procedure to generate the first data ; The scrambled logic circuit receives the first data and the first key, and generates the plaintext according to the first data and the first key. 12. The entanglement and retrieval system of claim 11 , wherein the scrambled logic circuit generates the first data after XORing the plaintext with the first key; and the scrambled logic circuit generates the first data. The plaintext is generated after performing the XOR operation on a data and the first key. 13. The entanglement and retrieval system of claim 11, wherein the scrambled logic circuit generates the first data after encrypting the plaintext and the first key; and the scrambled logic circuit generates the first data; The plaintext is generated after the data is decrypted with the first key. 14. The entanglement and retrieval system of claim 4, wherein during the entanglement operation, the scrambled logic circuit receives the plaintext and the first key, and generates the first key according to the plaintext and the first key data; the sequential logic circuit receives the first data and the second key and performs a sequence adjustment procedure to generate the ciphertext; and, during the retrieval operation, the sequential logic circuit receives the ciphertext and the second key The first data is generated after performing a sequence reply procedure; the scrambled logic circuit receives the first data and the first key, and generates the plaintext according to the first data and the first key. 15. The entanglement and retrieval system of claim 14, wherein the scrambled logic circuit generates the first data after XORing the plaintext with the first key; and the scrambled logic circuit generates the first data; The plaintext is generated after performing the XOR operation on a data and the first key. 16. The entanglement and retrieval system of claim 14, wherein the scrambled logic circuit performs an encryption process on the plaintext and the first key to generate the first data; and the scrambled logic circuit generates the first data; The plaintext is generated after the data is decrypted with the first key. 17. The entanglement and retrieval system of claim 1, wherein the processing circuit comprises: sequential logic circuits; and scrambled logic circuits connected to the antifuse-type PUF memory cell array; and An encryption logic circuit is connected to the anti-fuse type PUF memory cell array. 18. The entanglement and retrieval system of claim 17, wherein the encryption logic circuit comprises a data encryption standard circuit, and the data encryption circuit receives the first key generated by the antifuse type PUF memory cell array, and uses for encryption or decryption. 19. The entanglement and retrieval system of claim 17, wherein the encryption logic circuit comprises an advanced encryption standard circuit, and the advanced encryption circuit receives a first key generated by the antifuse PUF memory cell array , used for encryption or decryption. 20. The entanglement and retrieval system of claim 17, wherein the scrambled logic circuit is connected to the sequential logic circuit and the encryption logic circuit; during the entanglement action, the sequential logic circuit receives the plaintext and performs sequence adjustment After the program, first data is generated; and the scrambled logic circuit receives the first data and the first key, and generates second data according to the first data and the first key; and the encryption logic circuit receives the second data After performing the encryption process on the data and the second key, the ciphertext is generated; and during the retrieval operation, the encryption logic circuit receives the ciphertext and the second key and performs the decryption process to generate the second ciphertext data; the scrambled logic circuit receives the second data and the first key, and generates the first data according to the second data and the first key; the sequential logic circuit receives the first data and responds sequentially The plaintext is generated after the program. 21. The entanglement and retrieval system of claim 17, wherein the scrambled logic circuit is connected to the sequential logic circuit and the encryption logic circuit; during the entanglement action, the encryption logic circuit receives the plaintext and the first gold After the encryption process is performed, the first data is generated; the scrambled logic circuit receives the first data and the second key, and generates the second data according to the first data and the second key; the sequential logic circuit receives The ciphertext is generated after the second data is subjected to a sequence adjustment procedure; and, during the retrieval operation, the sequence logic circuit receives the ciphertext and performs a sequence reply procedure to generate the second data; and the scrambled logic circuit Receive the second data and the second key, and generate the first data according to the second data and the second key; and the encryption logic circuit receives the first data and the first key and performs a decryption process After that, the plaintext is generated. 22. The entanglement and retrieval system of claim 17, wherein the scrambled logic circuit is connected to the sequential logic circuit and the encryption logic circuit, and the sequential logic circuit is connected to the anti-fuse PUF memory cell array; During the entanglement action, the sequential logic circuit receives the plaintext and the first key and performs a sequence adjustment process to generate first data; and the scrambled logic circuit receives the first data and the second key, and according to the first data A data and the second key generate second data; and the encryption logic circuit generates the ciphertext after receiving the second data and the third key and performing an encryption process; and, during the retrieval action, the encryption After the logic circuit receives the ciphertext and the third key and performs a decryption process, the second data is generated; the scrambled logic circuit receives the second data and the second key, and generates the second data according to the second data and the first key. Two keys generate the first data; the sequential logic circuit generates the plaintext after receiving the first data and the first key and performing a sequence reply procedure. 23. The entanglement and retrieval system of claim 17, wherein the scrambled logic circuit is connected to the sequential logic circuit and the encryption logic circuit, and the sequential logic circuit is connected to the antifuse PUF memory cell array; During the entanglement operation, the encryption logic circuit receives the plaintext and the first key and performs an encryption process to generate first data; the scrambled logic circuit receives the first data and the second key, and according to the first data data and the second key to generate second data; the sequential logic circuit receives the second data and the third key and performs a sequence adjustment process to generate the ciphertext; and, during the retrieval action, the sequential logic circuit The second data is generated after receiving the ciphertext and the third key and performing a sequence reply procedure; and the scrambled logic circuit receives the second data and the second key, and generates the second data according to the second data and the second key. The key generates the first data; and the encryption logic circuit generates the plaintext after receiving the first data and the first key and performing a decryption process. 24. The entanglement and retrieval system of claim 17, wherein the sequential logic circuit is connected to the scrambled logic circuit and the encryption logic circuit; during the entanglement action, the scrambled logic circuit receives the plaintext and the first key, and generate first data according to the plaintext and the first key; the sequential logic circuit receives the first data and performs a sequence adjustment process to generate second data; and the encryption logic circuit receives the second data and the first data After performing the encryption process with the two keys, the ciphertext is generated; and, during the retrieval operation, the encryption logic circuit receives the ciphertext and the second key and performs the decryption process to generate the second data; the The sequential logic circuit receives the second data and performs a sequential recovery procedure to generate the first data; and the scrambled logic circuit receives the first data and the first key, and generates the first data according to the first data and the first key produce the plaintext. 25. The entanglement and retrieval system of claim 17, wherein the sequential logic circuit is connected to the scrambled logic circuit and the encryption logic circuit; during the entanglement action, the encryption logic circuit receives the plaintext and the first gold After the encryption process is performed, the first data is generated; the sequential logic circuit receives the first data and performs the sequence adjustment process to generate the second data; and the scrambled logic circuit receives the second data and the second key, and Generate the ciphertext according to the second data and the second key; and, during the retrieval operation, the scrambled logic circuit receives the ciphertext and the second key, and generates the ciphertext according to the ciphertext and the second key The key generates the second data; the sequence logic circuit receives the second data and performs a sequence recovery process to generate the first data; and the encryption logic circuit receives the first data and the first key and performs a decryption process , which produces the plaintext. 26. The entanglement and retrieval system of claim 17, wherein the sequential logic circuit is connected to the scrambled logic circuit and the encryption logic circuit, and the sequential logic circuit is connected to the antifuse PUF memory cell array; During the entanglement action, the scrambled logic circuit receives the plaintext and the first key, and generates first data according to the plaintext and the first key; the sequential logic circuit receives the first data and the second key and combines After performing the sequence adjustment process, the second data is generated; and the encryption logic circuit receives the second data and the third key and performs the encryption process to generate the ciphertext; and, during the retrieval operation, the encryption logic circuit receives After the ciphertext and the third key are decrypted, the second data is generated; the sequential logic circuit receives the second data and the second key and performs a sequence recovery process to generate the first data; and the The scrambled logic circuit receives the first data and the first key, and generates the plaintext according to the first data and the first key. 27. The entanglement and retrieval system of claim 17, wherein the sequential logic circuit is connected to the scrambled logic circuit and the encryption logic circuit, and the sequential logic circuit is connected to the anti-fuse type PUF memory cell array; During the entanglement action, the encryption logic circuit receives the plaintext and the first key and performs an encryption process to generate first data; the sequential logic circuit receives the first data and the second key and performs a sequence adjustment process to generate second data; and the scrambled logic circuit receives the second data and the third key, and generates the ciphertext according to the second data and the third key; and, during the retrieval action, the scrambled The logic circuit receives the ciphertext and the third key, and generates the second data according to the ciphertext and the third key; the sequential logic circuit receives the second data and the second key and performs a sequence reply procedure Then, the first data is generated; and the encryption logic circuit generates the plaintext after receiving the first data and the first key and performing a decryption procedure. 28. The entanglement and retrieval system of claim 17, wherein the encryption logic circuit is connected to the scrambled logic circuit and the sequential logic circuit; during the entanglement action, the scrambled logic circuit receives the plaintext and the first the key, and generate the first data according to the plaintext and the first key; the encryption logic circuit receives the first data and the second key and performs the encryption process to generate the second data; and the sequence logic of the ciphertext The circuit receives the second data and performs a sequence adjustment process to generate the ciphertext; and, during the retrieval operation, the sequence logic circuit receives the ciphertext and performs a sequence recovery process to generate the second data; the encryption logic circuit After receiving the second data and the second key and performing a decryption process, the first data is generated; and the scrambled logic circuit receives the first data and the first key, and generates the first data according to the first data and the first key. A key produces the plaintext. 29. The entanglement and retrieval system of claim 17, wherein the encryption logic circuit is connected to the scrambled logic circuit and the sequential logic circuit; during the entanglement operation, the sequential logic circuit receives the plaintext and performs sequence adjustment After the program, the first data is generated; the encryption logic circuit receives the first data and the first key and performs the encryption process to generate the second data; and the scrambled logic circuit receives the second data and the second key, and Generate the ciphertext according to the second data and the second key; and, during the retrieval operation, the scrambled logic circuit receives the ciphertext and the second key, and generates the ciphertext according to the ciphertext and the second key The key generates the second data; the encryption logic circuit receives the second data and the first key and performs a decryption process to generate the first data; and the sequential logic circuit receives the first data and performs a sequence recovery process The plaintext is then generated. 30. The entanglement and retrieval system of claim 17, wherein the encryption logic circuit is connected to the scrambled logic circuit and the sequential logic circuit, and the sequential logic circuit is connected to the antifuse PUF memory cell array; During the entanglement action, the scrambled logic circuit receives the plaintext and the first key, and generates first data according to the plaintext and the first key; the encryption logic circuit receives the first data and the second key and combines After performing the encryption process, the second data is generated; and the sequence logic circuit of the ciphertext receives the second data and the third key and performs the sequence adjustment process to generate the ciphertext; and, during the retrieval action, the sequence The logic circuit receives the ciphertext and the third key and performs a sequence recovery process to generate the second data; the encryption logic circuit receives the second data and the second key and performs a decryption process to generate the first data ; and the scrambled logic circuit receives the first data and the first key, and generates the plaintext according to the first data and the first key. 31. The entanglement and retrieval system of claim 17, wherein the encryption logic circuit is connected to the scrambled logic circuit and the sequential logic circuit, and the sequential logic circuit is connected to the antifuse PUF memory cell array; During the entanglement action, the sequential logic circuit receives the plaintext and the first key and performs a sequence adjustment process to generate first data; the encryption logic circuit receives the first data and the second key and performs an encryption process to generate the first data second data; and the scrambled logic circuit receives the second data and the third key, and generates the ciphertext according to the second data and the third key; and, during the retrieval action, the scrambled The logic circuit receives the ciphertext and the third key, and generates the second data according to the ciphertext and the third key; the encryption logic circuit receives the second data and the second key and performs a decryption process , to generate the first data; and the sequence logic circuit generates the plaintext after receiving the first data and the first key and performing a sequence reply procedure.