JP3490887B2 - Synchronous semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor memory device, and more particularly to a synchronous DRAM (dynamic RAM).

[0002]

2. Description of the Related Art In recent years, various memory LSs have been used in order to eliminate an access gap between a microprocessor and a memory.
Although I has been proposed, all of them are characterized in that input / output is performed in synchronization with an external clock to increase the data transfer rate. One of these synchronous memories is called a synchronous DRAM (hereinafter referred to as "SDRAM").

The SDRAM is provided with auto-refresh and self-refresh as refresh modes.

FIG. 8 is a timing diagram showing an auto refresh operation of the SDRAM chip.

At time t5, the row address strobe signal bar RAS and the column address strobe signal bar CAS are at low level, and the write enable signal bar WE.
If the clock enable signal CKE is at high level, auto refresh is activated. At time t6,
When a signal similar to that at time t5 is input, the auto refresh is repeated again.

In the auto-refresh, a refresh address is generated by an internal refresh counter, one row of memory cells corresponding to the refresh address is refreshed, and then automatically brought into a precharge state.
Normally 4096 to refresh all memory cells
You only need to repeat the auto refresh once.

FIG. 9 is a timing chart showing the self-refresh operation of the SDRAM chip.

At time t7, the row address strobe signal bar RAS, the column address strobe signal bar CAS, and the clock enable signal CKE become low level, and the write enable signal bar WE becomes high level, and then the clock enable signal CKE becomes low. Self-refresh is activated during the low level.

The self-refresh is an operation in which an internal timer automatically performs the same operation as the above-described auto-refresh at regular intervals.

In the refresh method standardized by JEDEC, a plurality of memory banks are to be refreshed alternately, and each memory bank is refreshed at the same time, or in parallel with the refresh operation for one memory bank, It was not possible to access the other memory bank. Also, it was not possible to specify a bank for refreshing.

Synchronous DR having a plurality of memory banks, each of which is independently enabled for memory access operation
The AM is provided with a function for refreshing the plurality of memory banks at the same time, a function for designating one to a plurality of memory banks among the plurality of memory banks to enable refreshing, or in parallel with the refresh operation independently. As a conventional technique for improving the memory function by performing the memory access as described above, Japanese Patent Laid-Open Publication No.
-139074, JP-A-7-226077, JP-A-8-
77769, and further, JP-A-7-169266 and the like.

FIG. 7 shows a block diagram of a configuration example of the SDRAM disclosed in Japanese Patent Laid-Open No. 9-139074 as one of the conventional techniques.

The SDRAM of this configuration example includes a memory array 200A forming a memory bank A (BANKA),
Memory array 2 forming a memory bank (BANKB)
00B and. Each of the memory arrays 200A and 200B includes dynamic memory cells arranged in a matrix, each memory cell having a capacitor for storing data, a gate coupled to a word line (not shown), and a drain having a complementary bit line (see FIG. And a MOS transistor (not shown).

One word line (not shown) of the memory array 200A is driven to the selection level according to the result of decoding the row address signal by the row decoder 201A. A complementary bit line (not shown) of the memory array 200A is coupled to the sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary bit line by reading data from the memory cell. The column switch circuit in that case is a switch circuit for individually selecting complementary bit lines and connecting them to the complementary common bit line 204. The column switch circuit is selectively operated according to the decoding result of the column address signal by the column decoder 203A.

A row decoder 201B, a sense amplifier / column selection circuit 202B, and a column decoder 203B are similarly provided on the memory array 200B side.

The complementary common bit line 204 is connected to the output terminal of the input buffer 210 and the input terminal of the output buffer 211. The input terminal of the input buffer 210 and the output terminal of the output buffer 211 are connected to 8-bit data input / output terminals I / O0 to I / O7.

The row address signal and the column address signal supplied from the address input terminals A0 to A11 are supplied to the column address buffer 205 and the row address buffer 206, respectively.
Are taken in in the address multiplex format. The supplied address signal is held in each buffer.
The row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal in the refresh operation mode. The output of the column address buffer 205 is supplied as preset data of the column address counter 207, and the column address counter 207 sequentially outputs the column address signal as the preset data or its column address signal according to the operation mode designated by the command. The incremented value is used by the column decoder 2
Output to 03A and 203B.

The control circuit 212 is not particularly limited, but the clock signal CLK, the clock enable signal CKE, the chip select signal bar CS, the column address strobe signal bar CAS, the row address strobe signal bar RAS, the write enable signal bar WE, and the data input. External control signals such as the output mask control signal DQM (not shown) and control data from the address input terminals A0 to A11 are supplied, and the operation mode of the SDRAM and the above-mentioned operation are based on the level change and timing of these signals. It forms an internal timing signal for controlling the operation of the circuit block, and includes a control logic (not shown) for that purpose and a mode register 30.

The clock signal CLK is used as the master clock of the SDRAM, and other external input signals are latched in synchronization with the rising edge of the internal clock signal CLK. The chip select signal bar CS instructs the start of the command input cycle by its low level. Bar RAS, bar CAS, and bar WE signals are normally D
It has a different function from the corresponding signal in the RAM and is a signal used when setting a command cycle.

The clock enable signal CKE is a signal indicating the validity of the next clock signal, and the signal C
If KE is at high level, the next rising edge of the clock signal CLK is valid, and if it is at low level, it is invalid. Further, although not shown, an external control signal for controlling the output enable for the output buffer 211 in the read mode is also included in the control circuit 212.
Is supplied to the output buffer 211, the output buffer 211 is placed in a high impedance state.

The row address signal is a clock signal C.
A0 to A in the bank active command cycle synchronized with the rising edge of LK (internal clock signal)
Defined by 10 levels. The input from A11 is regarded as a bank selection signal in the bank active command cycle. That is, when the input of A11 is low level, the memory bank BANKA is selected,
At the high level, the memory bank BANKB is selected. The memory bank selection control is not particularly limited,
This can be performed by activation of only the row decoder on the selected memory bank side, all deselection of column switch circuits on the non-selected memory bank side, connection to the input buffer 210 and output buffer 211 on the selected memory bank side only, and the like. .

A in the precharge command cycle
The input of 10 indicates the mode of the precharge operation for the complementary bit line and the like, the high level thereof indicates that the target of the precharge is both memory banks, and the low level thereof is one of the ones indicated by A11. Indicates that the memory bank is subject to precharge.

The column address signal is defined by the levels of A0 to A8 in a read or write command (column address read command, column address write command described later) cycle synchronized with the rising edge of the clock signal CLK (internal clock). To be done.
The column address thus defined is used as the start address for burst access.

The SDRAM has the following two refresh commands.

(1) Refresh command 1 This command is a command required to start the auto refresh, and is a bar CS, bar RAS,
Instructed by bar CAS = low level and bars WE and CKE = high level. This auto refresh command uses the two memory arrays 200A and 200B described above.
(Memory banks A and B) are simultaneously refreshed collectively.

(2) Refresh command 2 This command is a command required to start the auto refresh for each memory bank, and unlike the above command 1, for example, bar CS, bar R
AS, bar CAS = low level, bar WE, CKE = low level. In this auto refresh command, a specific bit of the mode register 30 is referenced. For example, if the specific bit is 0, the memory array 200A is refreshed, and the specific bit is 1.
Then, the memory array 200B is refreshed. In addition, for example, if the signal DQM is low level, the memory array 2
00A is refreshed, and if the signal DQM is at high level, the memory array 200B is refreshed.

In FIG. 7, only row-related addresses are selected in the refresh operation. That is, if the address signal generated by the refresh counter 208 is taken into the row address buffer 206 instead of the external address signal and the refresh command 1 as described above is input, the memory array 200
The selection operation of the A and 200B word lines and the amplification operation of the sense amplifier are performed. That is, the stored information of the dynamic memory cells connected to the selected word line in the two memory arrays 200A and 200B is sensed and amplified by the sense amplifier and rewritten (refresh) in the original memory cells. To be done. Alternatively, when the refresh command 2 as described above is input, the memory array 200A or 2 designated by the signal DQM or designated by the mode register 30 is input.
00B, one word line is selected and the sense amplifier is amplified.

In the refresh command 2, for example, when the memory array 200A (memory bank A) is refreshed, another memory array 200B (memory bank B) can be read / written by another command. To be For example, in the burst mode as described above, the memory array 200B
In (memory bank B), the word line selection operation has already been performed, and read / write is performed according to the address formed by the built-in column address counter 207.

The batch refresh operation of the plurality of memory banks and the refresh operation designating one to a plurality of memory banks among them are performed by a command designated by a combination of control signals.
The usability can be improved according to the interface of the synchronous DRAM.

The memory bank to be refreshed is specified in accordance with a refresh command by a combination of control signals by referring to memory bank specification information stored in a register in advance, so that various combinations of refresh operations can be performed. Can be realized with a simple configuration.

[0031]

As described above, while one memory bank is performing an access operation such as read / write, it is possible to perform auto or self-refresh in another memory bank. it can. However, the memory bank to be auto-refreshed must be set by setting the mode register, and
It did not indicate the bank to be self-refreshed or the procedure for ending self-refresh.

It is an object of the present invention to provide a method for efficiently designating a memory bank to be refreshed and a self refresh start and end procedure.

[0033]

SUMMARY OF THE INVENTION A synchronous semiconductor memory device according to the present invention includes a plurality of memory banks each independently having a memory access operation enabled, a plurality of the memory banks being collectively refreshed, and the above-mentioned memory banks being collectively refreshed. In a synchronous semiconductor memory device including a refresh control circuit capable of refreshing one to a plurality of memory banks among a plurality of memory banks, a chip select signal bar CS, in synchronization with a rising edge of a clock signal CLK,
The row address strobe signal bar RAS and the column address strobe signal bar CAS are set to the low level, and the write enable signal bar WE and the clock enable signal CK are set.
By setting E to high level, it is possible to specify the bank to be auto-refreshed by the address signal input at that time,
In synchronization with the rising of the clock signal CLK, the chip select signal bar CS, the row address strobe signal bar RAS, the column address strobe signal bar CAS, and the clock enable signal CKE are set to low level, and the write enable signal bar WE is set to high level. A bank to be self-refreshed can be specified by an address signal input, and when the row address input terminal or one of the other specific input terminals is at a high level, the plurality of memory banks are collectively refreshed or self-refreshed. However, when the row address input terminal or one of the other specific input terminals is at the low level, the plurality of memory banks are selected by the bank selection bit composed of one bit of the row address other than the above or a combination of a plurality of bits. One of the memory banks is designated for auto-refresh or self-refresh, and the chip select signal bar CS, the row address strobe signal bar RAS, and the write enable signal bar WE are set to the low level and the column address strobe is synchronized with the rising edge of the clock signal CLK. It is characterized in that the signal bar CAS and the clock enable signal CKE are set to a high level, and the address signal input at that time enables designation of a bank for ending the self-refresh. In the synchronous semiconductor memory device of the present invention, a plurality of memory banks each of which is independently enabled for memory access operation, a collective refresh of the plurality of memory banks, and one to one of the plurality of memory banks are provided. In a synchronous semiconductor memory device including a refresh control circuit that enables refresh with a plurality of memory banks specified, a chip select signal bar CS, a row address strobe signal bar RAS, and a column address are synchronized with a rising edge of a clock signal CLK. Strobe signal bar CA
S is set to a low level, write enable signal bar WE and clock enable signal CKE are set to a high level, and an address signal input at that time makes it possible to specify a bank to be auto-refreshed. The chip select signal is synchronized with the rising edge of clock signal CLK. Bar CS, row address strobe signal bar RAS, column address strobe signal bar CAS, and clock enable signal CK
E is set to low level, write enable signal bar WE is set to high level, the address signal input at that time enables the bank to be self-refreshed, and the row address input terminal or one of the other specific input terminals is set to high level. At the time, the plurality of memory banks are collectively auto-refreshed or self-refreshed, and when one of the row address input terminals or one of the other specific input terminals is at a low level, one bit or a plurality of row addresses other than the above are provided. Auto-refresh or self-refresh by designating one memory bank among the plurality of memory banks by a bank selection bit consisting of a combination of bits of the chip selection signal bar CS and row address in synchronization with the rising edge of the clock signal CLK. Strobe No. bar RAS, a column address strobe signal CAS, and a clock enable signal CK
It is characterized in that E is set to low level and the write enable signal bar WE is set to high level, and the address signal input at that time makes it possible to specify a bank for ending self-refresh.

Further, in the synchronous semiconductor memory device of the present invention, a plurality of memory banks each having a memory access operation enabled independently of each other, a plurality of the memory banks being collectively refreshed, and a plurality of the memory banks being composed of In a synchronous semiconductor memory device including a refresh control circuit that enables refreshing by designating one to a plurality of memory banks, a chip select signal bar CS and a row address strobe signal bar RAS are synchronized with a rising edge of a clock signal CLK. The column address strobe signal bar CAS is set to the low level, the write enable signal bar WE and the clock enable signal CKE are set to the high level, and the address signal input at that time makes it possible to specify the bank to be auto-refreshed. In synchronization with the above, the chip select signal bar CS, the row address strobe signal bar RAS, the column address strobe signal bar CAS and the clock enable signal CKE are set to the low level, and the write enable signal bar WE is set to the high level. A bank to be refreshed can be designated, and when the row address input terminal or one of the other specific input terminals is at a high level, the plurality of memory banks are collectively auto-refreshed or self-refreshed to set the row address. When the input terminal or one of the other specific input terminals is at the low level, one of the plurality of memory banks is selected by a bank selection bit composed of one bit of the row address other than the above or a combination of a plurality of bits. finger Then, the chip select signal bar CS, the row address strobe signal bar RAS, the column address strobe signal bar CAS, the write enable signal bar WE and the clock enable signal CKE are synchronized with the rising edge of the clock signal CLK. It is characterized in that the bank is set to the low level and the address of the address signal input at that time allows the bank to end the self-refresh. In the synchronous semiconductor memory device of the present invention, a plurality of memory banks each of which is independently enabled for memory access operation, a collective refresh of the plurality of memory banks, and one to one of the plurality of memory banks are provided. In a synchronous semiconductor memory device including a refresh control circuit that enables refresh with a plurality of memory banks specified, a chip select signal bar CS, a row address strobe signal bar RAS, and a column address are synchronized with a rising edge of a clock signal CLK. The strobe signal bar CAS is set to the low level, the write enable signal bar WE and the clock enable signal CKE are set to the high level, and it is possible to specify the bank to be automatically refreshed by the address signal input at that time, and in synchronization with the rising edge of the clock signal CLK. Chip select signal bar CS, a row address strobe signal bar RA
S, the column address strobe signal bar CAS and the clock enable signal CKE are set to the low level, and the write enable signal bar WE is set to the high level, and it is possible to specify the bank to be self-refreshed by the address signal input at that time. When one of the other specific input terminals is at the high level, the plurality of memory banks are collectively auto-refreshed or self-refreshed, and when the row address input terminal or one of the other specific input terminals is at the low level. Performs auto-refresh or self-refresh in which one of the plurality of memory banks is designated by a bank selection bit consisting of one bit of a row address other than the above or a combination of a plurality of bits, and the clock signal CLK In synchronization with rising, the chip select signal bar CS and the write enable signal bar WE are set to the low level, the row address strobe signal bar RAS, the column address strobe signal bar CAS and the clock enable signal CKE are set to the high level, and the address signal input at that time is input. It is possible to specify the bank to end the self refresh by.

According to such a synchronous semiconductor memory device of the present invention, for example, in a 16M synchronous DRAM,
When the chip select signal bar CS, the row address strobe signal bar RAS and the column address strobe signal bar CAS are low level, and the write enable signal bar WE and the clock enable signal CKE are high level,
The above signals and address input signals are decoded in the refresh control circuit, and the auto refresh of one row in each bank is executed. When A10 is high level,
Both of the two banks are refreshed, and when at the low level, only the bank selected by A11 is refreshed. That is, when A11 is low level, bank A is refreshed, and when A11 is high level, bank B is refreshed. Further, when the chip select signal bar CS, the row address strobe signal bar RAS, the column address strobe signal bar CAS and the clock enable signal CKE are at the low level and the write enable signal bar WE is at the high level, the above signals and the address input signal are inputted. Are decoded in the refresh control circuit, and self-refresh of each bank is executed. When A10 is high level, both banks are self-refreshed, and when A10 is low level,
Only the bank selected in A11 is self-refreshed. That is, when A11 is low level, bank A is self-refreshed, and when A11 is high level, bank B is self-refreshed.

Further, in the synchronous semiconductor memory device of the present invention, the chip select signal bar CS, the row address strobe signal bar RAS and the write enable signal bar WE are at the low level and the column address strobe signal is synchronized with the rising edge of the clock signal CLK. The bank CAS and the clock enable signal CKE are set to the high level, and the address signal input at that time allows the bank to end the self refresh. Alternatively, in synchronization with the rising edge of the clock signal CLK, the chip select signal bar CS, the row address strobe signal bar RAS,
The column address strobe signal bar CAS and the clock enable signal CKE are set to the low level, the write enable signal bar WE is set to the high level, and the address signal input at that time makes it possible to specify the bank in which the self-refresh is finished. Alternatively, the chip select signal bar CS, the row address strobe signal bar RAS, the column address strobe signal bar CAS, the write enable signal bar WE, and the clock enable signal CKE are set to the low level in synchronization with the rising edge of the clock signal CLK, and the address at that time is set. It is possible to specify the bank for ending the self-refresh by inputting a signal. Alternatively, the chip select signal bar CS and the write enable signal bar WE are set to low level and the row address strobe signal bar R is synchronized with the rising edge of the clock signal CLK.
The AS, the column address strobe signal CAS, and the clock enable signal CKE are set to the high level, and the address signal input at that time allows the bank to be designated to end the self-refresh.

[0037]

1 is a block diagram of a basic configuration of a synchronous DRAM according to the present invention. Compared with FIG. 7 which is a conventional technique, a self-refresh clock generation circuit 100 is added, and the other components are the same.

FIG. 2 is a timing chart showing an auto-refresh operation of the 16M synchronous DRAM according to the present invention.

At time t1, the chip select signal bar CS, the row address strobe signal bar RAS and the column address strobe signal bar CAS are at low level,
The high level of the write enable signal bar WE and the clock enable signal CKE means that the conventional JEDE
Similar to C standard. The above signals and address input signals are decoded in the control circuit 212, and one row of each memory bank is refreshed. A10
Is high, both banks are refreshed, and when low, only the bank selected by A11 is refreshed. That is, when A11 is low level, bank A is refreshed, and when A11 is high level, bank B is refreshed.

In FIG. 2, at time t1, A10 is at low level and A11 is at high level, so the bank B is refreshed. Further, at time t4, A10
The bank B can be refreshed by setting the low level to A11 and the high level to A11. Here, the interval T1 between the time t1 and the time t4 is a time interval required between the auto refresh operations, and it is necessary to be at least a minimum tRC (minimum delay time from the fall time of the bar RAS to the fall time of the bar CAS). Is.

In the present invention, in parallel with this, at time t2, row address strobe signal bar RAS is set to low level, column address strobe signal bar CAS is set to high level, and A11 is set to low level, and at time t3, row address strobe signal bar RAS is set. Is set to a high level, the column address strobe signal bar CAS is set to a low level, A11 is set to a low level, and necessary column addresses A10-A0 are input to execute a read operation for a certain column address in the bank A. At time t4 in FIG. 2, the read data from bank A is DQ.
It should be noted that the bank B auto-refresh command is being input at the same time that it is being output.

FIG. 3 is a timing chart showing the self-refresh operation of the 16M synchronous DRAM according to the present invention.

At time t5, the chip select signal bar CS, the row address strobe signal bar RAS, the column address strobe signal bar CAS and the clock enable signal CKE are set to the low level, and the write enable signal bar WE is set to the high level, so that the self The activation of refresh is similar to the JEDEC standard. The above signals and address signals are the control circuit 2
Decoded at 12, self-refresh of each memory bank is executed. When A10 is high level, both banks are self-refreshed,
At the low level, only the bank selected in A11 is self-refreshed. That is, when A11 is at the low level, bank A is self-refreshed and A
When 11 is at high level, bank B is self-refreshed. Self refresh clock generation circuit 10
The refresh counter 208 is incremented every refresh clock cycle from 0, and the corresponding row address of each bank is refreshed.

Further, according to the JEDEC standard, the clock enable signal CKE must be held at a low level during self refresh, but it is not necessary to hold it in the present invention. Of course, it is possible to hold CKE at a low level and enter the power down mode. However, in that case, command input is not possible for either bank.

In FIG. 3, at time t5, A10 is at low level and A11 is at high level, so the bank B is self-refreshed. In the present invention, in parallel with this, at the time t6, the clock enable signal CKE
High level, low address strobe signal bar RAS
Low level, column address strobe signal bar CA
S is set to high level, A11 is set to low level, necessary row addresses A10-A0 are input to activate a certain row address in bank A, and at time t7, the clock enable signal CKE is set to high level and row address. Strobe signal bar RAS is high level, column address strobe signal bar CAS is low level, A
11 is set to low level, and necessary column address A9-A
By inputting 0, the read operation is executed for a certain column address in bank A.

An example of the procedure for ending the self-refresh operation is as follows.

Similarly to the bank precharge command, the clock enable signal CKE and the column address strobe signal bar CAS are set to the high level, and the chip select signal bar CS and the row address strobe signal bar RA are set.
S, the write enable signal bar WE, and A10 are set to low level, and A11 is set to a level indicating a bank in self-refresh. In FIG. 3, A11 is set to the high level to complete the self refresh of bank B.

Besides this, the procedure for ending the self-refresh is carried out as follows. This will be described with reference to FIGS. 4 to 6.

In FIG. 4, the chip select signal bar CS, the row address strobe signal bar RAS, the column address strobe signal bar CAS, and the clock enable signal CKE are at the low level, and the write enable signal bar is the same as at the start of the self-refresh. WE is set to the high level, A10 is set to the low level, and A11 is set to the level indicating the bank in the self-refresh.

An example of the procedure for ending the self-refresh operation is as follows.

At time t8, the clock enable signal CKE, the chip select signal bar CS, the row address strobe signal bar RAS, and the column address strobe signal bar CAS are set to low level, the write enable signal bar WE is set to high level, and A10 is set to low level. A11 is set to the level indicating the bank in self refresh. In FIG. 4, A11 is set to the high level to end the self-refresh of bank B.

At time t8 in FIG. 5, similar to the mode register setting command, the chip select signal bar CS, the row address strobe signal bar RAS, the column address strobe signal bar CAS, the clock enable signal CKE and the write enable signal bar WE. Is set to a low level, A10 is set to a low level, and A11 is set to a level indicating a bank in self refresh. In FIG. 5, A
11 is set to the high level to complete the self refresh of bank B.

At time t8 in FIG. 6, as with the burst stop command, the chip select signal bar C
S and the write enable signal bar WE are set to low level, the row address strobe signal bar RAS, the column address strobe signal bar CAS, and the clock enable signal CKE are set to high level, A10 is set to low level, A
11 is set to the level indicating the bank being self-refreshed. In FIG. 6, A11 is set to the high level to complete the self-refresh of bank B.

In the above embodiments, various (auto, self) refresh operations are performed based on the row address, but similar refresh operations are performed based on the column address. Needless to say.

Further, although the above-mentioned embodiment implements the present invention in a synchronous semiconductor memory device having two memory banks, the present invention is a synchronous semiconductor memory device having three or more memory banks. It goes without saying that the same can be applied to the above. As a matter of course, in this case, 2 bits or more are required to specify the memory bank.

[0056]

As described above in detail, according to the present invention, the bank to be auto-refreshed need not be set by setting the mode register, and the designated bank can be auto-refreshed only by inputting the auto-refresh command. Yes, it is very efficient.

Further, by providing the self-refresh start command including the designation of the bank to be self-refreshed and the self-refresh end command including the designation of the bank to end the self-refresh, a flexible self-refresh operation which has never been realized is realized. It is possible.

Further, according to the present invention, each of the above refresh operations can be executed in one cycle.

[Brief description of drawings]

FIG. 1 is a schematic DRAM (S) to which the present invention is applied.
3 is a block diagram showing an embodiment of a DRAM).

FIG. 2 is a timing diagram illustrating an example of an auto refresh cycle of an SDRAM to which the present invention is applied.

FIG. 3 is a timing diagram illustrating an example of a self refresh cycle of an SDRAM to which the present invention is applied.

FIG. 4 is a timing diagram illustrating another example of the self-refresh cycle of the SDRAM to which the present invention is applied.

FIG. 5 is a timing diagram illustrating still another example of the self-refresh cycle of the SDRAM to which the present invention is applied.

FIG. 6 is a timing diagram illustrating still another example of the self-refresh cycle of the SDRAM to which the present invention is applied.

FIG. 7 is a block diagram showing a configuration example of a conventional SDRAM.

FIG. 8 is a timing diagram illustrating an example of a conventional SDRAM auto-refresh cycle.

FIG. 9 is a timing diagram illustrating an example of a self-refresh cycle of a conventional SDRAM.

[Explanation of symbols]

100 self-refresh clock generation circuit 200A memory bank A 200B memory bank B 212 control circuit

Claims (4)

(57) [Claims] 1. A plurality of memory banks each independently having a memory access operation enabled, a refresh collectively for the plurality of memory banks, and designation of one to a plurality of memory banks among the plurality of memory banks. In a synchronous semiconductor memory device having a refresh control circuit capable of refreshing, the chip select signal bar CS, the row address strobe signal bar RAS, and the column address strobe signal bar CAS are set to a low level in synchronization with the rising edge of the clock signal CLK. , The write enable signal bar WE and the clock enable signal CKE are set to the high level, the address signal input at that time enables the bank to be auto-refreshed, and the chip select signal bar is synchronized with the rising edge of the clock signal CLK. CS, row address strobe signal bar RAS, column address strobe signal bar CAS, and clock enable signal CKE are set to low level, and write enable signal bar WE is set to high level, and it is possible to specify a bank to be self-refreshed by the address signal input at that time. , When the row address input terminal or one of the other specific input terminals is at the high level, the plurality of memory banks are collectively auto-refreshed or self-refreshed, and the row address input terminal or the other specific input is When one of the terminals is at a low level, one bit of the row address other than the above or a bank selection bit consisting of a combination of a plurality of bits designates one of the plurality of memory banks for auto refresh or cell Refresh is performed, and the chip select signal bar CS, the row address strobe signal bar RAS and the write enable signal bar WE are at the low level, and the column address strobe signal bar CAS and the clock enable signal CKE are at the high level in synchronization with the rising edge of the clock signal CLK. A synchronous semiconductor memory device, wherein a bank for ending self-refresh can be designated by inputting an address signal at that time. 2. A plurality of memory banks each independently having a memory access operation enabled, a refresh for collectively performing the plurality of memory banks, and designating one to a plurality of memory banks among the plurality of memory banks. In a synchronous semiconductor memory device having a refresh control circuit capable of refreshing, the chip select signal bar CS, the row address strobe signal bar RAS, and the column address strobe signal bar CAS are set to a low level in synchronization with the rising edge of the clock signal CLK. , The write enable signal bar WE and the clock enable signal CKE are set to the high level, the address signal input at that time enables the bank to be auto-refreshed, and the chip select signal bar is synchronized with the rising edge of the clock signal CLK. CS, row address strobe signal bar RAS, column address strobe signal bar CAS, and clock enable signal CKE are set to low level, and write enable signal bar WE is set to high level, and it is possible to specify a bank to be self-refreshed by the address signal input at that time. , When the row address input terminal or one of the other specific input terminals is at the high level, the plurality of memory banks are collectively auto-refreshed or self-refreshed, and the row address input terminal or the other specific input is When one of the terminals is at a low level, one bit of the row address other than the above or a bank selection bit consisting of a combination of a plurality of bits designates one of the plurality of memory banks for auto refresh or cell Refreshing is performed, and the chip select signal bar CS, the row address strobe signal bar RAS, the column address strobe signal bar CAS and the clock enable signal CKE are at the low level and the write enable signal bar WE is at the high level in synchronization with the rising edge of the clock signal CLK. A synchronous semiconductor memory device, wherein a bank for ending self-refresh can be designated by inputting an address signal at that time. 3. A plurality of memory banks each independently having a memory access operation enabled, a refresh for collectively performing the plurality of memory banks, and designating one to a plurality of memory banks among the plurality of memory banks. In a synchronous semiconductor memory device having a refresh control circuit capable of refreshing, the chip select signal bar CS, the row address strobe signal bar RAS, and the column address strobe signal bar CAS are set to a low level in synchronization with the rising edge of the clock signal CLK. , The write enable signal bar WE and the clock enable signal CKE are set to the high level, the address signal input at that time enables the bank to be auto-refreshed, and the chip select signal bar is synchronized with the rising edge of the clock signal CLK. CS, row address strobe signal bar RAS, column address strobe signal bar CAS, and clock enable signal CKE are set to low level, and write enable signal bar WE is set to high level, and it is possible to specify a bank to be self-refreshed by the address signal input at that time. , When the row address input terminal or one of the other specific input terminals is at the high level, the plurality of memory banks are collectively auto-refreshed or self-refreshed, and the row address input terminal or the other specific input is When one of the terminals is at a low level, one bit of the row address other than the above or a bank selection bit consisting of a combination of a plurality of bits designates one of the plurality of memory banks for auto refresh or cell Refresh is performed, and the chip select signal bar CS, the row address strobe signal bar RAS, the column address strobe signal bar CAS, the write enable signal bar WE, and the clock enable signal CKE are set to the low level in synchronization with the rising of the clock signal CLK. A synchronous semiconductor memory device, wherein a bank for ending self-refreshing can be designated by inputting an address signal at the time. 4. A plurality of memory banks each independently allowing a memory access operation, a collective refresh of the plurality of memory banks, and designation of one to a plurality of memory banks among the plurality of memory banks. In a synchronous semiconductor memory device having a refresh control circuit capable of refreshing, the chip select signal bar CS, the row address strobe signal bar RAS, and the column address strobe signal bar CAS are set to a low level in synchronization with the rising edge of the clock signal CLK. , The write enable signal bar WE and the clock enable signal CKE are set to the high level, the address signal input at that time enables the bank to be auto-refreshed, and the chip select signal bar is synchronized with the rising edge of the clock signal CLK. CS, row address strobe signal bar RAS, column address strobe signal bar CAS, and clock enable signal CKE are set to low level, and write enable signal bar WE is set to high level, and it is possible to specify a bank to be self-refreshed by the address signal input at that time. , When the row address input terminal or one of the other specific input terminals is at the high level, the plurality of memory banks are collectively auto-refreshed or self-refreshed, and the row address input terminal or the other specific input is When one of the terminals is at a low level, one bit of the row address other than the above or a bank selection bit consisting of a combination of a plurality of bits designates one of the plurality of memory banks for auto refresh or cell Refresh is performed, and the chip select signal bar CS and the write enable signal bar WE are synchronized with the rising edge of the clock signal CLK.
Low level, row address strobe signal bar RA
A synchronous semiconductor memory device, wherein S, a column address strobe signal bar CAS, and a clock enable signal CKE are set to a high level, and a bank for ending self refresh can be designated by an address signal input at that time.