CN110825435A - Method and apparatus for processing data - Google Patents

Abstract

The embodiments of the present application disclose methods and apparatuses for processing data. A specific implementation of the method includes: obtaining the instruction to be executed, the instruction to be executed includes a data identifier; decoding the instruction to be executed to obtain the first address in the memory of the operand indicated by the data identifier; The first address is aligned with the data bit width to obtain the second address; the operand is read/written in the memory according to the second address. This embodiment improves the storage utilization of the memory.

Description

Method and apparatus for processing data

technical field

The embodiments of the present application relate to the field of computer technologies, and in particular, to methods and apparatuses for processing data.

Background technique

In recent years, with the rise and development of model algorithms represented by deep learning, neural network models have been widely used in various fields, such as speech recognition, image recognition, natural language processing and other fields. There are a large number of computationally intensive operators in neural network models, such as matrix computation, convolution, pooling, activation, normalization, and more. Since these operations are very time-consuming, the computing power of a traditional CPU (Central Processing Unit, central processing unit) cannot meet the requirements, so that heterogeneous computing becomes the mainstream. And as a result, various neural network dedicated processors have been developed, such as GPU (GraphicsProcessing Unit, graphics processor), FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), ASIC (Application Specific Integrated Circuits, application specific integrated circuit) ) and other special-purpose processors for neural networks.

At present, in general-purpose processors or processors for some computing-intensive features such as deep learning, the address of accessing memory has strong restrictions on software programmers. For example, when the bus data bit width is 64 bytes Under the setting of , the fetch address needs to be 64byte aligned. In the case of an unaligned address, the hardware will automatically ignore the unaligned part, return incorrect data, and report an interrupt exception to the software. In order to ensure the correctness of accessing data under the limitation of storage alignment, it is necessary to fill the irregular data structure with invalid data.

SUMMARY OF THE INVENTION

The embodiments of the present application propose methods and apparatuses for processing data.

In a first aspect, an embodiment of the present application provides a method for processing data, the method includes: obtaining an instruction to be executed, where the instruction to be executed includes a data identifier; decoding the instruction to be executed to obtain an operand indicated by the data identifier The first address in the memory; the first address is aligned according to the preset data bit width of the memory to obtain the second address; the operand is read/written in the memory according to the second address.

In some embodiments, after an alignment operation is performed on the first address according to a preset data bit width of the memory to obtain the second address, the method further includes: calculating shift information of the alignment operation.

In some embodiments, reading/writing the operand in the memory according to the second address includes: sending a data read request to the memory, the data read request including the second address; obtaining the data returned by the memory in response to receiving the data read request the first data; perform a shift operation on the first data according to the shift information to obtain an operand; and output the operand.

In some embodiments, performing a shift operation on the first data according to the shift information to obtain the operand includes: performing a shift operation on the first data according to the shift information to obtain the second data; according to a predefined data length of the operand Intercept the second data to obtain the operand.

In some embodiments, reading/writing the operand in the memory according to the second address includes: determining the valid bits of the data to be written indicated by the second address according to the first address and the data length of the pre-defined operand; Writes the data on the valid bits of the data to be written into memory.

In a second aspect, an embodiment of the present application provides an apparatus for processing data, the apparatus comprising: an acquisition unit configured to acquire an instruction to be executed, the instruction to be executed includes a data identifier; a decoding unit configured to be executed The instruction is decoded to obtain the first address in the memory of the operand indicated by the data identifier; the alignment unit is configured to perform an alignment operation on the first address according to the preset data bit width of the memory to obtain the second address; read A write unit configured to read/write the operand in the memory according to the second address.

In some embodiments, the apparatus further includes a calculation unit configured to calculate shift information for the alignment operation.

In some embodiments, the read/write unit includes: a sending subunit configured to send a data read request to the memory, the data read request including the second address; an obtaining subunit configured to obtain the memory in response to receiving the data The first data returned by the read request; the shift subunit is configured to perform a shift operation on the first data according to the shift information to obtain an operand; and the output subunit is configured to output the operand.

In some embodiments, the shift subunit is further configured to: perform a shift operation on the first data according to the shift information to obtain the second data; and truncate the second data according to the data length of the pre-defined operand to obtain the operand.

In some embodiments, the read-write unit includes: a determination sub-unit configured to determine the valid bits of the data to be written indicated by the second address according to the first address and the data length of the pre-defined operand; write The subunit is configured to write the data on the valid bits of the data to be written into the memory.

In a third aspect, embodiments of the present application provide an artificial intelligence chip, including: one or more processor cores; a storage device on which one or more programs are stored; when one or more programs are stored by one or more When executed by the processor cores, one or more processor cores are caused to implement the method described above in the first aspect.

In a fourth aspect, an embodiment of the present application provides a computer-readable medium on which a computer program is stored, and when the program is executed by an artificial intelligence chip, the method as described in the first aspect is implemented.

In a fifth aspect, an embodiment of the present application provides an electronic device, including: a processor, a storage device, and at least one artificial intelligence chip as described in the third aspect.

The method and device for processing data provided by the embodiments of the present application obtain the first address in the memory of the operand indicated by the data identifier by acquiring the instruction to be executed, and then decoding the instruction to be executed, and according to the preset The data bit width of the memory aligns the first address to obtain the second address, and finally reads/writes the operand in the memory according to the second address, thereby improving the storage utilization of the memory.

Description of drawings

Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG. 1 is an exemplary system architecture diagram to which an embodiment of the present application may be applied;

Figure 2 is a flowchart of one embodiment of a method for processing data according to the present application;

3A is a schematic diagram of a storage space whose starting address is the second address in the memory before writing the data to be written in an embodiment of the method for processing data according to the present application;

3B is a schematic diagram of data to be written whose starting address is the second address in an embodiment of the method for processing data according to the present application;

3C is a schematic diagram of a signal for indicating a valid bit in the data to be written in an embodiment of the method for processing data according to the present application;

3D is a schematic diagram of a storage space whose starting address is the second address in the memory after writing the data to be written in an embodiment of the method for processing data according to the present application;

Figure 4 is a flowchart of yet another embodiment of a method for processing data according to the present application;

5A is a schematic diagram of the first data in the storage space where the starting address returned by the memory is the second address in an embodiment of the method for processing data according to the present application;

5B is a schematic diagram of operands obtained by shifting and truncating operations in an embodiment of the method for processing data according to the present application;

6 is a schematic structural diagram of an embodiment of an apparatus for processing data according to the present application;

FIG. 7 is a schematic structural diagram of a computer system according to an embodiment of the electronic device of the present application.

Detailed ways

The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the related invention, but not to limit the invention. In addition, it should be noted that, for the convenience of description, only the parts related to the related invention are shown in the drawings.

It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

FIG. 1 illustrates an exemplary system architecture 100 to which embodiments of a method for processing data or an apparatus for processing data of the present application may be applied.

As shown in FIG. 1 , the system architecture 100 may include a CPU (Central Processing Unit, central processing unit) 101 , a bus 102 and an AI (Artificial Intelligence) chip 103 . The bus 102 is used as a medium for providing a communication link between the CPU 101 and the AI chip 103 . The bus 102 may include various bus types, such as a PCIE (peripheral component interconnect express) bus, an AMBA (Advanced Microcontroller Bus Architecture) bus, an OCP (Open Core Protocol) bus, and the like.

AI chip, that is, artificial intelligence chip, also known as AI accelerator or computing card, refers to a module dedicated to processing a large number of computing tasks in artificial intelligence applications (other non-computing tasks are still handled by the CPU). The computing requirements in AI computing are huge, especially complex computing requirements have a greater impact on computing performance. Although complex operations can be implemented with basic operation instructions, the execution efficiency of complex operations (such as floating-point square root operations, floating-point exponentiation operations, trigonometric function operations, etc.) will be reduced.

The AI chip 103 may include processor cores 1031 , 1032 , 1033 , a bus 1034 and a memory 1035 . The bus 1034 is used to provide the medium of communication links between the processor cores 1031 , 1032 , 1033 and the memory 1035 . The bus 1034 may include various bus types, such as a PCI bus, a PCIE bus, an AMBA bus supporting the Network On Chip protocol, an OCP bus, and other on-chip interconnect buses, and the like.

It should be noted that the method for processing data provided by the embodiments of the present application may be executed by the AI chip 103, and the corresponding apparatus for processing data may be provided in the AI chip.

It should be understood that the numbers of CPUs, buses, and AI chips in FIG. 1 are only illustrative. There can be any number of CPUs, buses, and AI chips according to implementation needs. Similarly, the numbers of processor cores, buses and memories in the AI chip 103 are only illustrative. According to implementation requirements, the AI chip 103 may have any number of processor cores, buses and memories. In addition, according to implementation requirements, the system architecture 100 may further include input devices (eg, mouse, keyboard, etc.), output devices (eg, display, speakers, etc.), input/output interfaces, and the like.

With continued reference to Figure 2, a flow 200 of one embodiment of a method for processing data according to the present application is shown. The method for processing data includes the following steps:

Step 201, acquiring the instruction to be executed.

In this embodiment, the method execution body for processing data (for example, the AI chip shown in FIG. 1 ) may first acquire the to-be-executed instruction, and the to-be-executed instruction includes a data identifier. The artificial intelligence chip may be communicatively connected with the CPU. As an example, the artificial intelligence chip may be communicatively connected with the CPU through PCIE to read instructions to be executed from the CPU. The instruction to be executed includes a data identifier, and the data identifier may be information that can identify an operand, such as a data name. An operand can be the data to be processed, such as data to be read or written.

Step 202: Decode the instruction to be executed to obtain the first address in the memory of the operand indicated by the data identifier.

In this embodiment, the above-mentioned execution body may decode the to-be-executed instruction obtained in step 201 to obtain the first address in the memory of the operand indicated by the data identifier, and the first address may be the operand when the operand is defined. assigned address. The first address may include the first address of the operand in the memory, or may include the address segment of the operand in the memory. When the first address is the first address of the operand in the memory, the storage space indicated by the first address may include the first address. An address is the storage space of the first address, and the size of the storage space can be preset or determined according to the length of the operand.

Here, the memory of the artificial intelligence chip may include at least one of the following: static random access memory (SRAM, Static Random-Access Memory), dynamic random access memory (DRAM, Dynamic RandomAccess Memory), and Flash memory (Flash Memory).

According to the storage level, the memory can be divided into: register, local memory (LM), shared memory (Share Memory, SM), global memory (Global Memory, GM), as an example, the operand indicated by the data identifier can be stored in Global Memory (GM).

Here, the above-mentioned execution body may select, from at least one processor core, a processor core that executes the to-be-executed instruction as a target processor core when the instruction to be executed is acquired. For example, the processor core that executes the instruction to be executed may be selected from at least one processor core as the target processor core according to the current working state of each processor core. For another example, the processor core that executes the instruction to be executed may be selected from at least one processor core as the target processor core in a polling manner.

In this way, the target processor core can decode the to-be-executed instruction to obtain the operation code and the address when the to-be-executed instruction is obtained. Decoding refers to splitting and interpreting the fetched instruction to be executed according to a predetermined instruction format. The opcode indicates the nature of the operation to be performed, that is, what to do, or what to do. The address is the address of the operand when the opcode is executed. When a computer executes a specified instruction, it must first analyze the operation code of the instruction to determine the nature and method of the operation, and then control the other components of the computer to cooperate to complete the function expressed by the instruction.

Step 203: Perform an alignment operation on the first address according to the preset data bit width of the memory to obtain the second address.

In this embodiment, the above-mentioned execution body may perform an alignment operation on the first address obtained in step 202 according to the preset data bit width of the memory to obtain the second address. The second address may also include the first address of the operand in the memory, and may also include the address segment of the operand in the memory.

The data bit width can be the amount of data that the memory can transmit at one time, that is, the data width that can be transmitted at one time. As an example, the global storage in the AI chip can use High Bandwidth Memory (HBM) technology, and the memory access interface can use the standard AXI (Advanced eXtensible Interface) bus protocol. Due to the characteristics of the HBM itself and the limitations of the AXI bus protocol, The address of accessing the memory has strong restrictions for software programmers. For example, when the data bit width of the AXI bus is 64 bytes, the address of accessing memory needs to be aligned with 64 bytes. Although the transmission granularity supported by the AXI bus protocol is 1 byte, under the same clock frequency, the data bit width is proportional to the memory access bandwidth. In order to improve the memory access bandwidth of the AI chip and avoid memory access bottlenecks, the AXI bus bit width is set to 64byte, thus causing the alignment limit of the fetch address.

Here, the alignment operation may be downward alignment, and the alignment operation is performed on the first address according to the preset data bit width of the memory, which may be to align the first address to the starting position of a data bit width before it, for example The first address 0x21000004 can be aligned to become the second address 0x21000000.

Step 204, read/write the operand in the memory according to the second address.

In this embodiment, the above-mentioned execution body may read/write the operand in the memory according to the second address obtained in step 203 . The execution body can read the data in the storage space indicated by the second address, or write the operand into the storage space indicated by the second address.

In some optional implementations of this embodiment, reading/writing the operand in the memory according to the second address includes: determining the to-be-written indicated by the second address according to the first address and the data length of the pre-defined operand Enter the valid bit of the data; write the data on the valid bit of the data to be written into the memory. As an example, in the AXI data channel transmission, the data on the valid bits in the data to be written may be written into the memory through the wstrb signal, and the wrtrb signal is used to indicate which are the valid bits of the data.

In this implementation manner, the data length of the operand may be determined when the operand is defined. As an example, the operand is an array A, the defined data type is floating point 32bit, the array length is 8, and the data length of the array A is 32bytes .

As shown in FIG. 3A , before the array A is written into the memory, the array C and the array B are stored in the storage space whose starting address is the second address in the memory. As shown in FIG. 3B , the operand in the data to be written whose starting address is the second address, that is, the starting address of the array A is actually the first address. According to the first address and the data length of the pre-defined operand, it can be determined The valid bit of the data to be written indicated by the second address, the signal used to indicate the valid bit may be as shown in FIG. 3C . Then, the data on the valid bits in the data to be written can be written into the memory, and the result after writing the operand array A in the storage space where the starting address of the memory is the second address is shown in FIG. 3D .

The method provided by the above-mentioned embodiments of the present application obtains the to-be-executed instruction, which includes a data identifier; decodes the to-be-executed instruction to obtain the first address in the memory of the operand indicated by the data identifier; according to the preset memory Aligning the first address to obtain the second address; reading/writing operands in the memory according to the second address, avoiding filling of invalid data and improving the storage utilization of the memory.

With further reference to Figure 4, a flow 400 of yet another embodiment of a method for processing data is shown. The flow 400 of the method for processing data includes the following steps:

In step 401, the instruction to be executed is obtained.

In this embodiment, the method execution body for processing data (for example, the AI chip shown in FIG. 1 ) may first acquire the to-be-executed instruction, and the to-be-executed instruction includes a data identifier.

Step 402: Decode the instruction to be executed to obtain the first address in the memory of the operand indicated by the data identifier.

In this embodiment, the above-mentioned execution body may decode the to-be-executed instruction obtained in step 401 to obtain the first address in the memory of the operand indicated by the data identifier.

Step 403: Perform an alignment operation on the first address according to the preset data bit width of the memory to obtain the second address.

In this embodiment, the above-mentioned execution body may perform an alignment operation on the first address obtained in step 402 according to the preset data bit width of the memory to obtain the second address.

Step 404, calculating the shift information of the alignment operation.

In this embodiment, the above-mentioned executive body may calculate the shift information of the alignment operation in step 403 . The shift information may include a shift number and a shift direction. As an example, aligning address 0x21000004 to 0x21000000, the shift number can be 4.

Step 405: Send a data read request to the memory, where the data read request includes the second address.

In this embodiment, the above-mentioned execution body may send a data read request to the memory, where the data read request includes the second address obtained in step 403 . Since the second address is an aligned address, the memory can return correct data according to the second address.

Step 406: Obtain the first data returned by the memory in response to receiving the data read request.

In this embodiment, the above-mentioned execution body may acquire the first data returned by the memory in response to receiving the data read request sent in step 405 . The required operands are included in the first data.

Step 407: Perform a shift operation on the first data according to the shift information to obtain an operand.

In this embodiment, the above-mentioned execution body may perform a shift operation on the first data according to the shift information calculated in step 404 to obtain an operand. Since the second address is the address after the alignment operation of the first address is performed, the data indicated by the second address is the data indicated by the first address after being shifted, that is, the data including the operand.

In some optional implementation manners of this embodiment, performing a shift operation on the first data according to the shift information to obtain the operand includes: performing a shift operation on the first data according to the shift information to obtain the second data; The data length of the operand intercepts the second data to obtain the operand. This implementation method intercepts the second data by the data length of the pre-defined operand to obtain the operand, which further improves the accuracy of the output operand, and the module that uses the memory to output the data can be used directly without further processing.

As an example, the first data in the storage space where the starting address returned by the memory is the second address is shown in FIG. 5A . For the first data, the shift operation is performed according to the shift information, and the data of the pre-defined operand is performed. The length is truncated to obtain the operand as shown in FIG. 5B .

Step 408, output the operand.

In this embodiment, the above-mentioned execution body may output the operand obtained in step 407 .

In this embodiment, the operations of step 401 , step 402 , and step 403 are basically the same as those of step 201 , step 202 , and step 203 , which will not be repeated here.

It can be seen from FIG. 4 that, compared with the embodiment corresponding to FIG. 2 , in the process 400 of the method for processing data in this embodiment, the shift information of the alignment operation is calculated, and the first The data is subjected to a shift operation. Therefore, in the solution described in this embodiment, a more precise operand is output, which is convenient for the module that reads the memory data to use the output operand.

Further referring to FIG. 6 , as an implementation of the methods shown in the above figures, the present application provides an embodiment of an apparatus for processing data. The apparatus embodiment corresponds to the method embodiment shown in FIG. 2 . The device can be specifically applied to various electronic devices.

As shown in FIG. 6 , the apparatus 600 for processing data in this embodiment includes: an acquisition unit 601 , a decoding unit 602 , an alignment unit 603 , and a read-write unit 604 . Wherein, the obtaining unit is configured to obtain the instruction to be executed, and the instruction to be executed includes a data identifier; the decoding unit is configured to decode the instruction to be executed to obtain the first address of the operand indicated by the data identifier in the memory; The alignment unit is configured to perform an alignment operation on the first address according to the preset data bit width of the memory to obtain the second address; the read-write unit is configured to read/write the operand in the memory according to the second address.

In this embodiment, for the specific processing of the acquiring unit 601 , the decoding unit 602 , the aligning unit 603 , and the reading and writing unit 604 of the apparatus 600 for processing data, reference may be made to steps 201 , 202 and 202 in the corresponding embodiment of FIG. 2 203 and step 204.

In some optional implementations of this embodiment, the apparatus further includes: a calculation unit configured to calculate the shift information of the alignment operation.

In some optional implementations of this embodiment, the read/write unit includes: a sending subunit, configured to send a data read request to the memory, where the data read request includes a second address; an obtaining subunit, configured to obtain The memory responds to receiving the first data returned by the data read request; the shift subunit is configured to perform a shift operation on the first data according to the shift information to obtain an operand; and the output subunit is configured to output the operand.

In some optional implementations of this embodiment, the shift subunit is further configured to: perform a shift operation on the first data according to the shift information to obtain the second data; intercept the first data according to the data length of the pre-defined operand Two data get operand.

In some optional implementations of this embodiment, the read/write unit includes: a determination subunit, configured to determine the to-be-written data indicated by the second address according to the first address and the data length of the pre-defined operand The valid bit of ; the writing subunit is configured to write the data on the valid bit in the data to be written into the memory.

In the device provided by the above-mentioned embodiments of the present application, the to-be-executed instruction is obtained by acquiring the to-be-executed instruction, which includes a data identifier; the to-be-executed instruction is decoded to obtain the first address in the memory of the operand indicated by the data identifier; The data bit width of the memory is used to align the first address to obtain the second address; the operand is read/written in the memory according to the second address, which improves the storage utilization of the memory.

The embodiments of the present application also provide an electronic device. For the structure of the electronic device, reference may be made to FIG. 7 , which shows a schematic structural diagram of a computer system 700 of an embodiment of the electronic device of the present application. The electronic device shown in FIG. 7 is only an example, and should not impose any limitations on the functions and scope of use of the embodiments of the present application.

As shown in FIG. 7 , the computer system 700 includes one or more central processing units (CPUs) 701 and one or more artificial intelligence chips 704 . The CPU 701 can execute various appropriate actions and processes according to a program stored in a read only memory (ROM) 702 or a program loaded from a storage section 707 into a random access memory (RAM) 703 . The artificial intelligence chip 704 includes one or more general-purpose execution units and one or more dedicated execution units, and the artificial intelligence chip 704 can execute various appropriate actions and processes according to the program received from the CPU 701 . In the RAM 703, various programs and data necessary for the operation of the system 700 are also stored. The CPU 701 , the ROM 702 , the RAM 703 , and the artificial intelligence chip 704 are connected to each other through a bus 705 . An input/output (I/O) interface 706 is also connected to bus 705 .

The following components are connected to the I/O interface 706: a storage section 707 including a hard disk and the like; and a communication section 708 including a network interface card such as a LAN card, a modem, and the like. The communication section 708 performs communication processing via a network such as the Internet. A driver 709 is also connected to the I/O interface 706 as needed. A removable medium 710, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is mounted on the drive 709 as needed so that a computer program read therefrom is installed into the storage section 707 as needed.

In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the method illustrated in the flowchart. In such an embodiment, the computer program may be downloaded and installed from the network via the communication portion 708 and/or installed from the removable medium 710 . When the computer program is executed by the general execution component of the artificial intelligence chip 704, the above-mentioned functions defined in the method of the present application are executed.

It should be noted that the computer-readable medium described in this application may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the above two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or a combination of any of the above. More specific examples of computer readable storage media may include, but are not limited to, electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable Programmable read only memory (EPROM or flash memory), fiber optics, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. In this application, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, however, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code therein. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device . Program code embodied on a computer readable medium may be transmitted using any suitable medium including, but not limited to, wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for performing the operations of the present application may be written in one or more programming languages, including object-oriented programming languages—such as Java, Smalltalk, C++, but also conventional procedural programming language - such as "C" language or similar programming language. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (eg, using an Internet service provider through Internet connection).

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more logical functions for implementing the specified functions executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It is also noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented in dedicated hardware-based systems that perform the specified functions or operations , or can be implemented in a combination of dedicated hardware and computer instructions.

The units involved in the embodiments of the present application may be implemented in a software manner, and may also be implemented in a hardware manner. The described unit can also be provided in the AI chip, for example, it can be described as: an AI chip includes an acquisition unit, a decoding unit, an alignment unit and a read/write unit. Wherein, the names of these units do not constitute a limitation on the unit itself in some cases, for example, the obtaining unit may also be described as "a unit configured to obtain the instruction to be executed".

As another aspect, the present application also provides a computer-readable medium. The computer-readable medium may be included in the AI chip described in the above embodiments; it may also exist alone without being assembled into the AI chip. middle. The above-mentioned computer-readable medium carries one or more programs, and when the above-mentioned one or more programs are executed by the AI chip, the AI chip: obtains the instruction to be executed, and the instruction to be executed includes a data identifier; decodes the instruction to be executed , obtain the first address in the memory of the operand indicated by the data identifier; perform an alignment operation on the first address according to the preset data bit width of the memory to obtain the second address; read/write operation in the memory according to the second address number.

The above description is only a preferred embodiment of the present application and an illustration of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solution formed by the specific combination of the above technical features, and should also cover the above technical features or Other technical solutions formed by any combination of its equivalent features. For example, a technical solution is formed by replacing the above-mentioned features with the technical features disclosed in this application (but not limited to) with similar functions.

Claims (13)

1. A method for processing data, comprising:

acquiring an instruction to be executed, wherein the instruction to be executed comprises a data identifier;

decoding the instruction to be executed to obtain a first address of an operand indicated by the data identifier in a memory;

aligning the first address according to a preset data bit width of the memory to obtain a second address;

reading/writing the operand in the memory according to the second address.

2. The method according to claim 1, wherein after performing an alignment operation on the first address according to a preset data bit width of the memory to obtain a second address, the method further comprises:

shift information of the alignment operation is calculated.

3. The method of claim 2, wherein said reading/writing the operand in the memory according to the second address comprises:

sending a data read request to the memory, the data read request including the second address;

acquiring first data returned by the memory in response to the received data reading request;

performing a shift operation on the first data according to the shift information to obtain the operand;

and outputting the operand.

4. The method of claim 3, wherein the shifting the first data according to the shift information to obtain the operand comprises:

shifting the first data according to the shifting information to obtain second data;

and intercepting the second data according to the predefined data length of the operand to obtain the operand.

5. The method of any of claims 1-4, wherein the reading/writing the operand in the memory according to the second address comprises:

determining the effective bit of the data to be written, which is indicated by the second address, according to the first address and the predefined data length of the operand;

and writing the data on the effective bits in the data to be written into the memory.

6. An apparatus for processing data, comprising:

the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is configured to acquire an instruction to be executed, and the instruction to be executed comprises a data identifier;

the decoding unit is configured to decode the instruction to be executed to obtain a first address of an operand indicated by the data identifier in a memory;

the alignment unit is configured to perform alignment operation on the first address according to a preset data bit width of the memory to obtain a second address;

a read/write unit configured to read/write the operand in the memory according to the second address.

7. The apparatus of claim 6, wherein the apparatus further comprises:

a calculation unit configured to calculate shift information of the alignment operation.

8. The apparatus of claim 7, wherein the read-write unit comprises:

a sending subunit configured to send a data read request to the memory, the data read request including the second address;

a fetch subunit configured to fetch first data returned by the memory in response to receiving the data read request;

a shift subunit configured to shift the first data according to the shift information to obtain the operand;

an output subunit configured to output the operand.

9. The apparatus of claim 8, wherein the shifting subunit is further configured to:

shifting the first data according to the shifting information to obtain second data;

and intercepting the second data according to the predefined data length of the operand to obtain the operand.

10. The apparatus according to any of claims 6-9, wherein the read-write unit comprises:

a determining subunit configured to determine, according to the first address and a predefined data length of the operand, valid bits of data to be written indicated by the second address;

a write subunit configured to write data on valid bits in the data to be written into the memory.

11. An artificial intelligence chip comprising:

one or more processor cores;

a storage device having one or more programs stored thereon;

the one or more programs, when executed by the one or more processor cores, cause the one or more processor cores to implement the method of any of claims 1-5.

12. A computer-readable medium, on which a computer program is stored which, when executed by an artificial intelligence chip, carries out the method according to any one of claims 1 to 5.

13. An electronic device, comprising: a processor, a memory device, and at least one artificial intelligence chip as recited in claim 11.

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