EP3959717A4 - SYSTEMS AND METHODS FOR RECONFIGURING DUAL-PURPOSE CELL NETWORKS - Google Patents

SYSTEMS AND METHODS FOR RECONFIGURING DUAL-PURPOSE CELL NETWORKS Download PDF

Info

Publication number
EP3959717A4
EP3959717A4 EP20796232.5A EP20796232A EP3959717A4 EP 3959717 A4 EP3959717 A4 EP 3959717A4 EP 20796232 A EP20796232 A EP 20796232A EP 3959717 A4 EP3959717 A4 EP 3959717A4
Authority
EP
European Patent Office
Prior art keywords
reconfiguring
dual
systems
methods
cell networks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20796232.5A
Other languages
German (de)
French (fr)
Other versions
EP3959717A1 (en
Inventor
Darrel James Guzy
Wei-Ti Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arbor Co LLP
Original Assignee
Arbor Co LLP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/810,779 external-priority patent/US10802735B1/en
Application filed by Arbor Co LLP filed Critical Arbor Co LLP
Publication of EP3959717A1 publication Critical patent/EP3959717A1/en
Publication of EP3959717A4 publication Critical patent/EP3959717A4/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/046—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using non-volatile storage elements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Memory System (AREA)
  • Immobilizing And Processing Of Enzymes And Microorganisms (AREA)
  • Meat, Egg Or Seafood Products (AREA)
  • Apparatus Associated With Microorganisms And Enzymes (AREA)
EP20796232.5A 2019-04-23 2020-04-20 SYSTEMS AND METHODS FOR RECONFIGURING DUAL-PURPOSE CELL NETWORKS Pending EP3959717A4 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962837704P 2019-04-23 2019-04-23
US202016777554A 2020-01-30 2020-01-30
US16/810,779 US10802735B1 (en) 2019-04-23 2020-03-05 Systems and methods for reconfiguring dual-function cell arrays
PCT/US2020/029010 WO2020219397A1 (en) 2019-04-23 2020-04-20 Systems and methods for reconfiguring dual-function cell arrays

Publications (2)

Publication Number Publication Date
EP3959717A1 EP3959717A1 (en) 2022-03-02
EP3959717A4 true EP3959717A4 (en) 2023-05-31

Family

ID=72941358

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20796232.5A Pending EP3959717A4 (en) 2019-04-23 2020-04-20 SYSTEMS AND METHODS FOR RECONFIGURING DUAL-PURPOSE CELL NETWORKS

Country Status (5)

Country Link
EP (1) EP3959717A4 (en)
JP (1) JP7064060B1 (en)
KR (1) KR102440799B1 (en)
CN (1) CN114341986B (en)
WO (1) WO2020219397A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120039142A1 (en) * 2008-06-10 2012-02-16 Philip Pan Scaleable look-up table based memory
US20190114138A1 (en) * 2016-05-06 2019-04-18 HangZhou HaiCun Information Technology Co., Ltd. Configurable Processor with In-Package Look-Up Table

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784313A (en) * 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US5737766A (en) * 1996-02-14 1998-04-07 Hewlett Packard Company Programmable gate array configuration memory which allows sharing with user memory
US6029236A (en) * 1997-01-28 2000-02-22 Altera Corporation Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM
US5940852A (en) * 1997-05-01 1999-08-17 Altera Corporation Memory cells configurable as CAM or RAM in programmable logic devices
JP2000284945A (en) * 1999-03-29 2000-10-13 Sharp Corp Digital device and its development method
US7126214B2 (en) 2001-12-05 2006-10-24 Arbor Company Llp Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US6952573B2 (en) * 2003-09-17 2005-10-04 Motorola, Inc. Wireless receiver with stacked, single chip architecture
US7242218B2 (en) * 2004-12-02 2007-07-10 Altera Corporation Techniques for combining volatile and non-volatile programmable logic on an integrated circuit
US7493519B2 (en) * 2005-10-24 2009-02-17 Lsi Corporation RRAM memory error emulation
US8677374B2 (en) * 2011-09-14 2014-03-18 International Business Machines Corporation Resource management in a virtualized environment
KR101920719B1 (en) * 2012-11-19 2019-02-13 삼성전자주식회사 Logic device, digital filter including the same, and method to control the same
US9972368B2 (en) * 2016-09-30 2018-05-15 Altera Corporation Circuitry for reducing leakage current in configuration memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120039142A1 (en) * 2008-06-10 2012-02-16 Philip Pan Scaleable look-up table based memory
US20190114138A1 (en) * 2016-05-06 2019-04-18 HangZhou HaiCun Information Technology Co., Ltd. Configurable Processor with In-Package Look-Up Table

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2020219397A1 *

Also Published As

Publication number Publication date
WO2020219397A1 (en) 2020-10-29
KR20220022120A (en) 2022-02-24
JP2022525557A (en) 2022-05-17
CN114341986A (en) 2022-04-12
KR102440799B1 (en) 2022-09-06
CN114341986B (en) 2023-03-28
JP7064060B1 (en) 2022-05-09
EP3959717A1 (en) 2022-03-02

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