CN102244061A - Low-k chip package structure - Google Patents

Abstract

The invention relates to a Low-k chip packaging structure, which belongs to the technical field of chip packaging. It includes chip body I (2-1), chip electrode (2-2) and chip surface passivation layer (2-3), chip body I (2-1) is covered with thin film layer I (2-4) , the film layer I (2-4) is provided with a support wafer (2-5) on the back, and the chip electrodes (2-2) are transferred to the film layer I (2 -4), the metal post (2-7) is arranged at the terminal of the redistribution metal trace (2-6), and the metal post (2-7) is covered with a film layer II (2-8), and the metal post ( 2-7) Thin film layer II (2-8) is exposed at the top, a metal layer (2-9) is arranged on the top of the exposed metal pillar (2-7), and a solder ball (2-9) is arranged on the metal layer (2-9) -10). The Low-k chip packaging structure of the present invention solves the problem that the Low-k chip fails due to stress concentration in the chip packaging process, and has low packaging cost and high product reliability.

Description

Low-k chip package structure

technical field

The invention relates to a Low-k chip packaging structure, which belongs to the technical field of chip packaging.

Background technique

In the semiconductor manufacturing industry, Moore's Law has always been the driving force for the industry to move forward, and Intel has contributed a lot in this regard. The chip line width node is mainly divided into several stages: the 0.18μm stage, when MOS tubes began to be popular, is the initial stage of the semiconductor manufacturing process, and the size of the manufactured chip is relatively large; the 0.13μm stage, people are full of confidence in the semiconductor manufacturing process, It is hoped that the chip area and cost will be reduced by reducing the feature size; these two stages are what we often call the micron process stage. With the development of nanotechnology, people's eyes are far beyond micron technology, and they have begun to advance semiconductor manufacturing processes to the nanometer scale. The initial nanometer was supported by 90nm, but as the number of dies per unit area increases exponentially according to Moore's Law , 65 nanometers, 45 nanometers, 32 nanometers and the current 22 nanometers technology have appeared successively. This sharp reduction in feature size has led to the pursuit of low dielectric loss constant (usually called Low-k) for dielectric materials to reduce the size of the circuit. The parasitic resistance, capacitance and inductance of the structure, while ensuring that the line has good insulation performance. Usually, the choice of low-k material is a porous material, which makes the material relatively brittle and easily cracks under the condition of applied stress, causing circuit failure.

Due to the fragile nature of low-k materials, the packaging process and structure of the chip need to be improved accordingly to meet the needs of product applications. Currently, the packaging for low-k products is still the usual flip-chip structure or wire bonding, resulting in packaging Yield losses were high, and failure analysis structures all pointed to dielectric layer fragmentation under bonding electrodes (both wire and flip-chip bonding). At present, the usual solution is to use flip-chip bonding for wire bonding packaging, and at the same time, apply non-fluid underfill glue on the substrate before flip-chip bonding. The chip packaging structure is shown in Figure 1. The bottom The filler glue has both the properties of ordinary underfill glue and the properties of reflow solder, so that wetting can be formed between the solder ball and the substrate pad. For the problem of damage to the internal dielectric layer, the reflow stress is redistributed through the non-flowing underfill glue, so that the internal dielectric layer of the chip will not be damaged due to stress concentration. However, the biggest disadvantage of this method is that the wetting effect of the solder is not strong due to the existence of the underfill glue, and it is impossible to ensure that each solder ball is well bonded to the pad, and the underfill glue is likely to be cured due to the existence of the flux and the reflow process. Holes appear in the process.

To sum up, in the packaging process of Low-k chips, there are currently two main problems:

1. Using wire bonding and conventional flip-chip technology, because the process stress leads to stress concentration at the electrode of the chip, and then breaks the fragile Low-K dielectric layer, resulting in chip failure;

2. The flip-chip process using non-fluid underfill has poor soldering and colloid void defects after curing, resulting in low product reliability.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned shortcomings, provide a Low-k chip packaging structure and packaging method, which can solve the problem of Low-k chip failure caused by stress concentration in the chip packaging process, and provide a low-cost packaging solution for Low-K chip packaging plan.

The object of the present invention is achieved like this: a kind of Low-k chip encapsulation structure, it comprises chip body 1, chip electrode and chip surface passivation layer, and described chip body 1 is coated with film layer 1 outside, and described film layer The back of I is provided with a support wafer, and the chip electrodes are transferred to the film layer I outside the periphery of the chip through the re-wiring metal lines, and the terminals of the re-wiring metal lines are provided with metal posts, and the metal posts are covered with a film Layer II, the thin film layer II is exposed at the top of the metal pillar, and a metal layer is arranged on the exposed top of the metal pillar, and solder balls are arranged on the metal layer.

The metal pillar is made of conductive metal such as copper and nickel, and its height is between 50 μm and 100 μm.

The metal layer is a multilayer metal with a structure of Ni/Au or Ni/Pd/Au, and the thickness of the metal layer is not more than 5 μm.

A chip body II is also embedded in the thin film layer I.

The redistribution metal traces are composed of metal wiring layer I and metal wiring layer II.

The film layer I and film layer II are made of non-photosensitive materials.

The supporting wafer is a silicon wafer or a metal wafer.

The original carrier sheet adopts a silicon substrate or a glass substrate.

Compared with prior art, the beneficial effect of the present invention is:

1. The chip is directly flipped on the carrier wafer without going through the reflow process, and there is no stress concentration experience, which solves the problem of chip failure caused by the stress concentration of the flip chip process in the current Low-k chip BGA package;

2. Using the wafer-level process to extend the chip electrodes to the non-chip area through rewiring, the stress generated by the BGA structure mounting process is transferred, and the chip area is in a stress-free state;

3. Utilize the technology and structure of metal pillars to realize high-power current carrying and uniform distribution of current. At the same time, the height of copper pillars is used to buffer the stress from BGA solder balls so that they do not reach the rewiring layer.

4. Combining wafer-level packaging technology and metal pillar technology, while realizing high-reliability packaging of Low-k chips, it can also achieve low-cost packaging;

5. The use of film sticking technology to replace the existing encapsulation technology reduces the requirements of the encapsulation process for equipment;

6. Integrating bump technology, flip chip technology and substrate technology, realizing the wafer manufacturing process of BGA packaging.

Description of drawings

FIG. 1 is a schematic diagram of a current Low-k chip packaging structure.

FIG. 2 is a schematic diagram of Embodiment 1 of the Low-k chip packaging structure of the present invention.

FIG. 3 is a schematic diagram of Embodiment 2 of the Low-k chip packaging structure of the present invention.

FIG. 4 is a schematic diagram of Embodiment 3 of the Low-k chip packaging structure of the present invention.

in:

Chip body 1-1

Chip electrode 1-2

Surface passivation layer 1-3

UBM 1-4

Solder bumps 1-5

Substrate 1-6

Substrate pad I1-7

Low filler glue 1-8

Substrate pads II1-9

BGA solder balls 1-10

Chip body I2-1

Chip electrodes 2-2

Chip surface passivation layer 2-3

Thin film layer I2-4

Support disc 2-5

Rerouting metal traces 2-6

Metal Post 2-7

Thin film layer II2-8

Metal layers 2-9

Solder balls 2-10

Chip body II2-11

Dielectric layer 2-12

Metal wiring layer I2-6-1

Metal wiring layer II2-6-2.

Detailed ways

Referring to Fig. 2, a kind of Low-k chip package structure of the present invention, it comprises chip body I2-1, chip electrode 2-2 and chip surface passivation layer 2-3, and described chip body I2-1 is covered with thin film Layer I2-4, the back of the thin film layer I2-4 is bonded with a support wafer 2-5, and the chip electrode 2-2 is transferred to the thin film layer I2- 4, a metal column 2-7 is provided at the terminal of the redistribution metal line 2-6, the metal column 2-7 is covered with a film layer II2-8, and the top of the metal column 2-7 exposes the film layer II2- 8. A metal layer 2-9 is disposed on the top of the exposed metal pillar 2-7, and a solder ball 2-10 is disposed on the metal layer 2-9.

Referring to FIG. 3 , a chip body II2-11 is also embedded in the thin film layer I2-4.

Referring to FIG. 4 , the redistribution metal trace 2-6 is composed of a metal wiring layer I2-6-1 and a metal wiring layer II2-6-2.

The realization process of the Low-k chip packaging structure of the present invention is as follows:

Step 1. Take a Low-k wafer and cut the Low-k wafer into individual chips.

Step 2: preparing a carrier wafer, forming an alignment mark on the carrier wafer by photolithography, and completing the graphic layout on the carrier wafer.

The carrier wafer can be made of a silicon substrate or a glass substrate, which facilitates subsequent chip flip-chip formation for the purpose of forming an alignment mark, so that the chip can be guaranteed to be in an ideal position.

Step 3: Paste a layer of temporary peeling film on the carrier wafer, and flip-pack the single chips cut in step 1 on the carrier wafer with the temporary peeling film attached.

Both sides of the temporary peeling film are sticky, and can form a good connection with the carrier wafer and the subsequent flip chip. The peeling film has thermal peeling properties or UV light peeling properties. If it is UV light peeling properties, it needs to use The carrier wafer of glass substrate or quartz substrate needs to be irradiated with UV light because of UV light stripping, so it is necessary to choose a transparent substrate to realize the transmission of UV light.

There are two purposes for flip chip selection. On the one hand, it is to ensure that the front of the chip with different thicknesses is on the same plane in the subsequent process. craft.

Step 4: Paste the thin film layer I2-4 on the carrier wafer that has completed the chip flip-chip for encapsulation, bond the support wafer 2-5 to the thin film layer I2-4 during the encapsulation process, and then cure the thin film layer I2 -4, forming a reconstituted wafer consisting of chips, thin film layers I2-4 and support wafers 2-5.

The supporting wafer 2-5 is a silicon wafer or a metal wafer. When encapsulating, the good fluidity of the film layer I2-4 under heating is used to ensure the smoothness of the wafer surface.

Step 5, peel off the reconstituted wafer from the carrier wafer by UV irradiation or thermal peeling, and clean the chip surface of the reconstituted wafer to expose the chip electrodes 2-2.

Step 6. Complete single-layer or multi-layer rewiring metal traces 2-6 on the film layer I2-4 and the surface of the chip through wafer-level process photolithography, sputtering or electroplating, etc., and redistribute the metal traces 2-6 6 Guide the chip electrode 2-2 to the peripheral area of the chip (excluding the chip area).

Step 7, forming metal pillars 2-7 at the terminals of the completed redistribution metal traces 2-6 by means of photolithography or electroplating.

The metal pillars 2-7 are conductive metals such as copper and nickel, and the height of the metal pillars 2-7 can be adjusted according to structural requirements, and the height should not be less than 50 μm, usually between 50 μm and 100 μm. The metal pillars 2-7 have two functions here. One is to reduce the current crowding effect, so that the current can be evenly distributed, thereby reducing the occurrence of electromigration; Stress from solder balls 2-10 to protect the Low-k chip.

Step 8: Paste the thin film layer II2-8 on the surface of the reconstructed wafer forming the metal pillars 2-7 for encapsulation and curing, and then use laser ablation to etch the thin film material on the top of the metal pillars to form the metal pillars The complete or partial opening of 2-7 exposes the film layer II2-8 at the top of the metal post.

The film layer I2-4 and the film layer II2-8 are non-photosensitive resin insulating materials.

Step 9, coating the metal layer 2-9 on the top of the metal pillar 2-7 exposing the film layer II2-8.

The metal layer 2-9 is a single-layer or multi-layer metal, and the usual structure is Ni/Au or Ni/Pd/Au. The thickness of the metal layer 2-9 should not exceed 5 μm, and its purpose is to block tin and copper in the solder The mutual diffusion between them improves the reliability of the product.

Step 10: Form BGA solder balls 2-10 on the metal layer 2-9 by printing or ball planting, and finally cut the reconstituted wafer with BGA solder balls into single BGA packages.

Claims (8)

1. Low-k chip-packaging structure, it is characterized in that: it comprises chip body I(2-1), chip electrode (2-2) and chip surface passivation layer (2-3), described chip body I(2-1) is coated with thin layer I(2-4), described thin layer I(2-4) back side is provided with and supports disk (2-5), described chip electrode (2-2) is transferred to the outer thin layer I(2-4 of chip periphery via wiring metal cabling (2-6) again) on, the terminal of wiring metal cabling (2-6) is provided with metal column (2-7) again, described metal column (2-7) is coated with thin layer II(2-8), thin layer II(2-8 is exposed on metal column (2-7) top), be provided with metal level (2-9) on the metal column that exposes (2-7) top, described metal level (2-9) is provided with soldered ball (2-10).

2. a kind of Low-k chip-packaging structure according to claim 1 is characterized in that: described metal column (2-7) adopts conducting metals such as copper, copper/nickel, and its height is between 50 μ m ~ 100 μ m.

3. a kind of Low-k chip-packaging structure according to claim 1 and 2 is characterized in that: described metal level (2-9) is a multiple layer metal, and its structure is Ni/Au or Ni/Pd/Au, and the thickness of metal level (2-9) is no more than 5 μ m.

4. a kind of Low-k chip-packaging structure according to claim 1 and 2 is characterized in that: also be equipped with chip body II(2-11 described thin layer I(2-4)).

5. a kind of Low-k chip-packaging structure according to claim 1 and 2 is characterized in that: the described cabling of wiring metal again (2-6) is by metal wiring layer I(2-6-1) and metal wiring layer II(2-6-2) form.

6. a kind of Low-k chip-packaging structure according to claim 1 and 2 is characterized in that: described thin layer I(2-4) and thin layer II(2-8) adopt the non-photosensitivity material.

7. a kind of Low-k chip-packaging structure according to claim 1 and 2 is characterized in that: described support disk (2-5) is silicon chip or sheet metal.

8. a kind of Low-k chip-packaging structure according to claim 1 and 2 is characterized in that: former of described carrier adopts silicon substrate or glass baseplate.

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