CN101044450A - Processor - Google Patents

Abstract

There is provided a processor capable of performing operation with a high operation frequency by reducing the delay generated between a memory and a register file. The processor (100) includes a register file (110) having a plurality of registers and a tag value generation circuit (102) for generating a tag value indicating the data attribute. Each of the registers has a data filed (112) for holding data and a tag field (111) for holding a tag value. When executing a load instruction for loading data into the register of the register file (110) from the memory (14), the tag generation circuit (102) generates a tag value according to the load instruction and stores it in the tag field (111).

Description

processor

technical field

The present invention relates to a processor capable of operating at a high operating frequency, and more particularly to a processor capable of increasing the operating frequency.

Background technique

There is now a processor that, when executing a load instruction, stores the data output from the memory after performing data transformation such as configuration change, code extension, zero extension, etc., according to the attributes of the data determined by the load instruction. in the register file (for example, refer to Patent Document 1).

FIG. 1 is a diagram showing the configuration of a conventional processor.

As shown in the figure, the processor 10 includes an instruction decoding circuit 11 , a memory read control circuit 12 , a memory write control circuit 13 , a memory 14 , an arithmetic unit 15 , a data conversion circuit 20 and a register file 30 . In addition, the register file 30 includes a plurality of registers composed only of data fields 31 . In addition, the data field 31 is managed using a register number (Reg#0 to Reg#N).

The instruction decoding circuit 11 outputs a signal according to the decoded instruction. For example, (a) when the decoded command is a load command, a signal (hereinafter referred to as a load command decoding signal) characterized by the load command is generated and output to the memory read control circuit 12 and the data conversion circuit 20. (b) When the instruction to be decoded is an operation instruction, generate a signal (hereinafter referred to as an operation instruction decoding signal.) with a characteristic added by the operation instruction, and output it to the arithmetic unit 15 and the data conversion circuit 20. (c) When the decoded command is a store command, a signal characterized by the store command (hereinafter referred to as a store command decode signal) is generated and output to the memory write control circuit 13 .

The so-called "load instruction" refers to an instruction to load data from memory.

The so-called "store instruction" is an instruction to store data in the memory.

The so-called "computation command" refers to a command to execute calculation processing.

The load command decoding signal includes information such as address, data size, and data type required for accessing the memory 14 and reading data.

Information for specifying the contents of arithmetic processing is included in the arithmetic instruction decode signal.

The storage instruction decoding signal includes information such as address, data size, and data type required for accessing the memory 14 and writing data.

The memory read control circuit 12 outputs a signal characterized by the load command decode signal (hereinafter referred to as a memory read control signal) to the memory 14 based on the load command decode signal output from the command decode circuit 11 .

The memory write control circuit 13 outputs a signal characterized by the store command decode signal (hereinafter referred to as a memory write control signal) to the memory 14 based on the store command decode signal output from the command decode circuit 11 .

The memory 14 stores data specified by the memory read control signal in the register file 30 based on the memory read control signal output from the memory read control circuit 12 . Also, based on the memory write control signal output from the memory write control circuit 13 , data specified by the memory write control signal is read from the register file 30 .

Also, the data read from the memory 14 is stored in the register file 30 after undergoing data conversion such as configuration change, code extension, and zero extension in the data conversion circuit 20 .

According to the operation instruction decoding signal output from the instruction decoding circuit 11, the arithmetic unit 15 reads out the data determined by the operation instruction decoding signal from the register file 30, and executes the operation determined by the operation instruction decoding signal on the data. deal with. Then, the data obtained by executing the arithmetic processing is stored in the register file 30 .

FIG. 2 is a diagram showing the configuration of a data conversion circuit.

As shown in the figure, here, as an example, the data conversion circuit 20 includes a sorting unit 21 , a zero extension unit 22 , a code extension unit 23 , a selector 24 , and the like.

The sorting unit 21 performs sorting processing on the data output from the memory 14 , and outputs the processed data to the zero extension unit 22 and the code extension unit 23 .

The "sorting process" refers to arranging and outputting a partial bit string of M (M is a natural number) bit data in accordance with the lowest bit. For example, when a partial bit string of the 8th bit to the 15th bit of 32-bit data is input, a bit string arranged from the 0th bit to the 7th bit is output.

The zero extension unit 22 performs zero extension processing on the data output from the sorting unit 21 , and outputs the processed data to the selector 24 .

The so-called "zero extension processing" means that when extending M (M is a natural number.) bit data to N (N is a natural number greater than M.) bit data, the data from the M-1th bit to the highest bit Bit is "0" and output.

The code expansion unit 23 performs code expansion processing on the data output from the sorting unit 21 , and outputs the processed data to the selector 24 .

The so-called "code expansion processing" means that when expanding M (M is a natural number.) bit data to N (N is a natural number greater than M.) bit data, make the code from the M-1th bit to the highest bit The bit is "the value of the code bit of the M-bit data" and output.

The selector 24 selects one of the data output from the memory 14, the data output from the zero extension unit 22, and the data output from the code extension unit 23 based on the load instruction decoding signal output from the instruction decoding circuit 11, and outputs it to the register File 30.

Patent Document 1: Japanese Unexamined Patent Publication No. 9-269895

However, in the prior art described above, there is a problem that when data is output from the memory 14 to the register file 30, it is necessary to pass through the data conversion circuit 20, so the delay generated between the memory 14 and the register file 30 This delay becomes a disadvantage in developing a processor that operates at a high operating frequency.

Contents of the invention

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a processor capable of reducing the delay generated between a memory and a register file and operating at a high operating frequency.

In order to achieve the above object, the processor of the present invention has: (a) a register file having a plurality of registers; (b) a generation unit for generating a tag value representing a data attribute; (c) each of the registers has a A data field and a flag field holding the flag value, (d) when the generating unit executes a load instruction loaded from the memory to the register, the flag value is generated according to the load instruction and stored in the flag field .

As a result, the data stored in the data field can be converted according to the tag value indicating the attribute of the data when executing the instruction for arithmetic processing or the storage instruction for storing data from the register file to the memory, without having to store data in the memory and register file Perform data conversion between configuration changes, code extensions, zero extensions, etc.

In addition, the present invention can be realized not only as a processor, but also as a method of controlling a processor (hereinafter referred to as a control method), or the like. In addition, it can also be used as an LSI that assembles functions provided by a processor (hereinafter referred to as processor functions), and an IP core program that forms processor functions in programmable logic devices such as FPGAs and CPLDs (hereinafter referred to as processor cores). program.), and a recording medium on which the processor core program is recorded.

Invention effect

As described above, according to the processor of the present invention, it is possible to provide a processor that does not need to pass through a data conversion circuit when outputting data from the memory to the register file, thereby reducing the delay generated between the memory and the register file, High operating frequency operation is possible.

In addition, there is provided a processor capable of improving data processing capability because it can easily process data larger than the size of a register allocated to one register number.

Description of drawings

FIG. 1 is a diagram showing the configuration of a conventional processor.

FIG. 2 is a diagram showing the configuration of a data conversion circuit.

FIG. 3 is a diagram showing the configuration of a processor according to Embodiment 1. FIG.

FIG. 4 is a diagram showing the configuration of a register file according to Embodiment 1 as an example.

FIG. 5 is a diagram showing a data structure of a register according to Embodiment 1 as an example.

6A is a first diagram showing an example of data conversion in the data conversion circuit of Embodiment 1. FIG.

6B is a second diagram showing an example of data conversion in the data conversion circuit of the first embodiment.

FIG. 6C is a third diagram showing an example of data conversion in the data conversion circuit of Embodiment 1. FIG.

FIG. 7 is a first diagram showing the operation of the processor according to the first embodiment.

8A is a second diagram showing the operation of the processor according to the first embodiment.

8B is a third diagram showing the operation of the processor according to the first embodiment.

8C is a fourth diagram showing the operation of the processor according to the first embodiment.

FIG. 9 is a diagram showing the configuration of a processor according to Embodiment 2. FIG.

FIG. 10 is a diagram showing the configuration of a register file according to Embodiment 2 as an example.

FIG. 11 is a first diagram showing the operation of the processor according to the second embodiment.

12A is a second diagram showing the operation of the processor according to the second embodiment.

12B is a third diagram showing the operation of the processor according to the second embodiment.

FIG. 13 is a diagram showing the configuration of a processor according to Embodiment 3. FIG.

FIG. 14 is a diagram showing a configuration of an arithmetic unit according to Embodiment 3 as an example.

FIG. 15A is a diagram showing the operation of the processor according to Embodiment 3. FIG.

FIG. 15B is a diagram showing the operation of the processor according to the third embodiment.

FIG. 16 is a diagram showing the configuration of a processor according to Embodiment 4. FIG.

FIG. 17 is a diagram showing a configuration of an arithmetic unit according to Embodiment 4 as an example.

FIG. 18 is a first diagram showing the operation of the processor according to the fourth embodiment.

FIG. 19 is a second diagram showing the operation of the processor according to the fourth embodiment.

FIG. 20 is a diagram showing the configuration of a processor according to Embodiment 5. FIG.

FIG. 21 is a diagram showing a configuration of an arithmetic unit according to Embodiment 5 as an example.

FIG. 22 is a diagram showing a data structure of a register according to Embodiment 5 as an example.

FIG. 23 is a first diagram showing the operation of the processor according to Embodiment 5. FIG.

FIG. 24 is a second diagram showing the operation of the processor according to Embodiment 5. FIG.

FIG. 25 is a third diagram showing the operation of the processor according to Embodiment 5. FIG.

FIG. 26 is a diagram showing the configuration of a processor according to Embodiment 6. FIG.

FIG. 27 is a diagram showing a configuration of an arithmetic unit according to Embodiment 6 as an example.

FIG. 28 is a first diagram showing the operation of the processor according to the sixth embodiment.

FIG. 29 is a second diagram showing the operation of the processor according to the sixth embodiment.

Symbol Description

10 processors

11 instruction decoding circuit

12 memory read control circuit

13 memory write control circuit

14 memory

15 calculator

20 data conversion circuit

21 Sorting Department

22 Zero Extension

23 Code Extension

24 selectors

30 register files

31 data fields

Reg#0～Reg#N registers

100, 200 processors

101 instruction decoding circuit

102 tag value generating circuit

110, 210 register files

111, 211 tag field

112, 212 data fields

113, 213 data attribute judgment circuit

114, 214 data conversion circuit

121, 221 Sorting Department

122, 222 Zero Extension

123, 223 Code Extension Section

124, 224 selector

300, 400 processors

310, 410 register files

311, 411 tag field

312, 412 data fields

320, 420 calculator

321, 421 data attribute judgment circuit

322, 422 operation processing circuit

330 memory write control circuit

331 data attribute judgment circuit

332 data conversion circuit

341, 441 Sorting Department

342, 442 Zero Extension

343, 443 Code Extension Section

344, 444 selector

345, 445 Adder

401 instruction decoding circuit

402 tag value generation circuit

500, 600 processors

510, 610 register files

520, 620 calculator

530 memory write control circuit

531 data attribute judgment circuit

532 data conversion circuit

541, 641 selector

542, 642 adders

543, 643 selector

Detailed ways

(Embodiment 1)

Next, Embodiment 1 of the present invention will be described with reference to the drawings.

The processor according to Embodiment 1 is characterized in that data conversion such as configuration change, code extension, and zero extension is performed before data is output from the register file to the arithmetic unit, instead of being performed between the memory and the register file.

Based on the above points of view, the processor according to Embodiment 1 of the present invention will be described.

FIG. 3 is a diagram showing the configuration of a processor according to Embodiment 1. FIG.

As shown in the figure, the processor 100 includes a memory read control circuit 12 , a memory write control circuit 13 , a memory 14 , and an arithmetic unit 15 . Furthermore, an instruction decoding circuit 101 , a flag value generating circuit 102 , and a register file 110 are provided.

The instruction decoding circuit 110 outputs a signal according to the decoded instruction. For example, (a) when the instruction to be decoded is a load instruction, a signal (hereinafter referred to as a load instruction decoding signal) characterized by the load instruction is generated and output to the memory read control circuit 12 and the flag value generation circuit 102. (b) When the instruction to be decoded is an operation instruction, a signal characterized by the operation instruction (hereinafter referred to as an operation instruction decoding signal) is generated and output to the arithmetic unit 15 and the flag value generation circuit 102 . (c) When the decoded command is a store command, a signal characterized by the store command (hereinafter referred to as a store command decoded signal) is generated and output to the memory write control circuit 13 .

The so-called "load instruction" refers to an instruction to load data from memory.

The so-called "storage instruction" refers to an instruction to store data in the memory.

The term "computation instruction" refers to an instruction to execute arithmetic processing.

The load command decode signal includes information such as address, data size, and data type required for accessing the memory 14 and reading data.

The operation command decode signal includes information specifying the content of the operation processing.

The memory command decode signal includes information such as an address, data size, and data type required to access the memory 14 and write data.

The tag value generation circuit 102 generates a tag value indicating the attribute of the data stored in the register file 110 by the load command decode signal output from the command decode circuit 101, and compares the generated tag value with This data is correspondingly stored in register file 110 . In addition, based on the operation instruction decoding signal output from the instruction decoding circuit 101, a tag value indicating the attribute of the data stored in the register file 110 by the operation instruction decoding signal is generated, and the generated tag value is associated with the data. stored in register file 110.

In addition, the tag value shows the attribute of the data corresponding to the tag value. In addition, the attributes include data size, data type, and valid or invalid information of each bit constituting the data.

The register file 110 has a plurality of registers composed of a flag field 111 and a data field 112 . Furthermore, a data attribute judgment circuit 113 and a data conversion circuit 114 are provided.

A tag value is stored in the tag field 111 , and data corresponding to the tag value is stored in the data field 112 .

In addition, the data field 112 and the flag field 111 have a one-to-one correspondence, and are managed by register numbers (Reg#0-Reg#N).

The data attribute judging circuit 113 reads the tag value corresponding to the data from the tag field 111 when reading data from the data field 112 , and judges the attribute of the data according to the read tag value. Then, the judgment result is output to the data conversion circuit 114 as a data attribute judgment signal.

The data conversion circuit 114 judges whether to convert the data according to the data attribute judgment signal when reading data from the data field 112 . When the judgment result is conversion, the read data is converted according to the data attribute judgment signal, and the converted data is output. When not converted, the read data is output without conversion.

The memory read control circuit 12 outputs a signal characterized by the load command decode signal (hereinafter referred to as a memory read control signal) to the memory 14 based on the load command decode signal output from the command decode circuit 101 .

The memory write control circuit 13 outputs a signal characterized by the store command decode signal (hereinafter referred to as a memory write control signal) to the memory 14 based on the store command decode signal output from the command decode circuit 101 .

The memory 14 stores data specified by the memory read control signal in the register file 110 based on the memory read control signal output from the memory read control circuit 12 . Also, based on the memory write control signal output from the memory write control circuit 13 , data specified by the memory write control signal is read from the register file 110 .

In addition, the data read from the memory 14 is stored in the register file 110 without performing data conversion such as configuration change, code extension, and zero extension.

The arithmetic unit 15 reads the data determined by the decoding signal of the calculation command from the register file 110 according to the decoding signal of the calculation command output from the command decoding circuit 101, and executes the calculation processing determined by the decoding signal of the calculation command on the data. . Then, the data obtained by executing the arithmetic processing is stored in the register file 110 .

Next, as an example, the configuration of the register file according to Embodiment 1 will be described.

Here, a case will be described taking, as an example, a case where arithmetic processing is performed on data read from the register (Reg#0), and the data obtained by performing the arithmetic processing, that is, an arithmetic result is stored in the register (Reg#1).

FIG. 4 is a diagram showing the configuration of a register file according to Embodiment 1 as an example.

As shown in the figure, the data attribute judging circuit 113 reads the tag value from the tag field 111 of the register (Reg#0), and judges the data read from the data field 112 of the register (Reg#0) according to the tag value read out Attributes. Then, the judgment result is output to the selector 124 and the like as a data attribute judgment signal.

On the other hand, the sorting unit 121 sorts the data output from the data field 112 of the register (Reg#0), and outputs the processed data to the zero extension unit 122 and the code extension unit 123 .

The "sorting process" refers to a process of arranging and outputting a partial bit string of M (M is a natural number)-bit data in accordance with the lowest bit. For example, when a partial bit string of the 8th bit to the 15th bit of 32-bit data is input, a bit string arranged from the 0th bit to the 7th bit is output.

The zero extension unit 122 performs zero extension processing on the data output from the sorting unit 121 , and outputs the processed data to the selector 124 .

The so-called "zero extension processing" means that when extending M (M is a natural number.) bit data to N (N is a natural number greater than M.) bit data, the data from the M-1th bit to the highest bit Bit is "0" and output processing.

The code expansion unit 123 performs code expansion processing on the data output from the sorting unit 121 , and outputs the processed data to the selector 124 .

The so-called "code expansion processing" means that when expanding M (M is a natural number.) bit data to N (N is a natural number greater than M.) bit data, make the code from the M-1th bit to the highest bit Bit is "the value of the code bit of M-bit data" and output.

The selector 124 selects the data output from the data field 112 of the register (Reg#0), the data output from the zero extension section 122, and the data output from the code extension section 123 based on the data attribute judgment signal output from the data attribute judgment circuit 113. One of them is output to the arithmetic unit 15.

Then, the arithmetic unit 15 executes arithmetic processing on the data output from the selector 124, and stores data obtained by performing the arithmetic processing, that is, an arithmetic result, in the data field 112 of the register (Reg#1).

Next, as an example, the data structure of the register in Embodiment 1 will be described.

FIG. 5 is a diagram showing a data structure of a register according to Embodiment 1 as an example.

As shown, the register is composed of an 8-bit flag field 151 and a 32-bit data field.

The lower 4 bits from the 0th bit to the 3rd bit of the flag field 151 indicate a valid bit, that is, from where in the data field 152 data is stored. For example, when (a) is "1000", it indicates that storage starts from the third bit string (31st bit). (b) When it is "0100", it indicates that storage starts from the second bit string (the 23rd bit). (c) When it is "0010", it means that the storage starts from the first bit string (15th bit). (d) When it is "0001", it indicates that storage starts from the 0th bit string (7th bit).

2 bits of the 4th to 5th bits of the flag field 151 indicate the size of data stored in the data field 152 . For example, (a) indicates 32 bits when it is "00", (b) indicates 16 bits when it is "01", and (c) indicates 8 bits when it is "10". Also, "11" is empty.

Bit 6 of the flag field 151 indicates whether or not the data stored in the data field 152 is coded data. For example, when (a) is "0", it indicates data without a code, and when (b) is "1", it indicates data with a code.

Bit 7 of the flag field 151 indicates whether or not the data stored in the data field 152 is data on which data conversion such as configuration change, code extension, zero extension, etc. has been performed. For example, when (a) is "0", it indicates that the conversion is completed, that is, the data after conversion, and when (b) is "1", it indicates that the conversion is not completed, that is, the data before conversion.

Next, an example of data conversion in the data conversion circuit of Embodiment 1 will be described.

6A to 6C are diagrams showing examples of data conversion in the data conversion circuit according to the first embodiment.

As shown in the figure, the data conversion circuit 114 differs according to the following (1) to (3), and the content of the data conversion is different.

(1) When executing instruction 161a (mov Reg, Mem) and reading 32-bit data from memory 162b, data conversion circuit 114 does not convert. That is, 32-bit data is stored in the 32-bit register 163b. (See Figure 6A.).

(2) When executing the instruction 161b (movb Reg, Mem) and reading out the effective 8-bit data from the first bit string in the 32 bits from the memory 162b, the data conversion circuit 114 converts it to the lowest bit Bit-aligned and zero-extended data. Then, the converted data is stored in the 32-bit register 163b. (See Figure 6B.).

(3) When the instruction 161c (movbex Reg, Mem) is executed and the effective 8-bit data from the first bit string in the 32 bits is read from the memory 162b, the data conversion circuit 114 converts it into the lowest bit Bit-aligned and code-extended data. Then, the converted data is stored in the 32-bit register 163c. (See Figure 6C.).

Next, the operation of the processor according to Embodiment 1 will be described.

7 and 8A to 8C are diagrams showing operations of the processor according to the first embodiment.

As shown in FIG. 7 , the instruction decoding circuit 101 executes one of the following (1) to (3) according to the decoded instruction (step S101 ).

(1) When the decoded command is a load command, the command decoding circuit 101 outputs a load command decode signal to the memory read control circuit 12 and the flag value generating circuit 102 (step S111 ).

Correspondingly, the memory read control circuit 12 outputs a memory read control signal to the memory 14 (step S112). The memory 14 stores the data specified by the memory read control signal in the register file 110 (step S113). On the other hand, flag value generating circuit 102 stores, in register file 110 , a flag value indicating an attribute of the data stored in register file 110 by the load instruction decode signal in association with the data (step S114 ).

At this time, as shown in FIG. 8, the register file 110 stores the data determined by the load instruction decoding signal in the data field 112 (step S121), and stores the tag value corresponding to the data in the tag field 111 (step S122).

(2) When the decoded instruction is an operation instruction, the instruction decoding circuit 101 outputs an operation instruction decoding signal to the arithmetic unit 15 and the flag value generation circuit 102 (step S131).

Correspondingly, the arithmetic unit 15 reads the data determined by the decoding signal of the operation instruction from the register file 110 (step S132), and executes the operation processing determined by the decoding signal of the operation instruction on the read data (step S133). Then, the data obtained by executing the arithmetic processing is stored in the register file 110 (step S134). On the other hand, the flag value generating circuit 102 stores, in the register file 110, a flag value indicating an attribute of the data stored in the register file 110 from the operation instruction decoded signal in association with the data obtained by executing the arithmetic processing (step S135) .

At this time, as shown in FIG. 8B, in the data attribute judging circuit 113, the register file 110 judges the attribute of the data according to the tag value corresponding to the data determined by the operation instruction decoding signal (step S141), and judges The result is output to the data conversion circuit 114 as a data attribute judgment signal (step S142). Then, in the data conversion circuit 114, it is judged whether to convert the data according to the data attribute judgment signal (step S143). When the judgment result is conversion (step S143: Yes), the data is converted according to the data attribute judgment signal (step S144), and the converted data is output to the arithmetic unit 15 (step S145).

In addition, when it is not converted (step S143: NO), the data specified by the operation command decode signal is not converted and output to the arithmetic unit 15 as it is.

(3) When the decoded command is a store command, the command decoding circuit 101 outputs a store command decode signal to the memory writing control circuit 13 (step S151).

Correspondingly, the memory write control circuit 13 outputs a memory write control signal to the memory 14 (step S152). The memory 14 reads out the data specified by the memory write control signal from the register file 110 (step S153).

At this time, as shown in FIG. 8C, in the data attribute judging circuit 113, the register file 110 judges the attribute of the data according to the tag value corresponding to the data determined by the store instruction decoding signal (step S161), and judges The result is output to the data conversion circuit 114 as a data attribute judgment signal (step S162). Then, in the data conversion circuit 114, it is judged whether to convert the data according to the data attribute judgment signal (step S163). When the judgment result is conversion (step S163: Yes), the data is converted according to the data attribute judgment signal (step S164), and the converted data is output to the memory 14 (step S165).

In addition, when it is not converted (step S163: NO), the data determined by the memory write control signal are output to the memory 14 without conversion.

According to the processor 100 of Embodiment 1 as described above, the register file 110 includes a flag field 111 , a data field 112 , a data attribute determination circuit 113 , and a data conversion circuit 114 .

As a result, before data is output from the register file 110 to the arithmetic unit 15, data conversion such as configuration changes, code extensions, and zero extensions can be performed instead of being performed between the memory 14 and the register file 110, and the number of conversions in the memory 14 can be reduced. and register file 110. Furthermore, since the arithmetic unit 15 can be used in common with existing arithmetic units, the design is also easy.

(Embodiment 2)

Next, Embodiment 2 of the present invention will be described with reference to the drawings.

The processor according to Embodiment 2 is characterized in that before outputting data from the register file to the arithmetic unit, data conversion such as configuration change, code extension, and zero extension is performed inside the register file instead of between the memory and the register file. .

Based on the above points of view, the processor according to Embodiment 2 will be described.

In addition, the same code|symbol is attached|subjected to the same component as Embodiment 1, and description is abbreviate|omitted.

FIG. 9 is a diagram showing the configuration of a processor according to Embodiment 2. FIG.

As shown in the figure, the processor 200 differs from the processor 100 according to Embodiment 1 in that it includes a register file 210 instead of the register file 110 (see FIG. 3 ).

Compared with the register file 110, the register file 210 is different in that it has a tag field 211, a data field 212, a data attribute judging circuit 213, and a data conversion circuit 214, instead of the tag field 111, the data field 112, the data attribute judging circuit 113, Data conversion circuit 114.

The data attribute judging circuit 213, when storing data in the data field 212 again, reads the tag value corresponding to the data from the tag field 211, and judges the attribute of the data according to the read tag value. Then, the judgment result is output to the data conversion circuit 214 as a data attribute judgment signal. And, according to the judgment result, it is judged whether to convert the flag value. When the judgment result is conversion, the tag value is converted according to the judgment result, and the converted tag value is stored in the register file 210 to replace the converted tag value with the converted tag value.

The data conversion circuit 214, when re-storing data into the data field 212, judges whether to convert the data according to the data attribute judgment signal. When the judgment result is conversion, the data is converted according to the data attribute judgment signal, and the converted data is stored in the data field 212 . When not converted, the data is not converted.

Next, as an example, the configuration of the register file according to Embodiment 2 will be described.

Here, the case where the data read from the memory (Reg#0) is converted into data and the converted data is stored in the register (Reg#0) will be described as an example.

FIG. 10 is a diagram showing the configuration of a register file according to Embodiment 2 as an example.

As shown in the figure, the data attribute judging circuit 213 reads out the tag value from the tag field 211 of the register (Reg#0), and judges the identity of the data read out from the data field 212 of the register (Reg#0) according to the tag value read out. Attributes. Then, the judgment result is output to the selector 224 as a data attribute judgment signal.

On the other hand, the sorting unit 221 sorts the data output from the data field 212 of the register (Reg#0), and outputs the processed data to the zero extension unit 222 and the code extension unit 223 .

In addition, since the zero extension unit 222 and the code extension unit 223 have the same configuration as the zero extension unit 122 and the code extension unit 123 in Embodiment 1, description thereof will be omitted.

The selector 224 selects the data output from the data field 212 of the register (Reg#0), the data output from the zero extension part 222, and the data output from the code extension part 223 based on the data attribute judgment signal output from the data attribute judgment circuit 213. One of them, and store into the data field 112 of the register (Reg#0).

And, the data attribute judging circuit 213 converts the read flag value, and stores the converted flag value in the flag field 212 of the register (Reg#0).

Then, the arithmetic unit 15 performs arithmetic processing on the converted data output from the data field 212 of the register (Reg#0), and stores the data obtained by the arithmetic processing, that is, the arithmetic result, into data such as the register (Reg#1). Field 212.

Next, the operation of the processor 200 according to Embodiment 2 will be described.

11 , 12A, and 12B are diagrams showing operations of the processor according to the second embodiment.

As shown in FIG. 11 , FIG. 12A , and FIG. 12B , the processor 200 differs from the processor 100 according to Embodiment 1 in the following points (1) to (3).

(1) The operation when the load command is executed differs from the operation in Embodiment 1 (steps S111 to S114 , S121 to S122 ) in the following points (see FIG. 8A and FIG. 11 ).

When the register file 210 executes the load command instead of the operation of the register file 110 in Embodiment 1 (steps S121 to S122), and stores the data in the data field 212 again (step S221), in the data attribute judging circuit 213, according to the The tag value corresponding to the data judges the attribute of the data (step S222), and outputs the judgment result as a data attribute signal to the data conversion circuit 213 (step S223). And, it is judged whether to convert the flag value according to the judgment result (step S224). When the result of judging is conversion (step S224: Yes), convert the tag value (step S225) according to the judgment result, and store the tag value after conversion into the tag field 211, so as to replace the tag value before conversion with conversion After the mark value (step S226). Then, in the data conversion circuit 213, it is judged whether to convert the data according to the data attribute judgment signal (step S227). When the result of judging is conversion (step S227: Yes), the data is converted according to the data attribute judgment signal (step S228), and the converted data is stored in the data field 212 to replace the converted data with the converted data. data (step S229).

(2) The operation when the operation command is executed differs from the operation in Embodiment 1 (steps S131 to S135 , S141 to S144 ) in the following points (see FIG. 8B and FIG. 12A ).

When register file 210 replaces the operation of register file 110 in Embodiment 1 (steps S141 to S144) to execute an operation instruction, data is read from data field 212 (step S241).

(3) The operation when the store command is executed differs from the operation in Embodiment 1 (steps S151 to S153 , S161 to S164 ) in the following points (see FIG. 8C and FIG. 12B ).

When register file 210 executes a store command instead of the operation of register file 110 in Embodiment 1 (steps S161 to S164), the data stored in data field 212 is output to memory 14 (step S261).

According to the processor 200 of Embodiment 2 as described above, the register file 210 includes a flag field 211 , a data field 212 , a data attribute judgment circuit 213 , and a data conversion circuit 214 .

Therefore, data conversion such as configuration change, code extension, and zero extension can be performed inside the register file 210 before outputting the data from the register file 210 to the arithmetic unit 15, instead of being performed between the memory 14 and the register file 210, And the delay generated between the memory 14 and the register file 210 can be reduced. In addition, since data conversion is performed inside the register file 210 , there is no influence of increased delay between the register file 210 and the arithmetic unit 15 and between the register file 210 and the memory 14 . In addition, since the computing unit 15 can be used with existing computing units, the design is easy.

(Embodiment 3)

Next, Embodiment 3 of the present invention will be described with reference to the drawings.

The processor according to Embodiment 3 is characterized in that data conversion such as configuration change, code extension, and zero extension is performed inside the arithmetic unit and the memory write control circuit, instead of between the memory and the register file.

Based on the above points of view, the processor according to Embodiment 3 will be described.

In addition, the same code|symbol is attached|subjected to the same component as Embodiment 1, and description is abbreviate|omitted.

FIG. 13 is a diagram showing the configuration of a processor according to Embodiment 3. FIG.

As shown in the figure, the processor 300 differs from the processor 100 according to Embodiment 1 in the following points (1) to (3) (see FIG. 3 ).

(1) The register file 310 is provided instead of the register file 110 .

The difference between the register file 310 and the register file 110 is that it does not have the data attribute judgment circuit 113 and the data conversion circuit 114 .

(2) The arithmetic unit 320 is provided instead of the arithmetic unit 15 .

Compared with the arithmetic unit 15 , the arithmetic unit 320 is different in that it newly includes a data attribute judgment circuit 321 and an arithmetic processing circuit 322 .

The data attribute judging circuit 321 reads out the flag value corresponding to the data determined by the operation instruction decoding signal from the register file 310, and judges the attribute of the data according to the read flag value. Then, the determination result is output to the arithmetic processing circuit 322 as a data attribute determination signal.

The arithmetic processing circuit 322 reads out data specified by the arithmetic instruction decode signal from the register file 310 . Whether to convert the read data is judged according to the data attribute judging signal. When the judging result is conversion, the read data is converted according to the data attribute judgment signal, and the converted data is processed. Then, the data obtained by performing the arithmetic processing is stored in the data field 311 of the register file 310 .

In addition, in the case of no conversion, the read data is not converted, and the arithmetic processing is performed as it is.

(3) A memory write control circuit 330 is provided instead of the memory write control circuit 13 .

Compared with the memory write control circuit 13 , the memory write control circuit 330 is different in that it newly includes a data attribute determination circuit 331 and a data conversion circuit 332 .

The data attribute judging circuit 331 reads out the flag value corresponding to the data determined by the store instruction decoding signal from the register file 310, and judges the attribute of the data according to the read flag value. Then, the judgment result is output to the data conversion circuit 332 as a data attribute judgment signal. Then, a memory write control signal based on the store command decode signal and the flag value is generated and output to the memory 14 .

The data conversion circuit 332 reads out the data determined by the store instruction decoding signal from the register file 310, and judges whether to convert the read data according to the data attribute judgment signal. When the judgment result is conversion, the read data is converted according to the data attribute judgment signal, and the converted data is output to the memory 14 .

In addition, in the case of no conversion, the read data is directly output to the memory 14 without conversion.

Next, as an example, the configuration of the arithmetic unit according to Embodiment 3 will be described.

Here, a case where addition processing is performed on data read from the register (Reg#0) and the addition result is stored in the register (Reg#1) will be described as an example.

FIG. 14 is a diagram showing a configuration of an arithmetic unit according to Embodiment 3 as an example.

As shown in the figure, the data attribute judging circuit 321 reads the tag value from the tag field 311 of the register (Reg#0), and judges the identity of the data read from the data field 312 of the register (Reg#0) according to the tag value read out. Attributes. Then, the judgment result is output to the selector 344 as a data attribute judgment signal.

On the other hand, the sorting unit 341 sorts the data output from the data field 312 of the register (Reg#0), and outputs the processed data to the zero extension unit 342 and the code extension unit 343 .

The zero extension unit 342 performs zero extension processing on the data output from the sorting unit 341 , and outputs the processed data to the selector 344 .

The code extension unit 343 performs code extension processing on the data output from the sorting unit 341 , and outputs the processed data to the selector 344 .

The selector 344 selects the data output from the data field 312 of the register (Reg#0), the data output from the zero extension part 342, and the data output from the code extension part 343 based on the data attribute judgment signal output from the data attribute judgment circuit 321. One, and output to the adder 345.

The adder 345 performs addition processing on the data output from the selector 344, and stores the data obtained by performing the addition processing, that is, an operation result, in the data field 312 of the register (Reg#1).

Next, the operation of the processor 300 according to Embodiment 3 will be described.

15A and 15B are diagrams showing operations of the processor according to the third embodiment.

As shown in the figure, the processor 300 differs from the processor 100 of the embodiment in the following points.

(1) The operation when the load command is executed is the same as the operation (steps S111 to S114 , S121 to S122 ) in Embodiment 1, and description thereof will be omitted.

(2) The operation when the operation command is executed differs from the operation in the first embodiment (steps S131 to S135 , S141 to S145 ) in the following points (see FIG. 8B and FIG. 15A ).

When replacing the operation of the register file 110 of Embodiment 1 (steps S141 to S144), when the arithmetic unit 320 executes an arithmetic instruction, in the data attribute judging circuit 321, based on the flag value corresponding to the data determined by the arithmetic instruction decoding signal, The attribute of the data is judged (step S341), and the judgment result is output to the arithmetic processing circuit 322 as a data attribute judgment signal (step S342). Then, in the arithmetic processing circuit 322, it is judged whether to convert the data based on the data attribute judgment signal (step S343). When the judgment result is conversion (step S343: Yes), the data is converted according to the data attribute judgment signal (step S344), and arithmetic processing is performed on the converted data (step S345). The data obtained by executing the arithmetic processing is stored in the data field 312 of the register file 310 (step S346).

In addition, when it is not converted (step S343: No), the calculation process is directly performed without converting the data specified by the calculation instruction decode signal.

(3) The operation when the store command is executed differs from the operation in Embodiment 1 (steps S151 to S153 , S161 to S165 ) in the following points (see FIG. 8C and FIG. 15B ).

When the memory write control circuit 330 executes a store instruction instead of the operation of the register file 110 in the first embodiment (steps S161 to S164), the data attribute judging circuit 331 uses the data corresponding to the data specified by the memory write control signal mark value, judge the attribute of the data (step S361), and output the judgment result as a data attribute judgment signal to the data conversion circuit 332 (step S362). And, it is judged whether to convert the data according to the data attribute judgment signal in the data conversion circuit 332 (step S363). When the judgment result is conversion (step S363: Yes), the data is converted according to the data attribute judgment signal (step S364), and the converted data is output to the memory (step S365).

In addition, when it is not converted (step S363: NO), the data determined by the memory write control signal are output to the memory 14 as it is without conversion.

According to the processor 300 of Embodiment 3 as described above, the flag field 311 and the data field 312 are provided in the register file 310, the data attribute determination circuit 321 and the operation processing circuit 322 are provided in the arithmetic unit 320, and the memory write control unit 330 includes a data attribute judgment circuit 331 and a data conversion circuit 332 .

As a result, data conversion such as configuration change, code extension, and zero extension can be performed inside the arithmetic unit 320 and the memory write control circuit 330 instead of between the memory 14 and the register file 310, and the memory 14 can be reduced. and register file 310.

(Embodiment 4)

Next, Embodiment 4 of the present invention will be described with reference to the drawings.

The processor according to Embodiment 4 is characterized in that data conversion such as configuration change, code extension, and zero extension is performed inside each of the arithmetic unit and the memory write control circuit instead of between the memory and the register memory.

Based on the above points, a processor according to Embodiment 4 will be described.

In addition, the same reference numerals are attached to the same constituent elements as those in Embodiment 3, and description thereof will be omitted.

FIG. 16 is a diagram showing the configuration of a processor according to Embodiment 4. FIG.

As shown in the figure, the processor 400 differs from the processor 300 of Embodiment 3 in the following points (1) to (3) (see FIG. 5 ).

(1) An instruction decoding circuit 401 is provided instead of the instruction decoding circuit 101 .

Compared with the instruction decoding circuit 101 , the instruction decoding circuit 401 is different in that: when executing an operation instruction, it does not output the operation instruction decoding signal to the flag value generation circuit 402 .

(2) A flag value generating circuit 402 is provided instead of the flag value generating circuit 102 .

The flag value generation circuit 402 differs from the flag value generation circuit 102 in that it does not generate a flag value indicating the attribute of data obtained by executing the arithmetic processing determined by the arithmetic instruction decode signal.

(3) A computing unit 420 is provided instead of the computing unit 320 .

Compared with the arithmetic unit 320 , the arithmetic unit 420 is different in that it includes a data attribute judgment circuit 421 and an arithmetic processing circuit 422 instead of the data attribute judgment circuit 321 and the arithmetic processing circuit 322 .

The data attribute judging circuit 421 reads out the flag value corresponding to the data determined by the operation instruction decoding signal from the register file 410, and judges the attribute of the data according to the read flag value. And, the determination result is output to the arithmetic processing circuit 422 as a data attribute determination signal. Then, a tag value indicating the attribute of the data obtained by executing the arithmetic processing specified by the operation instruction decode signal is generated, and the generated tag value is stored in the register file 410 in association with the data obtained by executing the arithmetic processing.

The arithmetic processing circuit 422 reads the data determined by the decoding signal of the arithmetic instruction from the register file 410, and judges whether to convert the read data according to the data attribute judging signal. When the judgment result is conversion, the read data is converted according to the data attribute judgment signal, and the operation processing determined by the operation instruction decoding signal is performed on the converted data. Also, the data obtained by executing the arithmetic processing is stored in the register file 410 .

In addition, in the case of no conversion, the read data is not converted and the arithmetic processing is directly executed.

Next, as an example, the configuration of the arithmetic unit according to Embodiment 4 will be described.

Here, a case where arithmetic processing is performed on data read from the register (Reg#0) and the data obtained by performing the arithmetic processing, that is, the calculation result is stored in the register (Reg#1) will be described as an example.

FIG. 17 is a diagram showing a configuration of an arithmetic unit according to Embodiment 4 as an example.

As shown in the figure, the data attribute judging circuit 421 reads the tag value from the tag field 411 of the register (Reg#0), and judges the identity of the data read from the data field 412 of the register (Reg#0) according to the tag value read out. Attributes. Also, the judgment result is output to the selector 444 and the like as an attribute judgment signal.

On the other hand, the sorting unit 441 sorts the data output from the data field 412 of the register (Reg#0), and outputs the processed data to the zero extension unit 442 and the code extension unit 443 .

The selector 444 selects the data output from the data field 412 of the register (Reg#0), the data output from the zero extension part 442, and the data output from the code extension part 443 based on the data attribute judgment signal output from the data attribute judgment circuit 421. One of them, and output to adder 445.

The adder 445 performs addition processing on the data output from the selector 444, and stores the data obtained by performing the addition processing, that is, an operation result, in the data field 412 of the register (Reg#1).

Then, the data attribute determination circuit 421 generates a flag value for the data obtained by the addition process performed by the adder 445 , that is, an operation result, and stores the generated flag value in the flag field 411 of the register (Reg#1).

In addition, the configurations of the zero extension unit 442 and the code extension unit 443 are the same as those of the zero extension unit 342 and the code extension unit 343 in Embodiment 3, and description thereof will be omitted.

Next, the operation of Embodiment 4 will be described.

18 and 19 are diagrams showing operations of the processor according to the fourth embodiment.

As shown in FIGS. 18 and 19 , the processor 400 differs from the processor 300 according to Embodiment 3 in the following point (2).

(1) The operation when the load command is executed is the same as the operation (steps S111 to S114 , S121 to S122 ) in Embodiment 3, and therefore description thereof will be omitted.

(2) The operation when the operation instruction is executed differs from the operation in the third embodiment in the following points (see FIG. 7 , FIG. 15A , FIG. 18 , and FIG. 19 ).

Instead of the operation of the instruction decoding circuit 101 in the third embodiment (step S131), the instruction decoding circuit 401 outputs an operation instruction decoding signal to the arithmetic unit 420 when the decoded instruction is an operation instruction (step S431).

In addition, instead of the operation of the flag value generation circuit 102 in the third embodiment (step S135), the arithmetic unit 420 sets, in the data attribute judging circuit 421, a flag indicating the attribute of the data stored in the register file 410 from the operation instruction decoded signal. The value is stored in the flag field 411 of the register file 410 corresponding to the data (step S441).

(3) The operation when the store command is executed is the same as the operation (steps S151 to S153 , S361 to S365 ) in Embodiment 3, and therefore description thereof will be omitted.

According to the processor 400 of Embodiment 4 as described above, the flag field 411 and the data field 412 are provided in the register file 410, the data attribute determination circuit 421 and the operation processing circuit 422 are provided in the arithmetic unit 420, and the memory write control unit 430 includes a data attribute judgment circuit 431 and a data conversion circuit 432 .

As a result, data conversions such as configuration change, code extension, and zero extension can be performed inside the arithmetic unit 420 and the memory write control circuit 330 instead of between the memory 14 and the register file 410, and the number of data conversions between the memory 14 and the register file 410 can be reduced. Delays incurred between register files 410 . In addition, since the tag value indicating the attribute of the data is added to the data obtained by executing the arithmetic processing, it is not necessary to specify the attribute of the data for the instruction executing the arithmetic processing, and the number of instructions can be reduced and the instruction decoding circuit 401 can be simplified.

(Embodiment 5)

Next, Embodiment 5 of the present invention will be described with reference to the drawings.

The processor according to Embodiment 5 is characterized in that data having a size larger than a data field is stored across a plurality of registers. And, data is restored from data stored across a plurality of registers, and arithmetic processing is performed on the restored data.

Based on the above points, a processor according to Embodiment 5 will be described.

In addition, the same code|symbol is attached|subjected to the same component as Embodiment 3, and description is abbreviate|omitted.

FIG. 20 is a diagram showing the configuration of a processor in Embodiment 5. FIG.

As shown in the figure, the processor 500 is the same as the processor 300 in Embodiment 3, except for the following differences (1) to (3) (see FIG. 5 ).

(1) A register file 510 is provided instead of the register file 310 .

Register file 510 differs from register file 310 in that when storing data larger in size than data field 512, the data is stored across multiple registers.

(2) A computing unit 520 is provided instead of the computing unit 320 .

Compared with the arithmetic unit 320 , the arithmetic unit 520 is different in that it includes a data attribute judgment circuit 521 and an arithmetic processing circuit 522 instead of the data attribute judgment circuit 321 and the arithmetic processing circuit 322 .

The data attribute judging circuit 521 reads out the flag value corresponding to the data determined by the operation instruction decoding signal from the register file 510, and judges the attribute of the data according to the read flag value. And, the determination result is output to the arithmetic processing circuit 522 as a data attribute determination signal. Then, a tag value representing the attribute of the data obtained by executing the arithmetic processing determined by the operation instruction decode signal is generated, and the generated tag value is stored in the register file in association with the data obtained by executing the arithmetic processing.

The arithmetic processing circuit 522 reads the data determined by the decoding signal of the arithmetic instruction from the register file 510, and judges whether to convert the read data according to the data attribute judging signal. When the result of the judgment is conversion, the read data is converted according to the data attribute judgment signal. The arithmetic processing determined by the arithmetic instruction decoding signal is performed on the converted data. Also, the data obtained by executing the arithmetic processing is stored in the register file.

In addition, in the case of no conversion, the read data is not converted and the arithmetic processing is directly executed.

In addition, the operation processing circuit 522 restores the data from the data read from these registers when data is stored in the registers across a plurality of registers, and executes the operation processing determined by the operation command decode signal on the restored data. Also, the data obtained by executing the arithmetic processing is stored in the register file 510 across a plurality of registers.

(3) A memory write control circuit 530 is provided instead of the memory write control circuit 330 .

Compared with the memory write control circuit 330 , the memory write control circuit 530 is different in that it includes a data attribute judgment circuit 531 and a data conversion circuit 532 instead of the data attribute judgment circuit 331 and the data conversion circuit 332 .

The data attribute judging circuit 531 reads out the tag value corresponding to the data determined by the store instruction decoding signal from the register file 510, and judges the attribute of the data according to the read tag value. And, the judgment result is output to the data conversion circuit 530 as a data attribute judgment signal. And, a memory write control signal based on the store command decoding signal and the flag value is output to the memory.

The data conversion circuit 532 reads out the data determined by the store command decoding signal from the register file 510, and judges whether to convert the read data according to the data attribute judgment signal. When the judgment result is conversion, the read data is converted according to the data attribute judgment signal, and the converted data is output to the memory.

In addition, in the case of no conversion, the read data is directly output to the memory 14 without conversion.

In addition, the data conversion circuit 532 restores the data from the data read from these registers when data is stored in the register file 510 across a plurality of registers, and outputs the restored data to the memory 14 .

Next, the configuration of the arithmetic unit in Embodiment 5 will be described as an example.

Here, the addition processing is performed on the data stored across the register (Reg#0) and the register (Reg#1), and the data obtained by performing the addition processing, that is, the result of the addition is stored in the register (Reg#2) and register (Reg#2) and Take the situation in the register (Reg#3) as an example to illustrate.

FIG. 21 is a diagram showing a configuration of an arithmetic unit according to Embodiment 5 as an example.

As shown in the figure, the data attribute judging circuit 521 reads the tag value from the tag field 511 of the register (Reg#0), and judges whether the data corresponding to the read tag value is across registers ( Reg#0) and the data stored in the register (Reg#1). Then, a data attribute judgment signal indicating that the data stored across the register (Reg#0) and the register (Reg#1) is output to the selector 541, the adder 542, and the selector 543.

In contrast, the selector 541 selects the data of the slave register (Reg#1) from the data output from the data field 512 of the register (Reg#0) and the data output from the data field 512 of the register (Reg#1). The data output by field 512 is output to adder 542 .

In addition, the adder 542 makes the data output from the data field 512 of the register (Reg#0) the high-order part, and makes the data output from the selector 541, that is, the data output from the data field 512 of the register (Reg#1) the low-order part. part, and combine the high part and low part to restore the data. Then, addition processing is performed on the restored data, and the data obtained by performing the addition processing, that is, the addition result is divided into an upper part and a lower part, and each is output to the selector 543 . In addition, the lower part is stored in the data field of the register (Reg#3).

Further, the selector 543 selects the high-order part from the high-order part and the low-order part output from the adder 542 and stores it in the data field 512 of the register (Reg#2).

Next, the data structure of the register in Embodiment 5 will be described as an example.

FIG. 22 is a diagram showing a data structure of a register in Embodiment 5 as an example.

As shown in the figure, the register according to Embodiment 5 differs from the register according to Embodiment 1 in the following point (2).

(1) The lower 4 bits from bit 0 to bit 3 of the flag field 551 are the same as the lower 4 bits from bit 0 to bit 3 of the flag field 151 , so the description is omitted.

(2) The 2 bits from the 4th to the 5th bits of the flag field 551 are compared with the 2 bits from the 4th to the 5th bits of the flag field 151, (d) when it is "11", it is 64 bits A little bit different. At this time, the size of the data field remains 32 bits, and the data field 553 of a plurality of registers is allocated.

(3) The 6th to 7th two bits of the flag field 551 are the same as the 6th to 7th two bits of the flag field 151 , so description is omitted.

Next, the operation of the processor in Embodiment 5 will be described.

23 to 25 are diagrams showing operations of the processor according to the fifth embodiment.

As shown in FIGS. 23 to 25 , the processor 500 differs from the processor 300 according to Embodiment 3 in the following points (1) to (3).

(1) The operation when the load command is executed differs from the operation in Embodiment 3 (steps S111 to S114 , S121 to S122 ) in the following points (see FIG. 8A and FIG. 23 ).

The register file 510, when the data specified by the memory read control signal is larger than the size of the data field (step S521: No), stores the data across a plurality of registers (step S522).

(2) The operation when the operation instruction is executed differs from the operation in Embodiment 3 (steps S131 to S135 , S341 to S346 ) in the following points (see FIG. 15A and FIG. 24 ).

The arithmetic unit 520, when storing the data determined by the operation instruction decoding signal across multiple registers (step S541: No), restores the data according to the data read from these registers (step S254), and executes on the restored data. Operation processing (step S543). The data obtained by executing the arithmetic processing is stored in the register file 510 across multiple registers (step S544).

(3) The operation when the store command is executed differs from the operation (steps S151 to S153 , S361 to S365 ) in Embodiment 3 in the following points (see FIG. 15A and FIG. 25 ).

The memory writing control circuit 530, when storing the data determined by the memory writing control signal across multiple registers (step 561: No), restores the data according to the data read from these registers (step S562), and stores the restored The data is output to the memory 14 (step S365).

According to the processor according to Embodiment 5 as described above, the flag field 511 and the data field 512 are provided in the register file 510, the data attribute determination circuit 521 and the operation processing circuit 522 are provided in the arithmetic unit 520, and the memory write control unit 530 It includes a data attribute judgment circuit 531 and a data conversion circuit 532 .

Thus, data larger in size than the data field 512 can be easily handled.

(Embodiment 6)

Next, Embodiment 6 of the present invention will be described with reference to the drawings.

The processor according to Embodiment 6 is characterized in that data having a size larger than a data field is stored across a plurality of registers. And, data is restored from data stored across a plurality of registers, and arithmetic processing is performed on the restored data.

Based on the above points, the processor in Embodiment 6 will be described.

In addition, the same code|symbol is attached|subjected to the same component as Embodiment 5, and description is abbreviate|omitted.

FIG. 26 is a diagram showing the configuration of a processor according to Embodiment 6. FIG.

As shown in the figure, the processor 600 differs from the processor 500 in Embodiment 5 in the following points (1) to (3) (see FIG. 7 ).

(1) An instruction decoding circuit 601 is provided instead of the instruction decoding circuit 101 .

Compared with the instruction decoding circuit 101, the instruction decoding circuit 601 is different in that: when executing the operation instruction, the operation instruction decoding signal is not output to the flag value generating circuit 602.

(2) A flag value generating circuit 602 is provided instead of the flag value generating circuit 102 .

The flag value generation circuit 602 differs from the flag value generation circuit 102 in that it does not generate a flag value representing the attribute of data obtained by executing the arithmetic processing determined by the arithmetic instruction decode signal.

(3) A computing unit 620 is provided instead of the computing unit 520 .

Compared with the arithmetic unit 520 , the arithmetic unit 620 is different in that it includes a data attribute judgment circuit 621 and an arithmetic processing circuit 622 instead of the data attribute judgment circuit 521 and the arithmetic processing circuit 522 .

The data attribute judging circuit 621 reads out the flag value corresponding to the data determined by the operation instruction decoding signal from the register file 610, and judges the attribute of the data according to the read flag value. Then, the determination result is output to the arithmetic processing circuit 622 as a data attribute determination signal. Then, a tag value indicating the attribute of the data obtained by executing the arithmetic processing specified by the operation instruction decode signal is generated, and the generated tag value is stored in the register file 610 in association with the data obtained by executing the arithmetic processing.

The arithmetic processing circuit 622 reads the data determined by the decoding signal of the arithmetic instruction from the register file 610, and judges whether to convert the read data according to the data attribute judging signal. When the judgment result is conversion, the read data is converted according to the data attribute judgment signal, and the operation processing determined by the operation instruction decoding signal is performed on the converted data. Also, the data obtained by executing the arithmetic processing is stored in the register file 610 .

In addition, in the case of no conversion, the read data is not converted and the arithmetic processing is directly executed.

In addition, when data is stored in the register file 610 across a plurality of registers, the arithmetic processing circuit 622 restores the data from the data read from these registers, and executes arithmetic processing determined by the arithmetic instruction decode signal on the restored data. Also, the data obtained by executing the arithmetic processing is stored in the register file 610 across a plurality of registers.

Next, the configuration of the arithmetic unit in Embodiment 6 will be described as an example.

Here, the addition process is performed on the data stored across the register (Reg#0) and the register (Reg#1), and the data obtained by performing the addition process, that is, the result of the addition is divided and stored in the register (Reg#2 ) and register (Reg#3) as an example to illustrate.

FIG. 27 is a diagram showing a configuration of an arithmetic unit in Embodiment 6 as an example.

As shown in the figure, the data attribute judging circuit 621 reads the tag value from the tag field 611 of the register (Reg#0), and judges whether the data corresponding to the read tag value is across registers (Reg#0) according to the tag value read out. #0) and the data stored in the register (Reg#1). Then, a data attribute determination signal indicating that the data is stored across the register (Reg#0) and the register (Reg#1) is output to the selector 641, the adder 642, the selector 643, and the like.

In contrast, the selector 641 selects the data of the slave register (Reg#1) from the data output from the data field 612 of the register (Reg#0) and the data output from the data field 612 of the register (Reg#1). field 612 and output to adder 642.

In addition, the adder 642 makes the data output from the data field 612 of the register (Reg#0) the high-order part, and makes the data output from the selector 641, that is, the data output from the data field 612 of the register (Reg#1) the low-order part. part, and combine the high part and low part to restore the data. Then, addition processing is performed on the restored data, and the data obtained by performing the addition processing, that is, the addition result is divided into an upper part and a lower part, and each is output to the selector 643 . In addition, the lower part is stored in the data field of the register (Reg#3).

Further, the selector 643 selects the high-order part from the high-order part and the low-order part output from the adder 642 and stores it in the data field 612 of the register (Reg#2).

And, the data attribute judging circuit 621 generates a flag value about the result of addition in the adder 642, that is, a flag value indicating that it is data stored across the register (Reg#2) and the register (Reg#3), and The generated tag value is stored in the tag field 611 of the register (Reg#2).

Next, the operation of the processor 600 in Embodiment 6 will be described.

28 and 29 are diagrams showing operations of the processor according to the sixth embodiment.

As shown in FIGS. 28 and 29 , the processor 600 differs from the processor in Embodiment 5 in the following point (2).

(1) The operation when the load command is executed is the same as the operation (steps S111 to S114 , S121 to S122 , S521 to S522 ) in Embodiment 5, and therefore description thereof will be omitted.

(2) Regarding the operation when the operation command is executed, compared with the operation of Embodiment 5 (steps S131 to S135, S341 to S346, S541 to S544), there are the following differences (see FIG. 7, FIG. 24, and FIG. 28 , Figure 29.).

Instead of the operation of the instruction decoding circuit 101 in the fifth embodiment (step S131), the instruction decoding circuit 601 outputs an operation instruction decoding signal to the arithmetic unit 620 when the decoded instruction is an operation instruction (step S631).

In addition, instead of the operation of the flag value generation circuit 102 in Embodiment 5 (step S135), the arithmetic unit 620 associates the flag value indicating the attribute of the data obtained by performing the arithmetic processing in the data attribute judging circuit 621 with the data. stored in the flag field 611 of the register file 610 (step S641).

(3) The operation when the store command is executed is the same as the operation (steps S151 to S153 , S361 to S365 , and S561 to S562 ) in Embodiment 5, and therefore description thereof will be omitted.

According to the above-mentioned processor 600 of Embodiment 6, the register file 610 is provided with the flag field 611 and the data field 612, the arithmetic unit 620 is provided with the data attribute determination circuit 621 and the operation processing circuit 622, and the memory write control unit 530 includes a data attribute judgment circuit 531 and a data conversion circuit 532 .

Thus, data larger in size than the data field can be easily handled. In addition, since the data obtained by executing the arithmetic processing is added with a tag value indicating the attribute of the data, it is not necessary to specify the attribute of the data for the instruction executing the arithmetic processing, and the number of instructions can be reduced and the instruction decoding circuit can be simplified.

(other)

In addition, when the tag value generation circuit stores data read from the memory across a plurality of registers, it may generate a tag value including the number of registers the data is stored across, that is, the number of divisions of the data, and store it in the tag field. .

In addition, the processor can also be realized by full custom (full custom) LSI (Large Scale Integration). In addition, it can also be realized by a semi-custom (semi-custom) LSI such as ASIC (Application Specific Integrated Circuit). In addition, it can also be realized by programmable logic devices such as FPGA (Fild Programmable Gate Array) and CPLD (Complex Programmable Logic Device). In addition, it can also be implemented as a dynamic reconfigurable device whose circuit structure can be dynamically rewritten.

In addition, the design data forming one to two or more functions constituting the processor in these LSIs may be described in a hardware description language such as VHDL (Very high speed integrated circuit Hardware Description Language), Verilog-HDL, SystemC, etc. program (hereinafter referred to as HDL program). In addition, it may also be a gate-level netlist (netlist) obtained by logic synthesis of an HDL program. In addition, macrocell (macrocell) information to which configuration information, processing conditions, and the like are added to a gate-level netlist may be used. In addition, mask (mask) data defining size, timing, etc. may be used.

And, the design data can also be pre-recorded on an optical recording medium (for example, CD-ROM, etc.), a magnetic recording medium (for example, a hard disk, etc.), a magneto-optical recording medium (for example, MO, etc.), a semiconductor memory (for example, RAM, etc.) etc. in a computer-readable recording medium so that it can be read by hardware systems such as computer systems and internal systems. Moreover, the design data read by other hardware systems via the recording medium can also be downloaded to the programmable logic device via the download cable.

Alternatively, design data may be held in advance in a hardware system on a transmission path so that it can be acquired by another hardware system via a transmission path such as a network. Moreover, the design data obtained from the hardware system by other hardware systems through the transmission path can also be downloaded to the programmable logic device through the download cable.

Alternatively, design data for logic synthesis, configuration, and routing can also be pre-recorded in serial ROM so that it can be transferred to the FPGA at power-on. Furthermore, the design data recorded in the serial ROM can also be directly downloaded to the FPGA at power-on.

Industrial availability

The present invention can be used as a processor for processing data, especially a processor for performing media processing such as audio and image processing that requires high-speed and huge calculation processing.

Claims (14)

1. A processor, characterized in that it has: a register file with multiple registers; and a generation unit that generates a tagged value representing a data attribute, said registers have a data field holding data and a tag field holding said tag value, When executing a load instruction for loading from a memory to a register, the generation unit generates the tag value according to the load instruction, and stores it in the tag field. 2. The processor according to claim 1, characterized in that: The data field holds data output from the memory as it is by executing a load instruction that loads data from the memory into the register. 3. The processor of claim 2, wherein: the generation unit generates the tag value based on the address, data size and data type specified by the load instruction, The data type indicates whether the data to be transmitted is data with a code or data without a code. 4. The processor of claim 3, wherein: The processor is further provided with a conversion unit that converts the data held in the data field of the register according to the flag value. 5. The processor of claim 4, wherein: The converting unit performs zero-extension or code-extension on the data held in the data field of the register according to the flag value. 6. The processor of claim 5, wherein: The conversion unit performs the conversion when an instruction to read a register is executed. 7. The processor of claim 5, wherein: The conversion unit executes the conversion in an idle cycle when no reading and writing of the register according to the instruction occurs, and updates the flag field and the data field according to the conversion result. 8. The processor of claim 4, wherein: The conversion unit performs conversion when executing a store instruction to store data held in a data field of the register into a memory. 9. The processor of claim 8, wherein: The processor further has a write processing section for writing the data converted by the conversion unit into a memory through a write process corresponding to the flag value. 10. The processor of claim 2, wherein: When the processor executes a load instruction for reading data larger in size than the data field from the memory, the processor divides the data read from the memory and stores the divided data in two or more data fields. 11. The processor of claim 10, wherein: The generation unit stores a flag value including a division number of the divided data in a flag field. 12. The processor of claim 11, wherein: The processor includes an arithmetic processing unit, and when executing an arithmetic instruction that reads data stored in the data field of the register and performs arithmetic processing, combines and stores data in two or more data fields according to the number of divisions. data, restore the data, and perform operations on the restored data. 13. The processor of claim 12, wherein: The calculation processing unit stores the calculation processing result across two or more data fields when the size of the calculation processing result is larger than the data field, and associates a flag value indicating that the calculation result is stored across two or more data fields with the Corresponding to the above operation processing result, it is stored in the tag field. 14. The processor of claim 11, wherein: When the processor executes a storage instruction for writing data larger in size than the data field into the memory, it restores the data stored across two or more data fields, and writes the restored data into the memory.

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