JPH05324572A - Atomic-access-controlled register device - Google Patents

Abstract

(57) Abstract: A computer storage register architecture is disclosed that enables reliable atomic access to set or clear one or more specific bits in a multi-bit register. Configuration In the exemplary embodiment, many unique addresses are assigned to multiple bit registers. One address is a read address, one address is a clear address, and the third address is a set address. The address decoder decodes the address specified in a register so that only that register is accessed for associated read, clear, and set operations, respectively. Data having a register position equivalent binary pattern of logical zeros and those corresponding to particular bit positions in the register to be set or cleared are associated with the set or clear address. If the position equivalent binary value of the data associated with the decoded address is a logical one, the corresponding bit in the register is set or cleared. Otherwise the bit will remain unchanged.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to computer system hardware, and more particularly to the hardware architecture of controllers and status registers in computer system processors.

[0002]

Computer systems often utilize registers for temporary data storage or control purposes. Registers are typically configured to store multiple bits of information simultaneously, typically over 1 to 4 bytes. Data in the form of logical zeros and ones generated by a computer processor can be stored in a register and then reread by the processor. In controlling the operation of a computer, operating systems often need to modify a single bit in a set of bits stored in a multi-bit register without affecting the remaining bits. In such cases, the operating
The system performs a read-modify-write cycle whereby the CPU reads the information contained in the storage register, modifies the contents, and then writes the modified contents back to the register. Read / modify / write operations allow the processor to set or clear the bits of certain control parameters that are needed in subsequent data processing or calculation operations.

The execution of read / modify / write cycles is
Usually used in single processor systems. However, in a multiprocessor environment where more than one master device has equal opportunity to access the registers, one master may overwrite, modify, modify, or connect to the contents of a register previously stored by another master device. There is a substantial possibility that Briefly referring to FIG. 1, two processors sharing storage registers are shown,
Here, both processors are performing read / modify / write cycles in parallel on a single register. It can be seen from FIG. 1 that when master B completes its final write operation, master B invalidates master A's write operation. An important requirement of multiprocessor systems is that the information stored by a particular master cannot later be invalidated by another master. The state of the contents of a particular register is consistent with the master device that intended to have such contents stored in that register, which is known as "coherence." Coherence in a multiprocessor environment, where one or more masters have the opportunity to modify the information stored in the registers, is primarily a concern with cache memory architectures. In multiprocessor architectures incorporating cache memory, cache coherency for a particular master is especially important.

In the prior art, the main way to prevent the cache coherence problem is to call a so-called "mutually exclusive lock" as shown in FIG. A mutual exclusion lock is a semaphore that acquires the ownership of a signal or flag that allows only the accessing master to communicate with and control a specific register before the specific master is accessed by software. Mutual exclusion locks are generally called by the master performing a swap operation with hardware registers containing flags. The master reads the contents of the flag and then partially loads the register with a non-zero value. At that time, both read and write operations are performed such that another master cannot read or write to the register during the exchange operation. The master next tests the value of the contents read from the register during the exchange, that is, if the register contents are equal to "0", the lock was "free" and the master writes some non-zero register contents. If they are equal, the lock can be declared not "free" and the master is denied to use it. The master generally continues the replacement and test operation until the test value indicating the lock is "free" is "0". The lock is released by the master controlling the lock writing a "0" to the flag register. For example, as shown in FIG. 2, the lock is set when the master performs a swap operation and the master stores some non-zero value <lock_busy>. Next, the master uses the value of the content previously stored in the lock register as the reference value <l
test for ock_free>. If the previously stored content is equal to <lock_free>, the master determines that it is the owner of the lock.

[0005]

The control of a mutual exclusion lock allows a processor to access a register and store information without fear that the stored information may later be corrupted by an unexpected access by another processor. You can do it. Furthermore, only the master who claimed the lock by setting the flag can unlock the lock by clearing the flag. Mutual exclusion locks are well known in the art and there are several software algorithms that provide the locking function. In a multiprocessor system, there are many such mutual exclusion locks, and operating system software frequently uses such locks to determine when important code is executed or when important registers are accessed. Is shown. However, the use of mutual exclusion locks requires significant additional processing time as well as additional code space to provide the locking function. For speed-critical operations, using multiple locks can substantially impede or degrade system performance. As will be described below, the present invention eliminates the need for the time-intensive software interlock mechanism provided in the prior art to store data stored in system storage registers in a multiprocessor environment with a master. A simple register architecture that ensures coherence between is disclosed. Further, the present invention allows one or more individual bits of a shared register to be accessed and modified during direct activity without the need for software interlocks as in the prior art.

[0006]

SUMMARY OF THE INVENTION The present invention provides a method and apparatus for a register structure in a multi-processor environment in which the processor protects against unintended access of an atomic access register by the wrong master while providing soft software. Atomically access a shared register to set or clear one or more specific bits in the register without a wear interlock. Multiple unique addresses are assigned to the multi-bit atomic access register. In the exemplary embodiment, three addresses are assigned to each atomic access register. One address is the clear address, the second address is the set address, and the third address is the read address. Each address is different from all other addresses. The address decoder decodes the address specified in each atomic cache register when the processor issues a register access instruction. When decoded by the address decoder, each address points to the same physical register and the two addresses point to "pseudo registers". Data having a position-equivalent binary pattern of logical zeros and the equivalent of specific bit positions in the physical register to be set or cleared are associated with the set and clear addresses respectively. No data is associated with the read address. Each bit in the atomic access register is set, cleared, selected, system
It is formed by a flip-flop having a clock input and an output enable. The select input for a particular flip-flop is activated according to the position equivalent binary data associated with the decoded address. If the data corresponding to the particular bit to be modified is a logic one, then the flip-flop containing that data bit in the register is selected.
Once selected, the bit is set or cleared depending on whether the address associated with the register containing the selected bit is a set or clear function, respectively. The remaining bits of the physical register accessed are also modified according to the remaining position equivalent binary data associated with the address accessing the corresponding pseudo register. The output enable of each flip-flop of the register sends the contents of each bit of the register to the accessing processor when the issued address is a read address.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a multiprocessor computer system, each processor atomically accesses a shared register to set or clear one or more specific bits without the need for software interlocks. Disclose the architecture. Although the following description sets forth specific numbers, times, signals, etc. for purposes of explanation in order to provide a thorough understanding of the present invention, those of ordinary skill in the art will be able to practice the invention without those specific details. It will be clear. In other instances, well-known circuits and devices are shown in block diagram form in order not to unnecessarily obscure the present invention. The present invention can be implemented in many embodiments. Two specific embodiments are described in detail below, but it will be apparent that many other embodiments will give the same results. It is envisioned that a storage register architecture incorporating the teachings of the present invention may be implemented anywhere within a computer system. As preferred herein, the registers that allow bits to be set or cleared are implemented within the interrupt steering architecture. The present invention can be used with any multiprocessor computer system, but is intended to function with a multiprocessor computer manufactured by Sun Systems, Inc. of Mountain View, California. The present invention that describes the following, the continuation application listed above, in particular "dynamic steering undirected interrupts"
It is intended to work with a continuing application number in the name of.

Referring now to FIG. 3, there is shown a block diagram showing two atomic access registers. However, in any particular multiprocessor computer system design, any number of atomic access registers may be implemented. In FIG. 3, the multi-bit register 10 is formed in a known manner. Register 10 has multiple individual bits
It is formed by 15. There is no practical limit to the number of bits 15 contained in register 10, register 10
Typically contains as many bits as a computer system bus (not shown) can accommodate. In the exemplary embodiment, register 10 is 32 bits wide. Associated with register 10 are multiple addresses 25. As shown in FIG.
ADDR0, ADDR4, ADDR8 of each address
All refer to register 10. Address 25, when executed by a processor (not shown) and decoded by an address decoder (not shown), registers with the processor.
Allow access to 10. The processor and address decoder are formed as is generally known in the art. It is important to note that the activity on register 10 depends on which address 25 is executed by the processor. The details of register 10 also depend on how the decoder is implemented. Although a specific address value has been assigned to address 25 for purposes of illustration, how each address is unique, decodable, and consistent with the overall system architecture within the invention It will be appreciated that any address value will work.

The activity on the individual bits 15 that make up register 10 is controlled by the data 27 associated with each address 25 when the address instruction is executed by the processor. In particular, each bit 16 in register 10 can be represented by a position equivalent bit 28 of the binary representation of data 27 associated with a particular address 25 in the address instruction executed by the accessing processor. That is, the position equivalent bit 28 position within the binary data equivalent of the data 27 associated with the particular address 25 being executed controls whether the physical bit 16 within register 10 is actuated. Associated data in controlling individual bit 15 in register 10 27
The operation of address 25 associated with is described in more detail in the following sections. Still referring to FIG. 2, the address 25 assigned to perform a read operation on register 10 is ADDR.
It is 0. When executed by the processor and decoded by the address decoder, ADDR0 points to register 10 and the processor causes all bits contained in register 10 to be
Read 15 data. Since bit 15 in register 10 is not modified during a read operation, there is no data 27 associated with address 25 when address 25 is assigned to do the read. The address assigned to perform the clear operation is ADDR4. ADDR4, when executed and decoded by the processor, also points to register 10.
However, unlike the ADDR0 address associated with a read operation, the ADDR4 address is associated with data 27 masking bit 15 to clear. The processor then sets the specific bit 15 of register 10 to the data 27 associated with ADDR4.
Clear according to the binary position equivalent bit 28, which is equivalent to. If position equivalent bit 28 is a logical one, bit 16 corresponding to position equivalent bit 28 is set to a logical zero. Bit 16 remains unchanged if position equivalent bit 28 is a logical zero. The address 25 assigned to perform the final setting operation is ADDR8. When executed by the processor and decoded, ADDR8 also points to register 10. As in the case of ADDR4 above, data 27
Is associated with the address ADDR8. The processor sets each bit 16 of register 10 according to position equivalent bit 22 which is the binary equivalent of data 27 associated with address ADDR8. If position equivalent bit 22 is a logical one, bit 16 corresponding to position equivalent bit 22 is set to a logical one.
If position equivalent bit 22 is a logical 0, then bit 16 remains unchanged.

The activity on the individual bits 17 that make up register 11 is controlled by the data 27 associated with each of the addresses 26 when the address instruction is executed by the processor. In particular, each bit 18 in register 11 contains a specific address 26 that is executed by the accessing processor.
Position equivalent bit 29 of the binary representation of the data 27 associated with
Can be expressed as That is, the specific address to be executed
The binary data equivalent position of the data 27 associated with 26 The position of the equivalent bit 29 controls whether the physical bit 18 in register 11 is actuated. The operation of address 26 associated with associated data 27 in controlling individual bits 17 in register 11 is described in further detail in the following sections. Still referring to FIG. 3, the address 26 assigned to perform a read operation on register 11 is ADDRC. When executed by the processor and decoded by the address decoder, the ADDRC points to register 11 and the processor reads all bits 17 of the data contained in register 11. When address 26 is assigned to do a read, there is no data 27 associated with address 26 because bit 17 in register 11 is not modified during the read operation. The address assigned to perform the clear operation is ADDR
Is 10. Once executed and decrypted by the processor,
Points to ADDR 410 register 11. However, unlike the ADDRC address associated with a read operation, ADDR10
The address is associated with data 27 that masks bit 17 to clear. The processor then clears specific bits 17 of register 11 according to the binary equivalent position equivalent bit 29 of data 27 associated with ADDR 10. If position equivalent bit 29 is a logical one, bit 18 corresponding to position equivalent bit 29 is set to a logical zero. Bit 17 remains unchanged if position equivalent bit 29 is a logical zero. The address 26 assigned for the last setting operation is A
It is DDR14. When executed and decoded by the processor, ADDR 14 also points to register 11. ADD above
As in R10, data 27 is associated with address ADDR14. The processor sets each bit 18 of register 11 according to the binary equivalent position equivalent bit 23 of data 27 associated with address ADDR14. If the position equivalent bit 23 is a logical one, the bit 18 corresponding to the position equivalent bit 23 is set to a logical one. If the position equivalence bit 23 is a logical 0, then bit 18 remains unchanged.

Referring now to FIG. 4, a block diagram illustrating an implementation of the N-bit atomic access register 12 is shown. In FIG. 4, the flip-flop 30 of the register 12 stores the "nth" bit. The flip-flop 30 has four inputs of “setting”, “clear”, “select”, and “clock”. Associated with register 12 is address decoder 35. The address decoder 35 is a hardware decoder having a known design and implemented in a known manner,
Has "Read Enable (RD-EN)", "Write Enable (WR-EN)" inputs to receive the appropriate inputs for the address lines as well as a signal indicating that a valid read or write operation is in progress. There is. The address decoder 35 has two settings, "setting" and "clear", which are connected to the settings of the flip-flop 30, the clear input and the setting of each flip-flop including the register 12, and the clear input.
Have two inputs. The read output of address decoder 35 is connected to the output enable (OE) inputs of flip-flop 30 and all flip-flops that make up register 12. The output enable is asserted during the address cycle associated with register 12 and while there is an appropriate signal from the processor (not shown) indicating that a read operation is taking place. As shown in FIGS. 3 and 4, the select input of flip-flop 30 is derived from data 27 associated with address 25, and in particular the position equivalent binary representation of data 27 associated with flip-flop 30. The clock inputs of flip-flop 30 and address decoder 35 are taken from the system clock signal distributed within the computer.

In operation, when the address decoder 35 determines that the address appearing on the address line corresponds to the register 12 controlled by the address decoder 35, the address decoder 35 determines by the data 27 associated with the address 25. Set or clear individual read bits to 0 as
To N. In the particular application to register 12 shown in FIG. 4, the select inputs to flip-flop 30 are decoded as shown in FIG. 3 to address ADDR4 and ADD, respectively.
It is activated by the "nth" position equivalent bits 28 and 22 in the data 27 associated with R8. All bits 0 to N are read when a read command is issued with the address ADDR0. As explained in the previous section, the set or clear atomic access architecture disclosed in the present invention essentially implements a "pseudo register" function for registers constructed in accordance with its teachings. It should be recalled that a pseudo register generally refers to a virtual non-physical storage location. The pseudo register can be identified by an address other than the address assigned to the physical register that actually stores the target data. Thus, even if there is only one physical register in the hardware, the physical register can be identified by multiple addresses that allow the register to perform multiple functions.

Referring now to FIG. 7, a specific example of addresses and associated data that controls the reading, setting and clearing of register bits will be described. FIG. 7 shows the addresses and data associated with the read and write commands. Further, FIG. 7 shows the final register contents of the specific register (not shown) designated by the address. For purposes of illustration in FIG. 7, registers are assumed to be 4-bit registers. In FIG. 7, the binary data forming the contents of the 4-bit register is initially an arbitrary combination of 1 and zero. Suppose it is initially desired to clear all bit positions in the register. To clear the bits in the register, the operating system writes to the register using the address or ADDR4 assigned to the write-clear operation described above with respect to FIG. According to the present invention, which associates a particular binary position in a physical register with the equivalent bit position of a binary data value, when the position equivalent bit of the binary representation is set to a logical one,
A specific bit is selected. Therefore, to clear all bit positions in the register, all 4 bit positions must be selected. Selecting all four bits requires setting all position equivalent binary bits in the data representation to logic ones. For a 4-bit register, the binary data expression is "1111". Binary 1111
Is equivalent to F in hexadecimal notation. Therefore, to clear all bit positions in the 4-bit register, the composite instruction executed by the control processor is WRT ADDR4
It becomes FH.

Assume the next operation to be performed is to set a particular bit in the register. Further, it is assumed that the set bit is the most significant bit. A binary representation of "1000" is required to set the most significant bit in the register. From FIG. 3 and the above description, the address associated with the setting command is the address ADDR8. Therefore, when setting the most significant bit of a register, the composite instruction is WRT
It becomes ADDR8 8H. Further assume that the next operation is to set the second least significant bit from the bottom in the register. The address set here is also ADDR8.
Address ADD by setting the second least significant bit from the bottom
The data associated with R8 will be data equal to "0010" to 2H. Therefore, the synthetic instruction to set the second least significant bit from the bottom in the register is WRT ADDR8.
It becomes 2H. Here, it is assumed that the contents of the register are read. The read address from the above description shown in FIG. 3 is the address ADDR0. Notably, there is no data associated with the read command because the operating system expects to receive the data from the register it is reading. Therefore, the instruction to read the register is RD ADDR0. Executing a read command causes the register contents to appear at the read input of the processor requesting the read. Next, suppose that the most significant bit is cleared. Therefore, the write-clear address ADDR4 that selects the most significant bit is executed. The most significant bit is achieved by writing data that selects the fourth bit position, binary 1000. Therefore, the synthetic instruction for clearing the most significant bit is WRTADDR48H. Finally, it is desired to reread the contents of the register. As mentioned above, the read command is the address ADDR.
No data associated with 0 is required. Therefore, the synthesis instruction is RD ADDR0. For each instruction executed according to the above example, FIG. 4 shows the final contents of the register following each operating step.

As explained in the previous section, a key attribute of the present invention is that it is possible to avoid unintended access to registers by an unintended processor during a multi-step instruction cycle. Thus, in a multiprocessor computer system, coherence between data stored in the processor and registers stored in the processor shared by the multiple processors is maintained. Functionally, by selecting one of the addresses 25 and 26, which points to physical registers 10 and 11, respectively.
Activities within 10 and 11 are decided. That is, all addresses 25 associated with register 10 operate only in register 10, thus ensuring coherence of the data stored in register 10 for a particular processor. Register 10 is only accessed by the processor executing the address which, when decoded, ties the processor to register 10. The uniqueness of the function can be obtained analogously in the register 11 by the address 26. Thus, the unique register address provides a sufficient selection of registers that can be accessed by multiple processors while avoiding the coherence problems encountered in the prior art.

Another important attribute of the present invention is that individual bits in the register can be set or cleared atomically without the need for multi-step read / modify / write cycles. The present invention uses a mask of the actual bits of a physical register to set or clear individual bits of a position equivalent binary data pattern. It obviates the need for cumbersome code spaces and time intensive software interlock schemes to maintain data coherence between the master and the data stored by the master.

Those skilled in the art will appreciate that a read instruction can be implemented by using a write-set address or a write-clear address with an appropriate readable signal issued by the processor. Whether to read using three separate addresses as in the first embodiment or one of the write addresses to read is entirely at the discretion of the designer. In previous 1st generation (ie 4-bit) processors, the address space was limited, and so were all large valued addresses. In modern 32-bit and higher processors, address space is typically allocated in blocks to devices, which far exceeds the expected number of discrete addresses. So either build a two address atom access register or
Constructing a three-address atomic address register is entirely a matter of designer preference. The choice of 3 address implementation versus 2 address implementation will of course impact the design of the address decoder. Referring now to FIG.
A second embodiment of the invention of atomic access to registers is shown. In FIG. 8, register 40 is a multi-bit register constructed as described above. The single address 45 only points to register 40. Associated with address 45 is that its binary equality is the individual bit in register 40.
The data 47 provides a mask for setting or clearing 41. In this second embodiment, a single bit of register 40
42 is shown as a flag indicating whether the operation is a set or clear command. The bits that perform this flag function may be any of the bits contained in register 40. The remaining bits store the data in the normal way. As shown in FIG. 8, in the second embodiment, the most significant bit 42 is used as a flag, where 1 indicates that the operation sets the bit and 0 indicates that the bit is cleared. Therefore, implementing the atomic access register according to this second embodiment will set or clear one bit less than the previous embodiment. That is, in the atomic access register formed of N bits, the atomic access register of the first and second embodiments sets or clears N bits, whereas the second embodiment sets N-1 bits of the register. Set or clear. A write command to register 40 with the binary equivalent most significant bit 48 of data 47 associated with an address instruction equal to a logical one causes the remaining bits of the binary equivalent of data 47 to be contained in individual bits 41 contained in register 40. Will be interrupted as a bit mask that sets On the other hand, if the binary equivalent most significant bit 42 of the data 47 issued by the write instruction is a logical 0, the remaining binary equivalent bits will be interrupted as a bitmask that clears the individual bits of register 40. .. In the second embodiment, the state of the most significant bit 42 is meaningless for read operations.

[Brief description of drawings]

FIG. 1 illustrates a coherence problem encountered in the prior art where a multiple master environment may result in overwrite or unintentional modification of registers.

2 shows a prior art solution to the coherence problem shown in FIG. 1 in which a software mutual exclusion lock prevents a master from accessing a particular register being accessed by another master.

FIG. 3 illustrates an embodiment of the invention in which three separate addresses are assigned to each physical atomic access register, each address carrying an associated bit mask.

FIG. 4 illustrates a flip-flop set, clear, read address select line in an atomic access register.

FIG. 5 is a logical table of an address decoder used in the embodiment of the present invention.

FIG. 6 is a logic table of a flip-flop including an atomic access register.

FIG. 7 illustrates an example of atomic access to registers for read and write operations.

FIG. 8 illustrates a second embodiment of the present invention, where a single address is assigned to each physical, atomic access register, but the atomic function is controlled by a single bit in the associated bitmask.

[Explanation of symbols]

10, 11 ... Register, 25, 26 ... Address, 27 ... Data, 28 ... Position equivalent bit.

Claims (3)

[Claims] 1. A computer system having a number of processors connected to a bus, and register means comprising a plurality of control registers each connected to the bus for storing a plurality of bits, each control register being identified by a plurality of addresses. Connecting to the bus and the register means to access the bits stored in the control register,
1 of the address issued by a particular processor
A specific processor which receives only an address instruction consisting of one address and a data value and changes only a specific bit of a specific control register in accordance with the data value and the address contained in the address instruction. Access control register device comprising addressing means connected according to the above. 2. A computer system having a number of processors connected to a bus, the computer system being connected to the bus for storing digital data, each associated with a plurality of addresses and having a plurality of storage locations. The register means comprises a plurality of control registers for storing a plurality of bits, and address means including an address decoding means connected to the bus and the register means for accessing the bits stored in the control register. This address means is issued by a specific processor,
The address decoding means is configured to receive an address command consisting of one of the plurality of addresses corresponding to a specific control register and a data value having a storage location equivalent binary data representation composed of a bit mask, and the address decoding means includes the one of the plurality of addresses.
And the specific processor is connected to the specific control register addressed by the specific processor, the addressing means further comprising: the storage location equivalent binary data representation of a data value included in an address instruction. Only a specific bit of the specific control register is modified according to the formed bit mask, and only the specific bit in the specific control register addressed by a specific processor is atomically accessed and modified according to the bit mask. Atomic access control register device. 3. A computer system having a large number of processors connected to a bus, provided with register means composed of a plurality of control registers for storing a plurality of bits, each control register being identified by a plurality of addresses, Address means for accessing the bits stored in the register are provided, and an address instruction consisting of one of the addresses and a data value is provided, and the address means is used to connect a specific processor to a specific control register according to the address. Then, the atomic access register control method comprising the step of changing only specific bits of the specific control register according to the address included in the address instruction.