JPH04184788A - Semiconductor memory apparatus - Google Patents

Abstract

PURPOSE:To achieve a shortening of writing time by causing a shortcircuiting between a bit line at one port and a bit line at the other port when a word line of a memory cell is accessed simultaneously from both the ports with a writing at the one port for the memory cell. CONSTITUTION:It is detected with a detection circuit 4 that line addresses coincide at both ports with a writing at one port for a certain memory cell. In other words, the detection circuit 4 outputs a detection signal Sd when every word line on both the port sides connected to the memory cell is accessed. Then, a bit line BL subjected to a writing is caused to shortcircuit with a bit line BL' opposite in port connected to the bit line BL through a transfer gate with a first shortcircuit circuit 5 while the detection signal Sd is applied. Thus, the transfer gates are connected in parallel and a synthetic resistance thereof is a half of a resistance portion of one transfer gate thereby enabling the shortening of required time for writing.

Description

[Detailed Description of the Invention] (Summary) The present invention relates to a semiconductor memory device that is capable of independently writing and reading data to and from a specific memory cell in a memory cell matrix from multiple ports such as dual ports for each port. 2. To reduce the write time by preventing data write speed from decreasing even when one port is in a write state for a specific memory cell and both ports access the word line of the memory cell at the same time.
The purpose of the present invention is to provide a semiconductor memory device capable of detecting a predetermined detection signal by detecting that word lines on both port sides are being driven when one port is in a writing state for a specific memory cell. and a first shorting circuit for shorting a bit line on one port side and a focus line on the other port side in the memory cell based on the detection signal. Or,
a detection circuit that detects that lead wires on both ports are driven when one port is in a writing state for the memory cell and outputs a predetermined detection signal; 1 on the other port side of
and a second shorting circuit for shorting the paired bit lines.

[Industrial application field]

The present invention relates to a semiconductor memory device capable of independently writing and reading data to and from a specific memory cell in a memory cell matrix from a plurality of ports such as dual ports for each port.

The above-mentioned semiconductor memory device having dual ports is also called a dual-port RAM, and has the following features not found in a RAM having only a single port. Firstly, data can be accessed faster because one port can be used to write data while the other port can be used to read data.Secondly, two similar systems In some cases, the dual-port RAM can be shared, allowing data to be exchanged quickly between the two systems.

The present invention refers to a semiconductor memory device that can be used in a high-speed system by utilizing the characteristics of the dual-port RAM and the like described above.

[Conventional technology]

FIG. 8 is a diagram showing an example of a conventional semiconductor memory device.

However, here, a dual-baud RAM having a memory cell matrix 1 configured by arranging a plurality of memory cells in a row direction and a column direction is shown as a representative semiconductor memory device. Furthermore, only two memory cells 1-1.1-2 among the memory cells described above are illustrated.

In FIG. 8, one memory cell is composed of a flip-flop circuit consisting of two inverters and four transfer gates. Furthermore, two types of ports (A port and B port) each having a word line and a pair of bit lines for selecting a specific memory cell in the memory cell matrix 1 are provided. To explain in more detail, a word line WL on the A port side and a word line WL' on the B port side are arranged for each row of the memory cell matrix 1, and these words fIsWL, WL' are connected to the upper and lower two lines in the memory cell. are connected to the respective transfer gates. Therefore, if these word lines WL, WL' are selected and driven by an external control signal, a specific transfer gate becomes conductive and a row address of a memory cell is specified. - On the other hand, a pair of bit lines BL, TT on the A port side and a pair of bit lines BL', ■r' on the B port side are arranged for each column of the memory cell matrix 1, and these bit lines The lines B L , 'r, B L ' and D'r' are connected to the flip-flop circuits of the memory cells via transfer gates. Furthermore, the bit lines BL and TT on the A port side and the bit line BL on the B port side
Column select circuits 2 and 2' are provided for driving each of ' and TU'.

This column select circuit 2.2' is composed of a plurality of switch elements connected to each bit line, and selectively drives the switch elements by a column select signal Scm, which is a type of control signal from the outside. This specifies the column address of a particular memory cell. Furthermore, the column select circuit 2.2' is provided with a signal amplification section 3.3' consisting of a write amplifier and a sense amplifier necessary for data write and read operations, respectively. The above-mentioned memory cell 1.2 types of ports, column select circuits 2, 2', and signal amplification sections 3, 3' constitute the main part of a dual-port RAM.

In this conventional dual-port RAM, data can be written to any memory cell by independently driving the word line and bit line at each port, A port and B port (however, data can be written to any memory cell at the same time). (writing is prohibited) and reading is possible. In this case, data writing is performed by the signal amplifying section 3.
This is done by inputting desired data from a write amplifier in 3' to a specific memory cell via a bit line.

On the other hand, data reading is performed by detecting the potential difference between a pair of bit lines by a sense amplifier in the signal amplifying section 3.3'.

[Problem to be solved by the invention]

As mentioned above, when writing and reading data to a specific memory cell in a conventional semiconductor memory device such as a dual-port RAM, the word line and bit line on each port side of the two types of ports are driven independently. The configuration is such that the specific memory cell is selected for each port.

Therefore, if one port is in the write state and the row addresses of the memory cells selected by both ports match,
That is, when data is written to one memory cell from one port (for example, A port) and the word lines on both port sides are accessed, all the transfer gates of the memory cell are in a conductive state. . Therefore, when writing data, part of the current flows from the bit line on the A port side to the bit line on the other port (eg, B port) side via the transfer gate. In particular, when the B port is in a read state and it is necessary to invert the data in the memory cell using the bit line on the A port side, the potential of the bit line on the B port side must also be inverted, and this potential inversion The drive current for this must also be supplied from the A port side. Generally, the transfer gate of a memory cell is composed of an MO3 type transistor that has a large resistance even in the conductive state, so the capacitance between the bit line on the B port side and ground cannot be ignored, and the potential of the bit line on both port sides increases. The time constant until reaching a steady state tends to become longer.

As a result, a problem arises in that the time required to write data becomes longer than usual and the writing speed decreases.

The present invention has been made in view of the above-mentioned problems, and it is possible to simultaneously access the word line of the memory cell from both ports while one port of the dual port is in a writing state for a specific memory cell in a memory cell matrix. It is an object of the present invention to provide a semiconductor memory device that can prevent data write speed from decreasing and shorten write time even when data is written.

[Means to solve the problem]

FIG. 1A and FIG. 1B are block diagrams showing the first principle configuration and the second principle configuration, respectively, of the present invention. however,
Here, only one memory cell 1-1 in memory cell matrix 1 is illustrated. Further, components similar to those described above are denoted by the same reference numerals.

As shown in FIG. 1A, according to the first principle of the present invention, the present invention has a dual port for selecting a specific memory cell in a memory cell matrix, and a word line and a bit line at each port of the dual port. In a semiconductor memory device in which data is written to and read from the memory cell by independently driving each port, word lines on both port sides are driven when one port is in a write state for the memory cell. a detection circuit 4 that detects that the memory cell is present and outputs a predetermined detection signal S4, and short-circuits the bit line on one port side and the bit line on the other port side in the memory cell based on the detection signal S4. A first short circuit 5 is provided.

On the other hand, as shown in FIG. 1B, according to the second principle of the present invention, there is provided a dual port for selecting a specific memory cell in a memory cell matrix, and a word in each port of the dual port is provided. In a semiconductor memory device that writes and reads data to and from the memory cell by independently driving a bit line and a pair of bit lines for each port, when one port is in a write state for the memory cell, both ports a detection circuit 4 that detects that the word line is being driven and outputs a predetermined detection signal Sd;
A second shorting circuit 6 is provided for shorting the pair of bit lines on the other port side of the memory cell based on the detection signal S4.

[For production]

In the first principle of the present invention shown in FIG. 1A, when one port is in a write state for a specific memory cell, the detection circuit 4 detects that the row addresses of both ports match. That is, this detection circuit 4 outputs the detection signal Sd when both word lines connected to the memory cell on both port sides are being accessed.

Furthermore, during the period when this detection signal Sd is output, the bit line BL in the writing state and the bit line BL' of the opposite port connected to this bit line BL via the transfer gate are first shorted. A short circuit is made by circuit 6. In this way, since the transfer gates are connected in parallel, their combined resistance will be half of the resistance meter of one transfer gate, and the time constant until the potential of the bit line on both ports reaches a steady state will be It is much shorter than before.

As a result, the time required for writing is significantly reduced.

The same thing can be said about the bit line r' of the port opposite to another bit line in the writing state.

On the other hand, according to the second principle of the present invention shown in FIG. 1B, during the period when the detection signal S4 is output from the detection circuit 4, the bit lines BL and TT in the write state are connected to a pair of pins at the opposite port. ) mBL' and r' are short-circuited by the second short circuit 6. If you do this, 1 of the opposite port
Paired bit line BL'.

Since T'IT' has the same potential, this bit line BL'
.

Since the influence of the writing state of digitr' on the bit lines BL and digitr can be almost ignored, the time required for writing is shortened.

Thus, in the present invention, in a semiconductor memory device such as a dual port RAM, one port is in a write state for a specific memory cell in a memory cell matrix, and the word line of the memory cell is simultaneously accessed from both ports. Even in such cases, it is possible to shorten the writing time and respond to faster system speeds.

〔Example〕

FIG. 2 is a circuit diagram showing an embodiment (hereinafter abbreviated as the first embodiment) based on the first principle configuration of the present invention. However, here, dual port R as a semiconductor memory device is used.
The main parts of AM are shown below. Furthermore, two memory cells 1-1.1-2 in the memory cell matrix 1 constituting this dual port RAM are shown as representatives.

In FIG. 2, a column select circuit 2-1.2-2 is provided which is composed of a plurality of switch elements for driving a pair of bit lines of the memory cell 1-1 in the first column.

Further, a column select circuit 2-2, 2'-2 is provided which is made up of a plurality of switch elements for driving a pair of bit lines of the memory cell 1-2 in the 0th column. A column address is designated by selecting these switch elements using a column select signal S cs and making them conductive.

Further, the signal amplifying section 3.3' connected to the column select circuit includes a write amplifier 13 for data writing.
, 13' and a sense amplifier for reading data 23'.
．． 23'. Here, before explaining the first short circuit 5 and the detection circuit 4, which are the constituent elements of the present invention, the overall structure of the dual port RAM will be described.

FIG. 3 is a block diagram showing the overall configuration of the dual baud RAM. However, the constituent elements of the present invention are omitted here. Furthermore, each circuit block on the A port side of the dual port RAM will be explained as a representative.

In FIG. 3, an address buffer 8 is provided on the A port side for outputting address signals A0 to A1 indicating the row address and column address of a specific memory cell in the memory cell matrix l. Furthermore, the address signal A mentioned above. −
A row decoder 9 for decoding A and specifying the row address of the memory cell, and a column decoder 20 for specifying the column address are provided. Furthermore, an address change detection circuit (Address T
transition Detector (hereinafter abbreviated as ATD) 19, and this.

A precharge circuit 29 is provided to precharge the bit line to be selected based on the detection result of the ATD 19. Further, data writing to a specific selected memory cell is started every time a write enable signal WE is supplied from an external control circuit to the row decoder 9, column decoder 20, etc. via the write buffer 7. When the write enable signal WE is input to the row decoder 9, a specific word line is accessed by the row select signal from the row decoder 9. On the other hand, when the write enable signal WE is input to the column decoder 20, the column select signal Scs from the column decoder 20 selectively turns on the switch elements in the column select circuit 2, so that a specific bit line is Driven.

Signal waveforms when writing and reading data in the dual port RAM are shown in FIGS. 4 and 5, respectively.

In FIG. 4, twc indicates the predefined pulse width of the address signal during data writing ((a) in FIG. 4), and the signal level changes to "H" in response to changes in the address.
(High) or “L” (Low). next,
tl indicates a period during which the write enable signal WE is at the signal level "L", and data can be written during this period. Furthermore, since the signal level of the write enable signal WE needs to be "HII" when the address signal changes, the rising timing of the write enable signal WE must be defined by twr ((b) in FIG. )) Furthermore, td, , indicates the minimum writing time required to write data after the address is determined, and tab indicates the retention time of the written data (see Fig. 4). (C)).On the other hand, in Fig. 5, trc indicates the predefined pulse width of the address signal at the time of reading data ((a) in Fig. 5), and then tma It shows the minimum period required from when the address is determined until the data can be read, and t6 shows the retention time of the read data ((b) in Figure 5). ).Next, the specific configurations of the first short circuit 5 and the detection circuit 4 in the first embodiment (FIG. 2) of the present invention will be explained in detail.

Referring again to FIG. 2, the first short circuit 5 (first A
Figure) shows the bit lines BL on both port sides at the left end of memory cells 1-1, 1-2 in each column.

A switch circuit 15 consisting of a switch element for short-circuiting BL' and a switch element for short-circuiting bit lines m and w' on both port sides at the right end of each memory cell.
-1 and 15-2. Furthermore, as the detection circuit 4 (FIG. 1A) of the present invention, the switch circuit 15
An arbitration circuit 40 is provided that generates a detection signal S4 for controlling conduction/non-conduction of 15-1 and 15-2.

To explain in more detail, this arbitration circuit 4
As shown in FIG. 6, 0 is constituted by an address/number construction circuit 14 and an inhibition gate circuit 24, each consisting of a combination of a plurality of logic elements. Above address-number configuration circuit 1
4, the address signals A, ~A, from the A port are compared with the address signals 〇'~A+m'' from the B port, and when the row addresses indicated by both address signals match, the word lines on both port sides are "H" as it is being accessed
Outputs a match signal. Furthermore, the above-mentioned prohibition gate circuit 2
4 outputs a detection signal S of "H" when the write enable signal WE of one port is active ("L"), that is, when one port is in the write state.

This "H" detection signal S4 turns on the switch element of the column select circuit selected by the column address (for example, the column select circuit 2-1 in the first column).

In this state, the bit line BL selected by one port in the writing state, for example, the A port, and the bit line BL' of the B port connected via the transfer gate of the memory cell selected by the A port. and the switch circuit 15-1
short circuit. Similarly, another bit line Ding UjJT'
also short circuit each other. On the other hand, when the B port is in the write state, the above relationship is reversed.

According to the first embodiment (Fig. 2), the combined resistance of the transfer gate is much smaller than the conventional one (Fig. 8) by shorting the bit lines on both port sides. Even when the line is being accessed, the write time tdw (FIG. 4) is short. Therefore, the write time tdw can be significantly shortened and the system can be made faster.

FIG. 7 shows an example (hereinafter referred to as the second embodiment) based on the second principle of the present invention.
FIG. 2 is a circuit diagram illustrating an example.

In this case, a second short circuit 6 (see FIG. 1A) is used instead of the first short circuit 5 (see FIG. 1A) in the first embodiment (FIG. 2).
(see Figure 1B). The circuit configuration other than the second short circuit 6 is the same as that of the first embodiment.

Furthermore, in FIG. 17, the second short-circuit circuit 6 includes a switch element for short-circuiting between a pair of bit lines at the A port of the memory cells 1-1, 1-2 in each column, and In order to bring the potential between the bit lines to zero when Here, the row addresses of both ports match, and the write enable signal W of one port, for example, port A, is
Arbitration circuit 4 indicates that E is active.
0, the pair of bit lines B L' and TT' of the B port connected via the transfer gate of the memory cell selected by the A port are short-circuited to have the same potential. . On the other hand, when the write enable signal of the B port is active, the above relationship is reversed.

According to the second embodiment (FIG. 7), when one port is in the writing state, a pair of bit lines of the other port are set at the same potential, so that the capacitance between these bit lines to ground can be ignored. As a result, the writing time L4'w (FIG. 4) can be shortened similarly to the first embodiment (FIG. 2), and the speed of the system can be increased.

〔Effect of the invention〕

As explained above, according to the present invention, dual port) R
In a semiconductor memory device such as an AM, when one port is in a writing state for a specific memory cell and the word line of the memory cell is accessed from both ports simultaneously, the bit line of one port and the other port The write operation of one port is shorted by shorting the bit lines of the other port, or by shorting a pair of bit lines of the other port, thereby reducing the write time and increasing the system speed. will be realized.

[Brief explanation of drawings]

Fig. 1A is a block diagram showing the configuration of the first principle of the present invention, Fig. 1E is a block diagram showing the configuration of the second principle of the present invention, and Fig. 2 shows an embodiment based on the first principle of the present invention. Circuit diagram, Figure 3 is a block diagram showing the overall configuration of dual baud RAM, - Figure 4 is a timing chart showing signal waveforms during writing, Figure 5 is a timing chart showing signal waveforms during reading, - Figure 4 is a timing chart showing signal waveforms during reading. FIG. 6 is a diagram showing details of an example of an arbitration circuit, FIG. 7 is a circuit diagram showing an embodiment based on the second principle of the present invention, and FIG. 8 is a diagram showing an example of a conventional semiconductor memory device. be. In the figure, l...Memory cell matrix, 2.2'...Column select circuit, 3.3'...Signal amplification section, 4...Detection circuit, 5...First short circuit, 6・
...Second short circuit, 40...Arbitration circuit. Figure 1B is a block diagram showing the first principle configuration of the present invention. Figure 1B is a block diagram showing the second principle configuration of the present invention.

Claims (1)

[Claims] 1. It has a dual port for selecting a specific memory cell in the memory cell matrix (1), and the word line and bit line in each port of the dual port are independently driven for each port. In a semiconductor memory device that writes and reads data to and from the memory cell, when one port of the memory cell is in a write state, it is detected that word lines on both port sides are driven, and a predetermined state is detected. A detection circuit (4) outputting a detection signal (S_d) of
), and a first shorting circuit (5) for shorting the bit line on one port side and the bit line on the other port side in the memory cell based on the detection signal (S_d). A semiconductor storage device. 2. It has a dual port for selecting a specific memory cell in the memory cell matrix (1), and the word line and the pair of bit lines in each port of the dual port are independently driven for each port. In a semiconductor memory device that writes and reads data to and from a memory cell, when one port of the memory cell is in a write state, it is detected that lead wires on both port sides are being driven, and a predetermined detection signal is generated. A detection circuit (4) that outputs (S_d)
); and a second shorting circuit (6) for shorting a pair of bit lines on the other port side of the memory cell based on the detection signal (S_d). .