CN1908927A - Reconfigurable integrated circuit device - Google Patents

Abstract

A reconfigurable integrated circuit device which is dynamically constructed to be an arbitrary operation status based on a configuration data, has a plurality of clusters including operation processor elements, a memory processor element, and an inter-processor element switch group for connecting the elements in an arbitrary status; an inter-cluster switch group for constructing data paths between the clusters in an arbitrary status; and an external memory bus. A direct memory access control section, for executing the data transfer between the memory processor element and the external memory by direct memory access responding to an access request from the memory processor elements of the plurality of clusters, is further provided.

Description

reconfigurable integrated circuit device

technical field

The present invention relates to reconfigurable integrated circuit devices, and more particularly, to a novel configuration of an internal memory mounted in a reconfigurable integrated circuit device for performing data transfer to and from an external memory.

Background technique

A reconfigurable integrated circuit device includes a plurality of processor elements and a network for interconnecting these processor elements, wherein the sequencer provides configuration data to the processor elements and the network in response to external or internal events, and according to the configuration data , using processor elements and networks to configure arbitrary computing states or computing circuits. A conventional programmable microprocessor reads instructions stored in memory sequentially and processes them sequentially. Since the number of instructions that a processor can execute at the same time is limited, the processing power of the microprocessor is also limited to some extent.

On the other hand, in recently proposed reconfigurable integrated circuit devices, ALUs with functions such as adders, multipliers, comparators, etc., and various processor elements such as delay circuits, counters, etc. are preinstalled and used to connect these A network of processor elements is also installed, and then, based on configuration data from a state transition control unit with a sequencer, the plurality of processor elements and network are reconfigured to the desired configuration, and in the operational state Next, execute the predetermined operation. When data processing in one operation state is completed, another operation state is constructed based on other configuration data, and different data processing is performed in this state.

By dynamically constructing different operation states in this way, the data processing capability for a large amount of data can be improved, and the overall processing efficiency can be improved. Such a reconfigurable integrated circuit device is disclosed, for example, in Japanese Patent Application Laid-Open No. 2001-312481.

Contents of the invention

In a conventional reconfigurable integrated circuit device, an array of multiple processor elements is surrounded by switches connected between the processors, and a state transition control unit provides configuration data to the processor elements and switch banks to set arbitrary computing states. In the group of processor elements, data is input from an external memory, the group of processor elements set in an operation state performs predetermined data processing on the input data, and the data thus obtained is output.

In the above-mentioned integrated circuit device, the data required for data processing is read in batches from the external memory and stored in the internal memory, and then set to a certain operation state of the processor element group and the switch group for reading All data performs data processing.

However, reconfigurable integrated circuit devices utilize a dynamically configured predetermined number of processor elements to execute different applications. Therefore, each processor element needs to write or read a required amount of data to or from the external memory at a required timing. In the prior art, data is transferred via a data path using a switch group connecting processor elements, and data transfer with an external memory is only possible at predetermined timing.

In addition, a predetermined number of internal memories for storing data read from or to be written to an external memory are mounted for a plurality of processor elements, but the operation state to be configured by the user is variable, so It is difficult to estimate how much internal memory is required and what kind of input/output characteristics the internal memory requires. Therefore, in the reconfigurable integrated circuit device, the configuration and operation of the internal memory need a high degree of flexibility.

In view of the above reasons, it is an object of the present invention to provide a reconfigurable integrated circuit device which allows highly flexible configuration and operation of the internal memory.

To this end, a first aspect of the present invention is a reconfigurable integrated circuit device that is dynamically constructed into an arbitrary operational state based on configuration data, the device comprising: a plurality of clusters comprising a plurality of Arithmetic processor element with calculation unit, memory processor element with memory for data transfer with external memory, and interprocessor element switch group for connecting arithmetic processor element and memory processor element in any state an inter-cluster switch group for constructing a data path between clusters in any state; and an external memory bus for performing data transfers between a memory processor element and an external memory, wherein the arithmetic processor element, the memory processor elements, inter-processor element switch groups, and inter-cluster switch groups are dynamically changed based on configuration data, and a direct memory access control component is provided that responds to access requests from multiple clusters of memory processor elements , data transfers between the memory processor element and the external memory are performed by direct memory access.

According to the first aspect, the memory processor elements installed in the cluster can transfer data to and from the external memory through direct memory access via an external memory bus different from the inter-cluster switch group, and can perform operation after reconfiguration At the timing of the state, the reconfigured operation is performed on the data in the external memory.

In the first aspect of the present invention, preferably, said cluster further comprises a configuration data memory for storing said configuration data, and a sequencer responsive to The end signal from the processor element outputs the configuration data for constructing the next operation state from the configuration data memory.

In the first aspect of the present invention, preferably, the reconfigurable integrated circuit device further includes a data flow control unit installed as a common unit of the plurality of memory processor elements for Direct memory access requests from the plurality of memory processor elements are accepted and simultaneous direct memory access requests are indicated to direct memory access control means for the plurality of memory processor elements.

In the first aspect, preferably, the reconfigurable integrated circuit device further includes a data flow control unit installed as a common unit of the plurality of memory processor elements for receiving data from all direct memory access requests of the plurality of memory processor elements, and indicate simultaneous direct memory access requests to direct memory access control means for the plurality of memory processor elements. Through the data flow control section, access requests from the plurality of memory processor elements can be executed synchronously.

In the first aspect, said memory processor element further comprises an inner interface to an internal bus connected to said inter-processor element switch bank, and an outer interface to said external memory bus, wherein said While the memory processor element accesses the external memory by direct memory access via the external interface, the arithmetic processor element accesses the memory processor element via the internal interface. According to this aspect, data transfer between the external memory and the arithmetic processor element can be seamlessly performed.

In the first aspect, it is also preferred that the memory processor element accepts data transfer with the arithmetic processor element while performing data transfer with the external memory by direct memory access, when the data transfer by direct memory access asserting a stall signal to stop operations of the plurality of arithmetic processor elements when unable to keep up with data transfers to and from the arithmetic processor elements, and deasserting the stall signal when able to catch up. According to this aspect, when seamless data transfer cannot be performed between the external memory and the arithmetic processor element, the arithmetic processor element's operation may be stopped to avoid erroneous operations.

To achieve this object, a second aspect of the present invention is a reconfigurable integrated circuit device that is dynamically configured to a predetermined operational state based on configuration data, the device comprising: a plurality of clusters, the clusters comprising computing units The operation processor element of the computer, the memory processor element with memory for data transmission between the external memory, and the inter-processor element switch group for connecting the operation processor element and the memory processor element in any state; inter-cluster a switch bank for constructing a data path between clusters in an arbitrary state; and an external memory bus for performing data transfer between a memory processor element and an external memory, wherein the arithmetic processor element, the memory processor element , inter-processor element switch groups and inter-cluster switch groups are dynamically changed based on configuration data, and a direct memory access control unit is provided that responds to access requests from memory processor elements of multiple clusters through direct memory access to perform a data transfer between a memory processor element and an external memory, the memory processor element including first and second memory banks, wherein when one of the first and second memory banks is passing through the direct memory When accessing and performing data transmission with the external memory, the other one of the first and second memory banks performs data transmission with the arithmetic processor element.

According to the second aspect, seamless data transfer between the external memory and the arithmetic processor element can be performed at arbitrary timing via an external memory bus different from the inter-cluster switch group.

According to the present invention, the memory processor element installed in each cluster enables data transfer by direct memory access to external memory independent of the data path between the clusters, thereby increasing the memory capacity in reconfigurable integrated circuit devices. The flexibility of the processor element to perform data transfers, and the data transfers can be done efficiently.

Description of drawings

FIG. 1 is a block diagram illustrating a cluster constituting a part of the reconfigurable integrated circuit device according to the present embodiment;

FIG. 2 is a schematic diagram illustrating a configuration example of a PE network element according to the present embodiment;

3 is a schematic diagram illustrating a configuration example of a circuit configured according to configuration data of a PE network element according to the present embodiment;

4 is a schematic diagram illustrating a configuration example of a circuit configured according to configuration data of a PE network element according to the present embodiment;

FIG. 5 is a block diagram illustrating a reconfigurable integrated circuit device according to the present embodiment;

FIG. 6 is a block diagram illustrating an example of a memory processor element according to the present embodiment;

7A-7C are schematic diagrams describing switching operations of two memory banks (memory banks) in the memory processor element according to the present embodiment;

8A-8C are schematic diagrams describing switching operations of two memory banks in the memory processor element according to the present embodiment;

9A-9C are schematic diagrams describing switching operations of two memory banks in the memory processor element according to the present embodiment;

10A-10C are schematic diagrams describing switching operations of two memory banks in the memory processor element according to the present embodiment;

11A-11C are schematic diagrams describing switching operations of two memory banks in the memory processor element according to the present embodiment;

FIG. 12 is a block diagram illustrating a control section of the memory processor element according to the present embodiment;

FIG. 13 is a state transition diagram of the control part of the memory processor element according to the present embodiment;

14A-14B are schematic diagrams describing the flag change control of the access end register;

15A-15B are schematic diagrams describing the external interface in the memory PE; and

FIG. 16 is a schematic diagram describing the external interface in the memory PE.

Detailed ways

Embodiments of the present invention will now be described with reference to the accompanying drawings. However, the technical scope of the present invention shall not be limited to these embodiments, but extend to the contents of the claims and their equivalents.

FIG. 1 is a block diagram of a cluster constituting a part of the reconfigurable integrated circuit device according to the present embodiment. The cluster 10 comprises: a sequencer SEQ for performing state management; a configuration data store 14 for storing configuration data CD; and a processor element network part 16 to be configured in an arbitrary circuit configuration according to the configuration data CD. In the configuration data storage 14, the configuration data CD is loaded from a configuration data loading section (not shown).

The processor element network part 16 includes: a plurality of processor elements (hereinafter often referred to as PEs) PE0-PE5; a switch 20 among PEs, and this group of switches is a selector for connecting PEs; and an input port part 22 and an output port Components 24, which are interfaces for data transmission with other clusters. The input port section 22 and the output port section 24 are connected to an intercluster switch group 30 . According to the example in Fig. 1, the processor elements PE0-PE3 are all arithmetic PEs, and each has an ALU, an adder, a comparator inside. The processor element PE4 is another PE, such as a delay circuit or a counter, and the processor element PE5 is a memory PE with RAM inside.

Configuration data CD0-CD5 are provided to processor elements PE0-PE5 from a configuration data store 14 and the configuration data are stored in registers (not shown) in these PEs. The circuits in each PE are dynamically configured based on the configuration data CD0-CD5 set in these registers. Likewise, configuration data CD is also provided from the configuration data store 14 to the inter-PE switch bank 20 and based on this data the required internal switch bank structure is configured and the data paths between the PEs are dynamically configured. The inter-cluster switch group 30 is also dynamically configured based on the configuration data CD, and the data paths between the clusters are also configured.

The memory processor element PE5 in the cluster can perform data transmission with each of PE0-PE4 via the inter-PE switch group 20 . Therefore, the memory processor element PE5 is connected to the internal bus I-BUS. The memory processor element PE5 can directly perform data transmission with the external memory E-MEM via the external buses E-BUS1 and E-BUS2. directly on the bus. Therefore, the memory processor element PE5 can directly perform data transfer with the external memory E-MEM, and also can perform data transfer at a timing independent of the inter-cluster data path operation.

Each end signal CS0-CS5 is output from each processor element PE0-PE5 respectively, and the switching signal generating section 12 outputs the switching signal SW1 based on these end signals. In response to the switching signal SW1, the sequencer SEQ outputs a new address Add and a switching signal SW2 to the configuration data memory 14, and in response thereto, new configuration data is output and the circuit configuration in the PE network part 16 is reconfigured.

FIG. 2 is a schematic diagram showing a configuration example of PE network components according to the present embodiment. The arithmetic processor elements PE0-PE3, the memory processor element PE5, and the other processor element PE4 can be connected via a selector 41 (one switch in the inter-PE switch group 20). In this configuration, each processor element PE0-PE5 can be configured as any configuration based on the configuration data CD0-CD5, and the selector 41 of the inter-PE switch group 20 can also be configured as any configuration based on the configuration data CD .

As illustrated in the lower right corner of Figure 2, the selector 41 includes: a register 42 for storing configuration data CD; a selector circuit 43 for selecting an input according to the data of the register 42; and a flip-flop 44 connected to the clock CK The output of the selector circuit 43 is latched synchronously.

FIG. 3 and FIG. 4 are schematic diagrams illustrating circuit configuration examples configured according to configuration data of PE network components according to the present embodiment. In FIGS. 3 and 4 , the arithmetic processor elements PE0-PE3 and PE6 of the dynamically configurable arithmetic circuit are connected by an inter-PE switch group 20 and configured as a dedicated arithmetic circuit performing predetermined arithmetic at high speed. The processor element PE6 is not shown in FIGS. 1 and 2 .

The example in FIG. 3 is an example when a dedicated operation circuit that performs the following arithmetic expressions on input data a, b, c, d, e, and f is configured.

(a+b)+(c-d)+(e+f)

According to an example of this configuration, the processor element PE0 is configured as an A=a+b operation circuit, the processor element PE1 is configured as a B=c-d operation circuit, the processor element PE2 is configured as a C=e+f operation circuit, and the processing The processor element PE3 is configured as a D=A+B arithmetic circuit, and the processor element PE6 is configured as an E=D+C arithmetic circuit. Each of the data a to f is supplied from a memory processor element and an external cluster (not shown), and an output of the processor element PE6 is output as an operation result E to the memory processor element and the external cluster.

The processor elements PE0, PE1 and PE2 perform operations in parallel, the processor element PE3 performs the operation D=A+B on the above operation results, and finally the processor element PE6 performs the operation E=D+C. In this way, the parallel operation is realized by configuring the dedicated operation circuit, thereby improving the operation processing efficiency.

Each arithmetic processor element has a built-in ALU, adder, multiplier, and comparator, and can be reconfigured into an arbitrary arithmetic circuit based on configuration data CD. By configuring as shown in FIG. 3, it is possible to configure a dedicated operation circuit for performing the above-mentioned dedicated calculation. And by configuring such a dedicated computing circuit, multiple operations can be executed in parallel, thereby improving computing efficiency.

The example of FIG. 4 is an example when a dedicated operation circuit performing (a+b)*(c-d) operation on input data a to d is configured. The processor element PE0 is configured as an A=a+b operation circuit, the processor element PE1 is configured as a B=c-d operation circuit, and the processor element PE3 is configured as a C=A*B operation circuit, and the operation result C is output to the memory Processor elements or external clusters. In this case, too, the processor elements PE0 and PE1 perform operations in parallel, and the processor element PE3 performs the operation C=A*B on its operation results A and B. Therefore, by configuring a dedicated operation circuit, the above-mentioned operation efficiency can be improved, and also operation efficiency for a large amount of data can be improved.

FIG. 5 is a block diagram illustrating a reconfigurable integrated circuit device according to the present embodiment. In FIG. 5, a plurality of clusters CLS0-CLS3 are installed, and inter-cluster switch groups 30 for connecting these clusters are arranged between these clusters. By configuring the inter-cluster switch group 30 according to the configuration data CD, an arbitrary arithmetic circuit combining a plurality of clusters can be dynamically configured.

In the example of FIG. 5, memory processor elements PE-RAM are installed in each of the clusters CLS0-CLS3. In a cluster, multiple or no memory processor elements may be installed as appropriate. These memory processor elements are connected to the direct access control section DMAC via the external bus E-BUS1, and perform data transfer with the external memory E-MEM by direct memory access via the access control section DMAC. As for the external memory E-MEM, for example, DDR-SDRAM (Double Data Rate Synchronous DRAM) is used as an example of a high-speed memory. In addition, a common data flow control section 40 is installed for a plurality of memory processor elements PE-RAM. Each memory processor element issues an access request DR0-DR3, and in response to the access request, the data flow control section 40 sends an access command to the control section DMAC, thereby performing data transfer by DMA with the memory processor element that sent the access request.

The data flow control section 40 accepts access requests from a plurality of memory processor elements, and synchronously performs DMA data transfer between the plurality of memory processor elements and an external memory. In other words, the access control section DMAC synchronously performs DMA data transfer with a plurality of memory processor elements in a round-robin manner based on the access command ACMD from the data flow control section 40 .

In this way, the memory processor element in the cluster transfers data from the external memory E-MEM by DMA, the data will be processed by the arithmetic circuit configured by the arithmetic processor element in the cluster, and the processed data is DMAed Transfer to external memory E-MEM. This DMA transfer is performed directly by the external buses E-BUS1 and E-BUS2 independent of the intercluster switch group 30 for connecting the clusters. Therefore, in the reconfigurable integrated circuit device, even if the connection structure of the inter-cluster switch group 30 is dynamically changed, it is possible to pass through a path independent of the inter-cluster switch group 30 at the timing required by each memory processor element. to perform data transfers between each memory processor element and external memory, and can implement optimal data transfers for dynamically configured clusters or for multiple clusters.

FIG. 6 is a block diagram illustrating an example of a memory processor element according to the present embodiment. In order to realize the seamless data transfer between the external memory and the arithmetic processor element in the cluster, the memory processor element includes a first memory bank BNK0 and a second memory bank BNK1, and also includes between these memory banks and the inter-PE switch group 20 The inner interface 50 between these memory banks and the outer interface 52 between these memory banks and the external bus E-BUS1. Memory banks BNK0 and BNK1 each include four 16-bit wide RAMs. The inner interface 50 is connected to the internal bus I-BUS connected to the inter-PE switch group 20, and is dynamically configured into different input/output bus interface structures based on the configuration data CD. The outside interface 52 is connected to the external bus E-BUS1, and is also dynamically configured into different input/output bus interface structures based on the configuration data CD. Details about the structure of the input/output bus interface to be configured will be described later.

In the first memory bank BNK0 and the second memory bank BNK1, when one memory bank is performing data transmission with the internal arithmetic processor element PE/ALU, the other is performing data transmission with the external memory E-MEM, and the two memory banks The library can also alternately perform data transfers. Therefore, selectors SEL are installed between the memory banks BNK0, BNK1 and the inner interface 50, the outer interface 52, and these selectors SEL are set according to the configuration data CD. Thus, the first and second memory banks may be alternately connected to the inner and outer interfaces. The signal lines between interfaces 50 and 52 and each memory bank BNK0 and BNK1 include 16-bit data lines, address lines and all other necessary control lines.

The memory processor element includes: a memory control unit 54 for controlling switching of memory banks and controlling DMA requests; and an operation control unit 56 for performing operation control on the internal arithmetic processor element PE/ALU. The memory control section 54 monitors the state of the memory bank, and performs switching control of the memory bank, DMA request, and assertion and cancellation of the stall signal STR for stopping the operation of the arithmetic processor element, thereby realizing external memory and internal arithmetic processing Seamless data transfer between device components. In response to this stall signal STR, the arithmetic control section 56 controls the start and stop of the operations of the arithmetic processor elements.

7A-7C and FIGS. 8A-8C are schematic diagrams describing switching operations of two memory banks in the memory processor element of the present embodiment. In FIGS. 7A-7C and FIGS. 8A-8C, two memory banks BNK0, BNK1 and an access end register END-REG are shown in the memory processor element PE/RAM, wherein the access end controller is controlled by the memory control unit 54( See Figure 6) used to control the switching of memory banks. There are two access end registers END-REG in which flags indicating the access states of the first and second memory banks are respectively stored, for example, when the memory access ends and an end signal is received, the flag is set to the end state " 0", and when the memory bank enters the access enable state (ready), the flag is set to the ready state "1". By monitoring these two register values, the memory control section 54 (see FIG. 6) controls switching of the two memory banks BNK0 and BNK1.

Operation after initial start-up will now be described with reference to Figure 6, Figures 7A-7C and Figures 8A-8C. At startup, the sequencer SEQ outputs the address corresponding to the initial startup after reset is cleared, and the configuration data for the initial startup is output from the configuration data memory 14 (FIG. 6), the processor elements PE and PE in the cluster The inter-switch bank 20 is configured as an initial circuit configuration. By this initial start, an initial value is set in the access end register END-REG, as shown in FIG. 7A. In this example, the register of the first memory bank BNK0 is in the ready state (flag is "0"), and the register of the second memory bank BNK1 is in the access end state (flag is "1"). With this initial activation, the selector SEL is configured such that the first memory bank BNK0 is connected to the outside interface 52 and the second memory bank BNK1 is connected to the inside interface 50 .

After the initial startup, the memory control section 54 refers to the access end register, and outputs an access request DMAR to the external memory. As described above, the access request DMAR is sent to the direct memory access control section DMAC via the data flow control section 40 (FIG. 5), and direct data transfer between the external memory E-MEM and the first memory bank BNK0 is started. Specifically, data read from the external memory E-MEM is directly transferred and written to the first memory bank BNK0 via the external bus. As described above, the access request DMAR at the time of initial start-up is output from a plurality of memory processor elements, so data transfer using a plurality of direct memory accesses is performed synchronously.

Then, as shown in FIG. 7B, when the data transfer from the external memory E-MEM to the first memory bank BNK0 ends, the DMA control part DMAC sends the access end signal END1, and in response to this, the corresponding access end register END-REG The bit in the first memory bank becomes the access end state (flag "1"). In this way, when both registers become the access end state (flag "1"), the memory control section 54 issues the state end signal CS, causing the sequencer SEQ to output the next address Add and causing the configuration data memory 14 to output the new The configuration data CD for switching the first memory bank BNK0 and the second memory bank BNK1. In other words, the second memory bank BNK1 is connected to the outside interface 52 , and the first memory bank BNK0 is connected to the inside interface 50 .

Then, as shown in FIG. 7C, when the two memory banks are switched, the memory control section 54 clears the access end register END-REG, thereby setting both memory banks to the ready state (flag "0"). In response to this state, the memory control section 54 outputs an access request DMAR to the external memory, based on which the DMA control section DMAC controls data transfer between the external memory E-MEM and the second memory bank BNK1. The access control DMAR in this case is issued at the timing at which the memory processor element needs access, which is different from the initial start-up, so data transfer is performed as needed. At the same time, the memory control part 54 outputs a signal ALU-EN indicating that the internal arithmetic processor element can be executed, and in response thereto, the arithmetic control part 56 outputs an operation start signal ALU-ST to the internal arithmetic processor element PE/ALU, And the operation processing of the operation processor element is started. Then, the internal arithmetic processor element PE/ALU accesses the first memory bank BNK0, reads data, and performs arithmetic processing on the read data.

Then, as shown in FIG. 8A, when the data transfer between the second memory bank BNK1 and the external memory E-MEM ends, in response to the access end signal END1, the access end register END-REG is set to the access end state (flag " 1"). Typically, direct memory access to and from external memory has a wider data bus width, and therefore is a high-speed data transfer, and ends before data transfer to and from the internal arithmetic processor element.

As shown in FIG. 8B, the access from the internal arithmetic processor element PE/ALU is also ended, and another flag of the access end register END-REG is also set to the access end state (flag "1") by the access end signal END2. In response thereto, memory control section 54 outputs state end signal CS, and replaces connections between first memory bank BNK0 and second memory bank BNK1 and the inside and outside interfaces based on configuration data CD output from configuration data memory 14 .

As shown in FIG. 8C , the memory control unit 54 outputs a direct memory access request DMAR again to start data transfer between the first memory bank BNK0 and the external memory E-MEM, and the operation control unit 56 outputs an operation start signal ALU-ST and starts to transfer data from the first memory bank BNK0 to the external memory E-MEM. Access from the internal arithmetic processor element PE/ALU to the 2nd memory bank BNK1.

As described above, by alternately switching the first and second memory banks, the memory control section 54 realizes seamless data transfer from the external memory E-MEM to the internal arithmetic processor element. Specifically, direct memory access to and from external memory is faster than access to internal OP elements, so the OP elements can read and process data seamlessly.

9A-9C are diagrams describing switching operations of two memory banks in the memory processor element according to the present embodiment. Controls in case of problems with seamless data transfer will be described here. Since the direct data transfer with the external memory is performed at high speed, usually one memory bank finishes the data transfer with the external memory before the other memory bank finishes the data transfer with the internal computing PE. When the data transfer with the internal computing PE is completed, memory bank switching control is performed, so that seamless data transfer between the external memory and the internal computing PE can be realized. However, due to some reasons, in some cases, the data transmission with the internal computing PE is completed first.

As shown in FIG. 9A, if the data transfer from the first memory bank BNK0 to the internal operation PE ends first, the access end register END-REG is set to the access end state (flag "1") by the end signal END2. In response to this, the memory control section 54 asserts a stall signal STR to the operation control section 56, whereupon the operation PE array temporarily stops its pipeline processing. In other words, when the data cannot be read from the memory PE, the pipeline processing of the operation PE array cannot be performed, and the operation processing starts to have a problem.

As shown in FIG. 9B, when the data transfer of the second memory bank BNK1 is completed, the access end register END-REG is set to the access end state by the end signal END1. Then, the memory control section 54 outputs the state end signal CS, and switches the memory banks according to the configuration data CD. Then, as shown in FIG. 9C, the memory control unit 54 outputs an access request DMAR, so that the first memory bank BNK0 starts data transmission with the external memory, cancels the pause signal STR, and restarts the operation of the internal computing PE array, so, The second memory bank BNK1 starts data transmission with the internal computing PE.

In this way, the dedicated arithmetic circuit is configured, and the data arithmetic processing is pipelined, so when the memory control section 54 monitors the access states of the two memory banks and the seamless transfer of data is prohibited, the memory control section 54 asserts a stall Signal STR to stop the pipeline processing of the internal operation PE. In this way, possible problems with pipelining can be avoided. When seamless transfer is enabled, the memory control section 54 cancels the stall signal STR, and resumes pipeline processing.

10A-10C and 11A-11C are schematic diagrams describing switching operations of two memory banks in a memory processor element. This is an example when performing data transfer from the internal operation PE to the external memory E-MEM via the memory PE.

In FIG. 10A, the operation PE writes data to the first memory bank BNK0. In FIG. 10B, when data writing is completed, both access end registers END-REG become access end states (flag "1"). In response to this, the memory control section 54 outputs a state end signal CS, and switches the two memory banks based on the configuration data CD. As shown in FIG. 10C, the first memory bank BNK0 starts the direct data transfer with the external memory through the access request DMAC, and starts the data writing from the operation PE to the second memory bank BNK1 through the operation start signal ALU-ST to the operation PE. .

Then, as shown in FIG. 11A , the data transfer of the first memory bank BNK0 is completed first, and the data writing of the slave operation PE is completed as shown in FIG. 11B . Then, the memory control section 54 switches the two memory banks, and the data transfer of the exchanged memory banks respectively starts as shown in FIG. 11C.

As described above, data transfer from the operation PE to the external memory is also performed seamlessly via the memory PE. If the seamless data transmission is disabled midway, the pause signal STR is canceled, the arithmetic PE array stops the pipeline processing, and restarts the pipeline processing when the data transmission is enabled.

FIG. 12 is a block diagram describing a control section of the memory processor element according to the present embodiment. Fig. 13 is a state transition diagram of its control components. In the example of FIG. 12, the memory unit 60 in the same cluster has a plurality of memory processor elements RAM-PE0˜PEn, and the array PE/ALU array of the arithmetic processor elements is configured to be connected with the memory processor elements RAM-PE0˜PEn. corresponds to each of the . Each memory PE includes a bank switch control section 541 and a DMA transfer execution judgment section 542 as the memory control section 54 , and also has an ALU operation execution judgment section 561 as the operation control section 56 . A plurality of memories PE share the ALU operation control section 562 as the operation control section 56 , and the DMA transfer control section 543 is provided as the memory control section 54 . The first memory bank BNK0 and the second memory bank BNK1 in the memory PE are configured to alternately perform data transfer with the access control part DMAC via the external bus, and alternately communicate with the arithmetic processor via the inter-PE switch group PE-SW in the cluster. The element array PE/ALU array performs data transmission.

The control flow will be described below with reference to the state transition diagram in FIG. 13 . As mentioned above, the first memory processor element RAM-PE is enabled and configured to the desired circuit configuration based on the configuration data CD (C10). By the activation, the access end register END-REG is set to an initial value flag by which the memory bank becomes the initial state (C12).

During the operation after the memory processor element RAM-PE starts, the bank switching control part 541 controls the switching (C12) of the memory bank according to the state of the access end register END-REG (both flags "1"), thereby switching the memory bank (C14). When the memory bank is switched, the circuit configuration of the computing PE can be converted accordingly (C12, C14).

When the memory bank is switched, the DMA transfer execution judgment part 542 judges whether the data transfer to the external memory is possible, and if the data transfer can be executed, the DMA transfer execution judgment part 542 outputs to the DMA transfer control part 543 installed outside the memory PE DMA transfer enable signal DMA-EN (C16). Whether or not data transfer is possible depends on the status of the access end register END-REG indicating the status of the memory bank. The corresponding DMA transfer control part 543 outputs an access request to the access control part DMAC via the data flow control part 40 (not shown, see FIG. 5) (C18), and data transfer is performed (C20). When the data transfer with the external memory ends, the DMA transfer control section 543 receives the data transfer end signal END1 , and the data transfer end signal END10 is sent to the bank switching control section 541 . Then, the above-mentioned bank switching control is executed according to the state of the access end register END-REG (C12).

On the other hand, when the memory bank is switched, the ALU operation execution judgment part 561 monitors the state of the memory bank based on the access end register END-REG, and judges whether access from the operation PE is possible, that is, whether the operation PE can perform operation processing (C22). If execution is possible, the ALU operation execution judging section 561 outputs an operation execution enable signal ALU-EN.

Only when the operation execution enable signal ALU-EN is received from all memory processor elements RAM-PE0～PEn, the ALU operation control part 562 outputs the operation start signal ALU-ST to all operation PE arrays in the cluster (C24), And make all computing PE arrays execute computing processing synchronously (C26). In other words, a plurality of operation PE arrays in the cluster must perform pipeline processing synchronously while performing data transfer with a plurality of memory PEs, so one ALU operation control part 562 is installed as a common part of a plurality of memory PEs, and only when from When all memory PEs receive the operation execution enable signal ALU-EN, the ALU operation control unit 562 outputs the operation start signal ALU-ST to multiple operation PE arrays. The ALU operation execution judging unit 561 monitors the state of the memory bank, and if the data transfer cannot be performed seamlessly, the ALU operation execution judging unit 561 asserts a pause signal STR, and stops the pipeline processing of the arithmetic PE array. The pause signal STR is as described above.

When the operation processing is completed, the access to the memory bank on the operation PE side ends, and upon receiving the end signal END2 from the operation PE, the ALU operation execution judging section 561 cancels the operation execution enable signal ALU-EN. Through the end signal END2, the flag state of the access end register END-REG is changed, the memory bank is switched or the configuration change of the operation PE is controlled and executed accordingly (C12, C14).

In FIG. 13, the state transition of the dotted line shows the state transition of the memory PE, the left side shows the state of the DMA transfer control unit 543 and the direct memory access control unit DMAC, and the right side shows the ALU operation control unit The 562 sums the state of the PE array.

In FIGS. 12 and 13, the DMA transfer control section 543 outputs a DMA request based on the DMA transfer enable signal DMA-EN output by the DMA transfer execution judgment section 542, but the DMA transfer control section 543 may check the Channel status, so as to judge whether the DMA transfer can be performed, that is, whether the execution timing of the DMA transfer is appropriate, and if appropriate, output a DMA request. In this way, when the number of channels of the direct memory access control part DMAC exceeds a predetermined number and the timing is not suitable for sending a DMA request, sending of a DMA request can be stopped until the number of channels becomes a predetermined number or less, and the DMA transfer timing can be It is delayed. The DMA transfer enable signal DMA-EN is generated according to the state of the access end register END-REG, so this control of delayed DMA transfer timing is important.

In FIG. 13, when the operation of the arithmetic processor element array ends (C26), new configuration data is output from the sequencer, and the configuration data of the arithmetic PE is changed (C12). Configuration data is switched when necessary.

14A-14B are diagrams describing flag change control of the access end register. FIG. 14A shows flag change control when the memory bank BNK0/1 is connected to the inside (operation PE array side). The address Add for access is supplied to the memory bank BNK from the arithmetic PE array side, and the corresponding access is performed. This access address Add is also supplied to the comparator 70 in the memory control section 54 . The end address E-Add to be accessed when the circuit is configured based on the configuration data has been set in the comparator 70 in advance. Every time the address valid signal Valid (the signal indicating whether the address attached to the access address is valid) becomes valid, the comparator 70 compares the access address Add and the end address E-Add, and if they match, the access end register END-Add The flag of REG becomes "1".

As another control method, the flag of the access end register END-REG may be changed to end state "1" in response to the end signal END2 from the operation PE array. In either case, when the inside and outside memory banks are switched, the flag of the access end register END-REG is set to the ready state "0".

FIG. 14B shows flag change control when the memory bank 0/1 is connected to the outside (external memory E-MEM side). In this case, the access address Add is provided from the access control section DMAC. In response to the end signal END1 from the access control part DMAC, the memory control part 54 changes the flag of the access end register END-REG into the end state "1", and when the inside and outside of the memory bank were switched, the memory control part 54 responded to The switching end signal END-SW sets the flag of the access end register END-REG to the ready state "0".

Also, the end state of the access end register END-REG is cleared by reset and set to the ready state.

15A-15B and 16 are schematic diagrams describing external interfaces in the memory PE. The outside interface 52 is connected to the external bus E-BUS1, and is dynamically configured into different input/output bus interface structures based on the configuration data CD. Generally, the external bus E-BUS1 for direct memory access has a wider bus width. For example, when the external memory E-MEM is a 32-bit DDR-SDRAM, data is output twice in one clock cycle, so the bus width of the external bus E-BUS1 is 64 bits. In this case, the circuit of the outside interface 52 is configured such that 64-bit data is input in parallel to or output from the four 16-bit RAMs in the memory bank BNK in parallel.

FIG. 15A shows the outside interface when the bus width of the external bus E-BUS1 is 16 bits. As described above, 64-bit data is input to or output from four 16-bit RAMs in parallel.

Figure 15B shows the situation when the bus width is 32 bits, the interface is configured such that 32-bit data is input in parallel to two sets of RAMs, or output from these two sets of RAMs in parallel, where each set consists of two 16-bit RAMs constitute. The interface for inputting 16-bit data to and outputting 16-bit data from the two RAMs of each group is serial.

FIG. 16 shows when the bus bandwidth is 16 bits and the interface is configured such that 16 bits of data are serially input to or serially output from four 16 bit RAMs. The configuration of the interface 52 in FIG. 16 is the same as that of the inner interface. In other words, the inside interface is configured as shown in FIG. 16 because the internal bus width on the arithmetic PE array side is narrow, ie, 16 bits. Therefore, the inside interface 50 is configured such that 16-bit data is serially input to or serially output from four 16-bit RAMs.

In this way, the interfaces 50 and 52 in the memory PE are configured to match the configuration of the bus connected based on the configuration data CD.

As described above, according to the present embodiment, a plurality of groups of clusters including a plurality of operation PEs and memory PEs are arranged in an integrated circuit device configurable by dynamically changing the circuit configuration, and the clusters are interconnected through switch groups whose connection states are dynamically changed. Connected, independent of the inter-cluster switch group, the storage PEs in the cluster are connected to external storage. Memory PE can perform DMA transfer with external memory. The memory PE is also configured with double buffers, so that seamless data transmission can be performed between the external memory and the computing PE. If there is a problem in data transmission, the pipeline operation of the computing PE array is temporarily stopped.

This application is based on and claims priority from prior Japanese Patent Application No. 2005-224208 filed on August 2, 2005, the entire contents of which are hereby incorporated by reference.

Claims (16)

1. reconfigurable integrated circuit device, this device is dynamically configured based on configuration data and is any compute mode, and this device comprises:

A plurality of trooping, described trooping also comprises and carries out the memory processor element with storer of data transmission between a plurality of arithmetic processor elements that have computing unit respectively and the external memory storage and be used for being connected switches set between the processor elements of described arithmetic processor element and described memory processor element under free position;

A switches set of trooping is used for the data routing between described the trooping of configuration under free position; And

External memory bus is used to carry out the data transmission between described memory processor element and the described external memory storage, wherein

Switches set and a described switches set of trooping are dynamically changed based on described configuration data between described arithmetic processor element, described memory processor element, described processor elements, and described device also comprises:

Direct memory access control parts, it visits the data transmission of carrying out between described memory processor element and the described external memory storage in response to the request of access of coming from described a plurality of memory processor elements of trooping by direct memory.

2. reconfigurable integrated circuit device as claimed in claim 1, wherein said trooping also comprises the configuration data memory that is used to store described configuration data, and sequencer, this sequencer is used to dispose the configuration data of next compute mode in response to from described arithmetic processor element and memory processor element and the end signal that comes from described configuration data memory output.

3. reconfigurable integrated circuit device as claimed in claim 1, also comprise the data-flow-control member made, this data-flow-control member made is installed to be the global facility of described a plurality of memory processor elements, be used to accept from described a plurality of memory processor elements and the direct memory request of access of coming, and to the synchronous direct memory request of access of described direct memory access control parts indication that is used for described a plurality of memory processor elements.

4. reconfigurable integrated circuit device as claimed in claim 1, also comprise the data-flow-control member made, this data-flow-control member made is installed to be the global facility of described a plurality of memory processor elements, be used to accept from described a plurality of memory processor elements and the direct memory request of access of coming, and to the synchronous direct memory request of access of described direct memory access control parts indication that is used for described a plurality of memory processor elements, wherein

When the direct memory request of access is when the single memory processor elements is accepted, described data flow con-trol unit response is indicated described direct memory request of access in described acceptance operation to described direct memory access control parts.

5. reconfigurable integrated circuit device as claimed in claim 1, wherein

Described memory processor element also comprise and be connected between the internal bus of switches set between described processor elements interior side interface and and described external memory bus between outer side interface, wherein

When described memory processor element was being visited described external memory storage via side interface outside described by the direct memory visit, described arithmetic processor element was via the described memory processor element of described inboard interface accessing.

6. reconfigurable integrated circuit device as claimed in claim 5, wherein

Described memory processor element also comprises first and second memory banks, wherein

Described first and second memory banks alternately are connected to described inboard and outer side interface based on described configuration data.

7. reconfigurable integrated circuit device as claimed in claim 6, wherein

After the data transmission of described memory processor element between the described external memory storage and described first or second storehouse finished, allow described arithmetic processor element and described first or the second memory storehouse between data transmission, and

If described external memory storage and described first or the second memory storehouse between data transmission do not finish, then described memory processor element is asserted a halted signals, to indicate shut-down operations to described a plurality of arithmetic processor elements, and when described external memory storage and described first or the second memory storehouse between data transmission when finishing, cancel described halted signals.

8. reconfigurable integrated circuit device as claimed in claim 3, wherein said memory processor element monitors the mode of operation of described direct memory access control parts, and based on described mode of operation described request of access is offered described data-flow-control member made.

9. reconfigurable integrated circuit device as claimed in claim 8, wherein said memory processor element is controlled the timing of described request of access changeably based on described mode of operation.

10. reconfigurable integrated circuit device as claimed in claim 1, data transmission when wherein said memory processor element carries out data transmission between by direct memory visit and described external memory storage between acceptance and the described arithmetic processor element, the data transmission by direct memory visit do not catch up with and described arithmetic processor element between data transmission the time, assert a halted signals stopping the computing of described a plurality of arithmetic processor elements, and in the time can catching up with, cancel described halted signals.

11. reconfigurable integrated circuit device as claimed in claim 5, the outer side interface of wherein said memory processor element is built as Interface status corresponding to described a plurality of data-bus widths based on described configuration data.

12. reconfigurable integrated circuit device as claimed in claim 1, wherein

Described memory processor element also comprises first and second memory banks, and

Described memory processor element is set to enable the state that when starting outside bus side conducted interviews based on configuration data with one in described first and second memory banks, and exports described request of access.

13. reconfigurable integrated circuit device as claimed in claim 12, when wherein in described first and second memory banks finishes the data transmission of visiting by direct memory, described memory processor element asserts that to described arithmetic processor element computing carries out enable signal, carries out computing to impel described arithmetic processor element.

14. reconfigurable integrated circuit device as claimed in claim 13, wherein when described first and second memory banks all enter the data transmission illegal state, described memory processor element is asserted a halted signals, to ask the shut-down operation of described arithmetic processor element.

15. reconfigurable integrated circuit device as claimed in claim 13, wherein said trooping also comprises a plurality of memory processor elements and a public computing execution control assembly of described memory processor element, this unit response is carried out asserting of enable signal in the computing that comes from described a plurality of memory processor elements, carries out to the computing that described a plurality of arithmetic processor element requests are synchronous.

Be predetermined compute mode 16. a reconfigurable integrated circuit device, this device are dynamically configured based on configuration data, this device comprises:

A plurality of trooping, described trooping comprises and carries out the memory processor element with storer of data transmission between arithmetic processor element with computing unit and the external memory storage and be used for being connected switches set between the processor elements of described arithmetic processor element and described memory processor element under free position;

A switches set of trooping is used for the data routing between described the trooping of configuration under free position; And

External memory bus is used to carry out the data transmission between described memory processor element and the described external memory storage, wherein

Switches set and a described switches set of trooping are dynamically changed based on described configuration data between described arithmetic processor element, described memory processor element, described processor elements, and described device also comprises:

Direct memory access control parts, it visits the data transmission of carrying out between described memory processor element and the described external memory storage by direct memory, wherein in response to the request of access of coming from described a plurality of memory processor elements of trooping

Described memory processor element comprises first and second memory banks, wherein when carrying out data transmission by the direct memory visit with described external memory storage for one in described first and second memory banks, another in described first and second memory banks and described arithmetic processor element carry out data transmission.

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