KR101882681B1 - Memory device and driving method thereof - Google Patents

Abstract

A memory device and a driving method thereof are provided. The memory device comprising: a normal storage area comprising a first and a second subset for respectively storing first and second normal data; A parity storage area for storing first and second parity data corresponding to the first and second normal data, respectively; An error detector receiving the first and second normal data, the first and second parity, and detecting whether the first and second normal data or parity are erroneous; And a refresh controller for setting the refresh operation of the first subset and the refresh operation of the second subset differently depending on whether the first and second normal data or parity is erroneous.

Description

[0001] Memory device and driving method [0002]

The present invention relates to a memory device and a driving method thereof.

The memory cell of the dynamic memory device is composed of a transistor serving as a switch and a capacitor storing data. However, a leakage current occurs in the PN junction of the MOS transistor or the like, and the initial data stored in the capacitor can be destroyed. Thus, the dynamic memory device requires a refresh operation that recharges the data in the memory cell before the data is destroyed.

Such refresh operations include auto refresh and self refresh. The auto refresh means performing refresh by receiving an external refresh instruction signal, and the self refresh means performing refresh while sequentially changing the internal address in response to the refresh instruction signal.

However, the refresh is repeated according to a predetermined period. Such a refresh period is referred to as a refresh period tREF. The refresh period is determined by the data retention time, and the data retention time is changed according to the change of PVT (Process, Voltage, Temperature). In addition, the data retention time may vary due to heat or other environmental factors (VRT, Variable Retention Time) during packaging or assembly. In this case, it is difficult to predict the extent to which the refresh characteristic is changed. That is, since the refresh characteristics may deteriorate during the packaging process or the set assembly, the margin of the refresh cycle to be secured in the test stage must be considerably large.

Therefore, there is a need for a means of rescuing the memory cell in which the refresh characteristic deteriorates in all production steps including after packaging, after assembling, and the like.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device with improved refresh characteristics.

Another object of the present invention is to provide a method of driving a memory device having improved refresh characteristics.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a memory device including a normal storage area including a first subset and a second subset storing first and second normal data, respectively; A parity storage area for storing first and second parity data corresponding to the first and second normal data, respectively; An error detector receiving the first and second normal data, the first and second parity, and detecting whether the first and second normal data or parity are erroneous; And a refresh controller for setting the refresh operation of the first subset and the refresh operation of the second subset differently depending on whether the first and second normal data or parity is erroneous.

According to another aspect of the present invention, there is provided a memory device including a normal storage area including a subset and a redundancy subset and storing normal data in the subset; A parity storage area storing a parity corresponding to the normal data; An error detector receiving the normal data and the parity and detecting whether the normal data or parity is erroneous; And repairing the subset to a redundancy subset according to whether the normal data or parity is erroneous.

According to another aspect of the present invention, there is provided a method of driving a memory device including a normal storage area including a first subset and a second subset, each storing first and second normal data, And a parity storage area for storing first and second parities respectively corresponding to the first normal data and second normal data, wherein the first and second normal data, the first and second parities are provided, 1 and the second normal data or the parity, and sets the refresh operation of the first subset and the refresh operation of the second subset differently according to whether the first and second normal data or parity is erroneous .

Other specific details of the invention are included in the detailed description and drawings.

1 is a block diagram illustrating a memory device according to a first embodiment of the present invention.
2 is a view for explaining a method of driving a memory device according to the first embodiment of the present invention.
3 is a view for explaining a method of driving a memory device according to a second embodiment of the present invention.
4 is a block diagram illustrating a memory device according to a third embodiment of the present invention.
5 is a block diagram illustrating a memory device according to a fourth embodiment of the present invention.
6 is a diagram illustrating an application system including a memory device according to some embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

1 is a block diagram illustrating a memory device according to a first embodiment of the present invention. 2 is a view for explaining a method of driving a memory device according to the first embodiment of the present invention.

Referring to Figure 1, a memory device 1 according to a first embodiment of the present invention includes an input buffer 10, a command and address decoder 20, a parity encoder 30, a normal storage area 51, A region 52, an error detector 70, a refresh controller 80, an output buffer 90, and the like.

The input buffer 10 receives and temporarily stores normal data TDATA and transfers the normal data TDATA to the parity encoder 30 and the first drive 41.

The command and address decoder 20 decodes the command CMD to detect entry into the refresh operation. Further, the address ADDR is decoded to designate a subset to be subjected to the refresh operation. Here, the subset means an area corresponding to the address ADDR in the normal storage area 51. [ For example, the subset may be a single memory cell, a row, a column, a two-dimensional form (e.g., a matrix) or a three-dimensional form (e.g., Block). The address ADDR is also transferred to the refresh controller 80.

The parity encoder 30 receives the normal data TDATA and generates a parity EDP. Here, the parity (EDP) is not limited to a particular type of code. For example, the parity (EDP) may be a simple even or odd parity code, a hamming code, a turbo code, a cyclic code, a low density parity check code or a Reed-Solomon error correction code, for example, a low-density parity-check code, a Reed-Muller code, or a Reed-Solomon error correction code, It is advantageous in terms of overhead to use a simple parity code only for detecting an error.

In the memory device 1 according to the first embodiment of the present invention, the parity EDP is a detection-only code. Table 1 shows a comparison between the detection-only simple parity code and the overhead when the parity is generated by the hamming code. Referring to Table 1, it can be seen that the simple parity used as the detection-only code minimizes the overhead. For example, in the case of Hamming codes, a 4-bit parity is required for single bit error correction of 8-bit normal data. The overhead is 4/8 * 100 = 50.00%. On the other hand, for single bit error detection of 8-bit normal data, a parity of 1 bit is required. The overhead is 1/8 * 100 = 12.50%.

Of the test data
Number of bits Number of bits in parity
(Detection only) Overhead
(%) Number of bits in parity
(For detection and correction) Overhead
(%) 8 One 12.50 4 50.00 16 One 6.25 5 31.25 32 One 3.12 6 18.75 64 One 1.56 7 10.93 128 One 0.78 8 6.25

Also, the memory device 1 according to the first embodiment of the present invention can minimize the overhead when employing a masking operation. The masking operation means limiting a certain range of data processing. That is, when the signal for controlling the masking operation is enabled, the corresponding data is not written even if the write command is enabled. When such a masking operation is adopted, the number of bits of the normal data TDATA that can be encoded and decoded in one unit can not be larger than the number of bits of the masking operation unit. This is because if the number of bits of the normal data TDATA to be encoded and / or decoded is larger than the number of bits of the masking operation unit, the encoding operation can not be performed because the bits to be masked are unknown to the encoder. That is, if the masking operation unit is 8 bits (i.e., 1 byte), parity can be generated for every 8 bits of normal data TDATA. For example, in the case of the memory device 1 adopting 64-bit pre-fetch and 8-bit unit masking, the parity of the detection-only code becomes 8 bits. Here, the overhead is calculated as 8/64 * 100 = 12.50%. On the other hand, the parity of the detection and correction code becomes 32 bits per 4 bits per 8 bits, and the overhead is 32/64 * 100 = 50%.

Further, if the memory device 1 according to the first embodiment of the present invention does not employ the masking operation, the number of bits of the normal data TDATA may be equal to the number of bits of the prefetch. For example, in the case of the 64-bit prefetch memory device 1, the parity becomes 1 bit. In this case, the overhead is 1/64 * 100 = 1.56%. In the case of the 128-bit prefetch memory device 1, the parity becomes 1 bit. In this case, the overhead is 1/128 * 100 = 0.78%.

On the other hand, the first drive 41 writes the normal data TDATA in the normal storage area 51 corresponding to the address ADDR. Further, the second drive 42 writes the parity (EDP) in the parity storage area 52 corresponding to the address ADDR.

Here, each of the normal storage area 51 and the parity storage area 52 may be a two-dimensional shape (for example, a matrix shape) or a three-dimensional shape (for example, a block shape). In addition, each of the normal storage area 51 and the parity storage area 52 may include a plurality of dynamic memory cells that require refreshing.

The first sense amplifier 61 reads the normal data TDATA from the normal storage area 51. [ The second sense amplifier 62 reads the stored parity EDP from the parity storage area 52.

The error detector 70 receives the read test data TDATA and the parity EDP and uses them to detect whether the normal data TDATA or the parity is erroneous.

The refresh controller 80 adjusts the refresh operation setting according to whether the normal data (TDATA) or the parity is erroneous. Specifically, when an error occurs in the normal data (TDATA) or parity, the address data (ADDR) of the subset storing the normal data (TDATA) or parity in which the error occurs and the corresponding refresh period are stored in the address storage unit . The address storage unit 82 may use an electrical fuse or a nonvolatile memory so as to store an address and a corresponding refresh period even if the power is off, but the present invention is not limited thereto.

For example, the refresh controller 80 can shorten the refresh period of the subset corresponding to the stored address ADDR.

Here, an example will be described with reference to FIG. The normal storage area 51 includes a first subset SUBSET1 and a second subset SUBSET2, a first subset SUBSET1 storing first normal data TDATA1, a second subset SUBSET2 storing a first normal data TDATA1, 2 normal data TDATA2. The parity storage area 52 stores a parity EDP1 corresponding to the first normal data TDATA and a parity EDP2 corresponding to the second normal data TDATA.

Assume that the first normal data TDATA1 is an error (i.e., a low retention state) and the second normal data TDATA2 is a normal retention state. The refresh controller 80 changes the refresh period of the first subset SUBSET1. That is, the refresh period (tREF1 in Fig. 2) of the first subset SUBSET1 is made shorter than the refresh period (tREF2 in Fig. 2) of the second subset SUBSET2.

This has the following effects.

The test is performed using the unique read and write functions of the memory device 1 according to the first embodiment of the present invention. Therefore, there is no additional burden on the system for the test.

In addition, since the memory device 1 according to the first embodiment of the present invention is tested / repaired using a unique read / write function, it can be used not only in chip production, but also in post package repair, These test / repair methods can be applied to post set assembly repair. In addition, the end user can use these test / repair methods. Therefore, in contrast to the unpredictable Variable Retention Time (VRT), the memory cell can be saved from the deterioration of the refresh characteristic.

Further, as described above, since the memory device 1 according to the first embodiment of the present invention uses the exclusive-use parity (EDP), the overhead is very high as compared with the parity used for detection and correction small.

3 is a view for explaining a method of driving a memory device according to a second embodiment of the present invention. For convenience of explanation, description will be made mainly on contents different from the contents described with reference to FIG. 1 and FIG.

3, the normal storage area 51 includes a third subset SUBSET3 to a sixth subset SUBSET6, and a third subset SUBSET3 to a sixth subset SUBSET6 includes third normal data TDATA3 to sixth normal data TDATA6.

The parity storage area 52 stores the parities EDP3 to EDP6 corresponding to the third normal data TDATA3 to the sixth normal data TDATA6, respectively.

The third normal data TDATA3 and the parity are in the normal retention state and the fourth normal data TDATA4 and the parity are in the low retention state and the fifth and sixth normal data TDATA5 and TDATA6 and parity are high retention State. In this case, the addresses of the fourth normal data (TDATA4) and the fourth subset (SUBSET4) corresponding to the parity and the refresh period are stored in the address storage section (82).

Here, the refresh controller 80 borrows a refresh opportunity of the other subset (SUBSET5, SUBSET6) in the high retention state and can perform the refresh operation of the subset SUBSET4 corresponding to the stored address.

In this way, the refresh period tREF4 of the fourth subset SUBSET4 is shorter than the refresh period tREF3 of the third subset SUBSET3, and the refresh period tREF3 of the third subset SUBSET3 is the fifth and sixth Is shorter than the refresh cycles (tREF5, tREF6) of the subset (SUBSET5, SUBSET6). For example, the refresh period tREF4 of the fourth subset SUBSET4 is 1/2 of the refresh period tREF3 of the third subset SUBSET3, and the refresh period tREF3 of the third subset SUBSET3 is the fifth And the refresh periods tREF5 and tREF6 of the sixth subset SUBSET5 and SUBSET6, but the present invention is not limited thereto.

4 is a block diagram illustrating a memory device according to a third embodiment of the present invention. For convenience of explanation, description will be made mainly on contents different from the contents described with reference to FIG. 1 and FIG.

Referring to FIG. 4, in the memory device 3 according to the third embodiment of the present invention, the parity EDP may be selectively used for error detection only, and may be used for error detection and correction.

As described above, when the memory device 3 according to the third embodiment of the present invention uses a masking operation, a detection-only parity (EDP) of 1 bit per 8 bits of normal data (TDATA) can be generated See Table 1). Therefore, when the masking operation is used, 8 (= 1 x 8) bits of detection dedicated parity (EDP) are required per 64 (= 8 x 8) bits of normal data (TDATA). At this time, the overhead is 12.50%. On the other hand, if the masking operation is not used, 7 bits of detection and correction parity (EDP) are required per 64 bits of normal data (TDATA). At this time, the overhead is 10.93% (see Table 1). That is, when 12.50% and 10.93% are compared, it can be seen that when the masking operation is not used, the overhead of the parity (EDP) used for detection and correction is not large.

As another example, when a masking operation is used, 16 (= 1 x 16) bits of detection specific parity (EDP) are required per 128 (= 8 x 16) bits of normal data (TDATA). At this time, the overhead is 12.50%. On the other hand, if the masking operation is not used, 8 bits of detection and correction parity (EDP) are required per 128 bits of normal data (TDATA). At this time, the overhead is 6.25% (see Table 1). That is, when 12.50% and 6.23% are compared, it can be seen that when the masking operation is not used, the parity (EDP) used for detection and correction does not have a large overhead.

That is, in the memory device 3 according to the third embodiment of the present invention, when the overhead of the parity (EDP) used for detection and correction is not large, the parity EDP used for detection and correction is used . In this case, the error corrector 72 receives the read normal data TDATA and the parity EDP used for detection and correction, corrects and outputs the normal data TDATA. The output buffer 90 outputs the corrected normal data TDATA to the outside.

In summary, when the memory device 3 according to the third embodiment of the present invention uses a masking operation, each subset is n bits (where n is a natural number) bits and each parity EDP is k Natural number) bits. In this case, each parity (EDP) is a detection-only code.

On the other hand, when the memory device 3 does not use the masking operation, each subset is n x q (where q is a natural number of 2 or more) bits, and each parity EDP is larger than k bits and equal to Or smaller. In this case, each parity (EDP) is a code used for detection and correction. Here, the n x q bits may be the number of bits of the pre-fetch.

5 is a block diagram illustrating a memory device according to a fourth embodiment of the present invention. For convenience of explanation, description will be made mainly on contents different from the contents described with reference to FIG. 1 and FIG.

Referring to FIG. 5, the memory device 4 according to the fourth embodiment of the present invention includes a repair controller 84, and repairs the subset to a redundancy subset according to whether normal data (TDATA) or parity is erroneous .

Specifically, the normal storage area 51 includes a redundancy area 58. [ The redundancy area 58 includes a redundancy subset. The parity storage area 52 stores a parity (EDP) corresponding to the normal data TDATA. The error detector 70 receives the test data TDATA and the parity EDP and detects whether the test data TDATA or the parity is erroneous. The repair controller 84 repairs the subset to the redundancy subset according to whether the normal data (TDATA) or the parity is erroneous. The repair controller 84 includes an address storage 82. The address storage 82 stores the normal data TDATA and the address of the subset storing the parity when the parity is error. (ADDR) and the refresh cycle.

As described above, the parity (EDP) may be a detection specific code. When the memory device 4 according to the fourth embodiment of the present invention adopts the masking operation, the number of bits of each normal data TDATA may be equal to the number of bits of the masking operation unit. On the other hand, in the memory device 4 according to the fourth embodiment of the present invention, when the masking operation is not employed, the number of bits of each normal data TDATA may be equal to the number of bits of the pre-fetch .

6 is a diagram illustrating an application system including a memory device according to some embodiments of the present invention. Here, the application system may be implemented by various systems such as a computing system, a mobile device, and the like.

6, an application system 700 includes a microprocessor 720 electrically coupled to a bus 710, a user interface 730, a modem 750 such as a baseband chipset, and a memory device 760 ). Here, the memory device 760 will be implemented with the same memory device as described in Figs. 1-5. The memory device 760 stores data to be processed or processed by the microprocessor 720. When the application system 700 is a mobile device, a battery 740 for supplying the operating voltage of the application system 700 may additionally be provided.

Although not shown in the figure, the application system 700 may further include an application chip set, a camera image processor (CIS), a NAND flash memory device, and the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: Input buffer 20: Command and address decoder
30: Parity encoder 51: Normal storage area
52: parity storage area 70: error detector
80: refresh controller 82: address storage unit
90: Output buffer

Claims (10)

A normal storage area including first and second subsets for respectively storing first and second normal data;
A parity storage area for storing first and second parity data corresponding to the first and second normal data, respectively;
An error detector receiving the first and second normal data, the first and second parity, and detecting whether the first and second normal data or the first and second parity are erroneous; And
And a refresh controller for setting the refresh operation of the first subset and the refresh operation of the second subset differently according to whether the first and second normal data or the first and second parity are erroneous,
Wherein the refresh controller includes an address storage unit,
Wherein the address storage section stores the address and the refresh period of the first subset when the first normal data or the first parity is an error,
The refresh controller borrows the refresh opportunity of the second subset when the first normal data or the first parity is an error and the second normal data or the second parity is in a high retention state, A memory device that performs a refresh operation of a subset. The method according to claim 1,
Wherein each of the first and second parities is a detection-only code. delete The method according to claim 1,
The refresh controller includes:
And changes the refresh period of the first subset when the first normal data or the first parity is an error and the second normal data or the second parity is a normal retention state. delete The method according to claim 1,
Wherein the memory device employs a masking operation and the number of bits of each normal data is equal to the number of bits of the masking operation unit. The method according to claim 6,
When the memory device uses a masking operation, each subset is n bits (where n is a natural number), each parity is k bits (where k is a natural number)
When the memory device does not use the masking operation, each subset is n x q (where q is a natural number greater than or equal to 2) bits, and each parity is greater than k bits and less than or equal to k x q bits. The method according to claim 1,
Wherein the memory device is packaged or assembled. delete delete

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