JPS59136859A - Buffer controller - Google Patents

Abstract

PURPOSE:To improve the writing efficiency of a memory by delaying the transmission of data to the memory from a buffer until a counter detects the prescribed value. CONSTITUTION:A processor 100 transmits a writing address, a writing position designating request, a writing data and a writing indicating request to buffers 410, 420 and 430 as well as to a writing indication reception control circuit 200, respectively. The contents of these buffers are supplied to a memory 500 via registers 415, 425 and 435. In this case, if plural writing requests are given to the same address, those writing data are written on each other with an indication of a degeneration indicating circuit 500. Then the data written on each other are sent to a memory 600 in accordance with the signal generated when a counter 210 in the circuit 200 reaches the prescribed value. Thus the writing efficiency is improved for a memory.

Description

TECHNICAL FIELD The present invention relates to a buffer control device for controlling the sending of write data to a storage device in a data processing device.

BACKGROUND OF THE INVENTION In general, the read/write operation speed of a main memory is slower than the read/write request speed of a processing device, so a wait occurs in write processing to the main memory in response to continuous write requests from the processing device. In order to eliminate this drawback, a system has been proposed in which the processing device is provided with a write buffer device.

After the processing device in this system completes the write process to the write buffer device, it performs writing from the write buffer device to the main storage device depending on the free space of the storage device. Therefore, even when partial write designations to the same address area of the main memory are given successively, if the main memory is empty, the preceding write request will be output from the write buffer device. For this reason, if a subsequent write request is for the same address area, there is a drawback that the main storage device is not made available until the preceding write process is completed and the main storage device is forced to wait.

In particular, in a multiprocessor system, an increase in the number of write instructions as described above increases the write processing in the main storage device, resulting in a decrease in the performance of the entire system.

Nine systems have also been proposed to overcome this drawback.

In this system, when a processing device issues a write request to a write buffer, it is notified that a subsequent write designation for the same address area exists. Respond to this notification
, a write request from the write buffer device to the main memory device is suppressed, and a write designation to the same address area is processed after being degenerated by the write buffer device. When there are no more write requests to the same address area, the processing device notifies the write buffer device of a write request, and the write buffer device is controlled to issue a write request to the main storage device.

This system has a drawback in that the processing device must be able to determine that there is a subsequent write designation to the same address area when making a write request to the write buffer.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a buffer control device that eliminates the above-mentioned drawbacks and allows the main memory to efficiently perform write processing.

Structure of the Invention Write instruction request means for generating a write instruction request signal; and a write address, write data, and information sent from the processing device together with the write instruction request signal from the write instruction request means. storage means for storing a write designation signal; a counting means that advances at regular time intervals in response to the write instruction request signal from the write instruction requesting means; and a count value of the counting means that is a predetermined value. a signal generating means that generates an instruction signal when the instruction signal is reached; and a comparison that compares the latest write address stored in the storage means before the instruction signal is generated from the signal generating means with the write address of the subsequent request. and in response to a match signal from the comparing means, the subsequent write data is added to the preceding write data stored in the storage means according to the write designation of the subsequent write request whose write address matches. The storage device includes a degenerating means for writing, and an instructing means for instructing to read the data overwritten by the degenerating means from the storage means in response to an instruction signal from the signal generating means.

DESCRIPTION OF EMBODIMENTS Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a processing device 10.
0. Write instruction reception control circuit 20 having a counter 210
0. Write address buffer circuit 41o.

Write position designation buffer circuit 420. IF-included data buffer circuit 430. Write address register 415°Write position designation register 425. Write data reception p435. and a buffer circuit 400 having a degeneration instruction circuit 500.
and a main storage device 600. The degeneration instruction circuit 50
0 is the write address comparison circuit 510. Write data register acquisition determination circuit 52o.

Selector 522. and a write position determining OR circuit 530.

Referring to FIG. 2, the write data register acquisition determining circuit 520 includes a plurality of gates 701 and a plurality of gates 7
It has 02. Previous=r2 When writing is desired to be performed on the writing device 600, the processing device 100 sends a write address to the write address line 110, a write position designation to the write position designation signal line 120, Write data to write data 1
30 and is notified to the write instruction reception control circuit 200 via the write instruction request line 101. The write instruction acceptance control circuit 200 controls the write address buffer 410. when there is space in the buffer 400 for buffering a new write request. The writing position specification (sofa 420
．． The control signal line 2 is connected to the write data buffer 430.
21 to instruct each data to be taken into a predetermined buffer position.

The write address buffer 410. The write position designation buffer 420. and the write data buffer 430
Although not shown, addressing is controlled by a pointer that is incremented each time it is written and a pointer that is incremented each time it is swept out. When the difference between these two pointers is 90'', it indicates that the buffer is empty, and when the difference is within a certain value (buffer capacity number), the write address buffer 410
．． The write position designation buffer 420. and indicates that the write data buffer 430 contains information related to transmission waiting. When the write address no. Your request will be accepted, but you will have to wait until a space becomes available.

The write instruction acceptance control circuit 200 outputs a signal from the write address buffer 410 via an output signal line 411 when the write address register 415, the write position designation register 425, and the write data register 435 are empty. The write address register 415 is instructed to write to the write position designation register 425 from the write position designation buffer 420 via the output signal line 421 and the selector 522.
Also, the write address capture signal tii 231 . The convolution position designation register acquisition signal lines 241.4 and 4F are instructed via the F-fold data register acquisition signals l# and 251, respectively. The write instruction reception control circuit 200 includes a write address register 415,
Write position specification register 425. Saving data register 43
When 5 is vacant, the output signal 411 from the write address buffer 410 is sent to the write address register 415, and the output signal 421 from the write position designation buffer 420 is sent to the selector 52.
2 to the write position designation register 425, and the output signal 431 from the write data noxter 430 to the write data register 435. All write address capture signal 23
1. Write position designation register take-in signal 241 and write data register take-in signal 251 respectively give instructions. The write address register 415. After the respective information has been taken into the write position designation register 425 and the 1-inclusive data register 435, the expense-included address buffer 41
01 When the write position designation buffer 420 and the scan data buffer 430 are empty, activation of the counter 210 is started. The counter 210 increments every machine cycle after starting, and outputs a sending instruction signal when it reaches a predetermined value. The contents of the output signal line 416 connected to the write address register 415 in the address comparison circuit 510 and the output signal 4 connected to the write address buffer 410
The content of line 11 is compared with the contents of line 11 by comparison circuit 510, and a mismatch is reported to write instruction reception control circuit 200 via output signal forest 501.

In response to this report, the control circuit 200 issues a transmission instruction signal. The write address regimen j1415. from the write instruction reception control circuit 200. The write position designation register 425. Then, the write data register 435 is instructed to take in the information, and the respective information is taken in. After this, if there are still subsequent write requests in the write address buffer 410, the write position designation buffer 420, and the write data buffer 430, the counter 2
10 is not activated. The above-mentioned input instruction reception control circuit 200
performs sending processing based on the comparison result of the address comparison circuit 510. The write address register 415. The write position designation register 425. and the write data register 435
Information retrieval is instructed to the write address buffer 410. The write position designation buffer 420. On the condition that there is no subsequent write request to the write data buffer 430 and the counter 210 detects a predetermined value and issues an instruction signal after starting the activation of the counter 210, the write instruction reception control circuit 200 Output write address signal line 4
16, the write position designation is sent to the output signal line 426, the write data is sent to the output signal 436 from the respective registers, and a write request is issued to the main storage device 600 via the write request signal line 201.

In response to acceptance of a write request for the storage device 600, the write address register 415. The write position designation register 425 and the write data register 435 become vacant. Therefore, preparations are made for the next write request to the storage device 600. When the main storage device 600- is in advance operation processing and does not accept a write request, the write request signal sent from the write instruction acceptance control circuit 200 via the write request signal line 201 is output until it is accepted. be done.

The input instruction reception control circuit 200 controls the address register 415. When the write position designation register 425.the write data register 435 is empty, the write address buffer 410. The write position designation buffer 420. and information related to the next write request from the write data buffer 430 to the write address register 415. The write position designation register 425. Input signal lines 231 and 241.2 are connected to input into the ordinary and inclusive data register 435.
51. The write address buffer 41
0, when there is no information related to the next write request in the write position designation buffer 42o and the write data buffer 7430, the counter 210 is activated and waits for an instruction signal.

A write request to the main memory device 600 is made to wait until an instruction signal is received from the counter 210. The write address register 415. While the write position designation register 425° and the write data register 435 are waiting for a write request to the main storage device 600, the next write request is sent from the processing device 100 via the line 101. The write address, write position designation, and write data are taken into a predetermined position in the buffer. After this import operation,
The write instruction acceptance control circuit 200 detects all the states of the match/mismatch output signals of the address comparison circuit 510 applied via the line 511. Address comparison circuit 510
, the output signal 41 of the write address register 415
6 and the subsequent write request address from the write address buffer 41ot (buffer output signal 411), and a signal indicating a match is notified to the write instruction reception control circuit zoovL via the output signal line 511. A write position designation OR circuit 530 logically ORs output signals 426 from a plurality of write position designation registers 425 and output signals 421 from a plurality of write position designation buffers 420 in a bitwise manner. Therefore, the write instruction reception control circuit 200 instructs the selector 522 to select the output signal 531 of the write position designation OR circuit 530 via the address comparison match valid signal line 261. Further, the circuit 200 includes:
Via the write position designation register capture signal line 241,
Instructs that the output of selector 522 be taken into write position designation register 425. The address comparison match valid signal line 261. is also connected to the write data register acquisition circuit 520. The respective signals are notified from the write instruction reception control circuit 200 via the 1-inclusive data register acquisition signal 251 line. The write data register capture gate circuit 520 receives the output signal @431 of the write data buffer 430 only at the position indicated by the output signal line 421 of the write position designation buffer 420.
This command instructs the write data register 435 to take in the data.

Output signal 11i1114 of write position designation buffer 420
The contents of the write data register 435 at locations not indicated by 21 are held as they are. This operation is called a degeneration operation. Before the counter 210 is activated and an instruction signal is issued, the next write instruction request is notified from the processing device 100, and the write address, write position designation, and write data are taken into the predetermined position of the buffer. or when the write instruction reception control circuit 200 checks the state of the output signal 511 line of the write address comparison circuit 510. If the addresses match, the write position designation and write data degeneracy are performed as described above. The contents of the output signal line 416 of the write address register 415 and the contents of the output signal &+411 of the write address buffer 410 are compared by the write address comparison circuit 510. As a result of this comparison, when a degree Celsius mismatch is notified via the output signal line 511, the counter 210 outputs an instruction signal.

In response to this signal, the write instruction reception control circuit 200 sends a convolution request signal Iv11201 to the main storage device 600.
Outputs the vc write request.

The write position designation data and degeneracy of write data will be explained with reference to FIG.

When the write instruction reception control circuit 200 instructs the write data register 435 to read the data via the write data register capture signal 251, the write address buffer 410 is given 'C via the line 411. output signal and line 41
At the same time, a signal indicating the result of the comparison between the address comparison circuit 510 and the output signal 416 of the write address register 415 applied via the line 261 is indicated via the line 261.

If the comparison results do not match, the content of the signal line 261 is 'Xo
, so the outputs of the OR game) 701 become ``1'', and the AND gate 7o2 performs a logical product of this output and the contents of the write data register capture signal #251.As a result, The output signal of the write data buffer 430 is passed through 1431' to the all write data register 4.
35. When the comparison result is a match, the signal edge 26
Since the content of 1 becomes "1", the OR gate 701 outputs "1" only on the "1" portion of the output signal line 421 of the write position designation buffer 420. Therefore, the C1 AND gate 702 outputs the output of the write position designation buffer 420.
XX1" is output in response to the write data buffer 4.
30 output signals are taken to write data register 435 via line 431. The write designation register 425 is loaded using a control signal fIM261 to switch the selector 522.
signal is used on line 421 in response to a discrepancy in the comparison result.
The output signal of the write position designation buffer 420 given through the register 426 is selected, and in response to a match, the output signal of the write position register 425 given through the register 426 and the edge 42 are selected.
The OR gate 703 performs a logical OR with the output signal of the write position designation buffer 420 given by 1 °C, and the output is selected. When input to the ordinary position finger/foot register 425 is instructed via the write position designation register input signal line 241, the output of the selector 522 is input. The write instruction reception control circuit 200 will be explained using FIG. 3.

Referring to FIG. 3, the AND gate 220 calculates the AND of the write request notified from the processing device 100 via the write instruction request line 10i and the content of the buffer full signal line 291 from the pointer control circuit 290. It will be done. When the buffer is not full, an instruction is given to take data into the buffer via the buffer take-in signal 1fM221, and the processing device 100 is notified that the write instruction request has been accepted. The input pointer 293 is instructed to advance, and a flip-flop (hereinafter abbreviated as F/F) 270 is set.

Although not specified in the above diagram, the write address buffer 410. Write position specification buffer 420. Addressing the write data buffer 430 indicates that the buffer is full when the difference between the two pointers indicates the buffer capacity number. 6. When the difference between the two pointers is "0", it indicates that the buffer is empty. Further, when the difference is within the buffer capacity number, it is indicated that there is data in the buffer. When data is loaded into the buffer, write address register 415 * write position specification register 425
Is the write data register 435 (hereinafter referred to as write register) free?

Is there a write request 201 to the main storage device 600 and whether this write request can be accepted? (When the F/F 280 is not set and the AND gate 213 is working, it is an or-or-game) 21.4 The output of is indicated by ゝゝ1“)
is checked by the AND gate 271. or gate 214
When the output of 91'' is displayed, it is possible to input data into the write register, so the AND gate 271 operates. 415 is instructed, and output signal lines 241 and 25 of OR gates 240 and 250
1 respectively to the write position designation register 42 in FIG.
Input into the 5-honor import data register 435 is instructed.

The output signal of OR gate 240 indicates the transfer of data from the buffer to the write register. Therefore, output pointer 2
94 steps are instructed. The output of AND gate 271 sets F/F 280. F/F 280 indicates that the write register is busy. p/pz? Since o is indicated by the output signal 292 of the pointer control circuit when the buffer is empty, it is reset by this signal.

When the write instruction request 101 from the processing device 100 is received at the same time, the F/F 270 has set priority and therefore remains in the set state. When F/F280 is set and the buffer is empty, the output of AND281 is XX1"
Start up Naru no Yakau/RI210. If there is no subsequent write request after starting the counter, and after the counter 210 starts starting, the counter detects a predetermined value and an instruction signal is output from the °C OR gate 211.
2, the output signal of the F/F 280 is ANDed.

The logical product result is the write request 2 to the main storage device 600.
It is output via the 01 line. When the main storage device 600 is capable of accepting a write request, °CI is sent via the output signal line 601.
J ply is applied to circuit 200 and AND gate 213
works. The output signal of AND gate 213 is F/F280
This becomes the reset signal No. 48 and the input signal of the OR gate 214, and becomes the condition for taking in the subsequent write request to the write register. When the counter 210 is activated and an instruction signal is issued, the next write instruction request 101 is notified from the processing device 100 while the write register is waiting for the write to the main memory device to be written, and the data is stored in the buffer. When a write instruction request 101 is received and a subsequent write request is stored in the buffer, or when F/Fs 270 and 280 are both set and C is in the state, the write address comparison circuit 510
The contents of the output signal line 511 are received by the buffer gate 263. When the comparison results match, AND gate 2
60 is activated and the address comparison match valid signal @261.

and game) 240 and 250 output signals -
Write position designation register 425. through lines 241 and 251, respectively. An instruction is given to take in the data of the subsequent write request to the honor data register 435.

Further, the output pointer 294 is instructed to increment.

From then on, when there is a write request for address matching between when the counter detects a predetermined value and an instruction signal is output from the °C OR gate,
The degeneration operation is performed. As a result of the address comparison, when a mismatch is notified via the output signal line 511, the AND gate 262 is activated and the counter 210 is activated from the OR gate 1211.
An instruction signal is output. Then, an AND gate 212 performs a logical product with the output signal of the F/F 280, and the memory device 6
A write request 201 is output for 00. The subsequent operations are similar to those described above.

Effects of the Invention In the present invention, by delaying the sending from the buffer to the storage device until the counter detects a predetermined value, if there is writing to the same address, consecutive write operations to the same address are unified. By degenerating the write operation into one write operation and issuing a write request to the storage device, there is an effect that the storage device can perform write processing efficiently.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a part of the configuration of FIG. 1 in detail, and FIG. FIG. 3 is a diagram showing the configuration. 1 to 3, 100...processing device, 101...write instruction request line, 110...
...Write address line, 12o...Write position designation line, 13°...P write data line, 200...
...Write instruction acceptance control circuit, 221...Buffer capture signal line from the write instruction acceptance control circuit, 261...
...Address comparison match valid signal line, 231...
...Write address register capture signal line, 241...
...Write position specification register capture signal line, 251...
...Write data register capture signal edge, 201...
-Write request signal line, 410...Write address buffer, 411-Old...Output signal line, 415-Paper write address register, 416...Output signal line,
420...°°Write position specification buffer, 421...
...Output signal line, 425...Write position specification register, 426...Output signal line, 435...
...Write data register, 436...Output signal line, 400...Buffer, 51o...
...Write address comparison circuit, 53°°°...Write position designation OR circuit, 511.531...Output signal line, 522...Selector, '520...・・・
・Write data register capture gate circuit, 500...
...Degeneration instruction circuit, 600...Storage device, 43
o...Write data buffer, 431...
・Output signal line, 42゜°゛°°゛Owned position write buffer, 421...Output signal line, 435...
Write data register, 53o...Write position designation OR circuit, 522 selector, 425°°...°
Write position specification register, 426... Output signal line, 701, 703, old... OR gate, 702...
264...Address general match signal line, 241...Write position designation/register capture signal line, 251...Write data register capture Including signal -1210... Counter, 270, 28
0...°Flip 70 knob, 220.271.2
51.260. 262.212,213...and gate,
211°214.240.250...°or gate, 263°230...buffage), 2
01...Write request signal line, 601...
Write request reception signal line of main storage device 600, 221...
...Buffer capture signal line, 510-°·°゛Write address comparison circuit, 511...Output signal line, 261
...Near address comparison match valid signal line, 231...
...Write address register capture signal line, 241...
...Write position specification register capture signal line, 251...
...Write data register capture signal line, 410...
・Write address buffer, 420...Write position specification buffer, 43o...Write data buffer 7a, 293...Input pointer, 294...Output pointer, 290...Pointer control circuit. Figure 1 Eel Z diagram

Claims (1)

[Scope of Claims] Write instruction request means for generating a write instruction request signal, and a write address and a write address sent from the processing device together with the write instruction request signal from the write instruction request means. a storage means for storing data and a write designation signal; a counting means that advances at regular time intervals in response to a write instruction request signal from the write instruction requesting means; and a count value of the counting means is predetermined. a signal generating means for generating an instruction signal when the specified value is reached; and a comparison for comparing the latest write address stored in the storage means with the address of the subsequent request before the instruction signal is generated from the signal generating means. and, in response to a match signal from the comparison means, subsequent write data stored in the storage means according to the write specification of a subsequent request having a write address that matches the latest write address. A buffer comprising: degeneration means for overwriting a take; and instructing means for instructing to read data overwritten by the degeneration means from the storage means in response to an instruction signal from the signal generation means. Control device.