FR2575564B1 - MICROPROCESSOR WITH ARCHITECTURE TO FACILITATE LINKING WITH PERIPHERAL DEVICES - Google Patents

MICROPROCESSOR WITH ARCHITECTURE TO FACILITATE LINKING WITH PERIPHERAL DEVICES

Info

Publication number
FR2575564B1
FR2575564B1 FR8519332A FR8519332A FR2575564B1 FR 2575564 B1 FR2575564 B1 FR 2575564B1 FR 8519332 A FR8519332 A FR 8519332A FR 8519332 A FR8519332 A FR 8519332A FR 2575564 B1 FR2575564 B1 FR 2575564B1
Authority
FR
France
Prior art keywords
microprocessor
architecture
peripheral devices
facilitate linking
linking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8519332A
Other languages
French (fr)
Other versions
FR2575564A1 (en
Inventor
Nobuhisa Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59281593A external-priority patent/JPH0658691B2/en
Priority claimed from JP59281594A external-priority patent/JPH0632052B2/en
Priority claimed from JP28159284A external-priority patent/JPS61156356A/en
Application filed by Sony Corp filed Critical Sony Corp
Publication of FR2575564A1 publication Critical patent/FR2575564A1/en
Application granted granted Critical
Publication of FR2575564B1 publication Critical patent/FR2575564B1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Executing Machine-Instructions (AREA)
FR8519332A 1984-12-27 1985-12-27 MICROPROCESSOR WITH ARCHITECTURE TO FACILITATE LINKING WITH PERIPHERAL DEVICES Expired FR2575564B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP59281593A JPH0658691B2 (en) 1984-12-27 1984-12-27 Micro computer
JP59281594A JPH0632052B2 (en) 1984-12-27 1984-12-27 Micro computer
JP28159284A JPS61156356A (en) 1984-12-27 1984-12-27 Microcomputer

Publications (2)

Publication Number Publication Date
FR2575564A1 FR2575564A1 (en) 1986-07-04
FR2575564B1 true FR2575564B1 (en) 1989-07-28

Family

ID=27336859

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8519332A Expired FR2575564B1 (en) 1984-12-27 1985-12-27 MICROPROCESSOR WITH ARCHITECTURE TO FACILITATE LINKING WITH PERIPHERAL DEVICES

Country Status (9)

Country Link
US (1) US5025368A (en)
CN (1) CN1033293C (en)
AT (1) AT401695B (en)
AU (1) AU582409B2 (en)
CA (1) CA1242803A (en)
DE (1) DE3545937A1 (en)
FR (1) FR2575564B1 (en)
GB (1) GB2172142B (en)
NL (1) NL193475C (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6230254B1 (en) 1992-09-29 2001-05-08 Seiko Epson Corporation System and method for handling load and/or store operators in a superscalar microprocessor
US6434693B1 (en) 1992-09-29 2002-08-13 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US6941447B2 (en) 1991-07-08 2005-09-06 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6954847B2 (en) 1992-03-31 2005-10-11 Transmeta Corporation System and method for translating non-native instructions to native instructions for processing on a host processor

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5243700A (en) * 1988-12-30 1993-09-07 Larsen Robert E Port expander architecture for mapping a first set of addresses to external memory and mapping a second set of addresses to an I/O port
US5253181A (en) * 1989-04-27 1993-10-12 Kawasaki Steel Corporation Programmable one-board computer, and methods of verification of logic circuit and alteration to actual circuit using the programmable one-board computer
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
WO1993001563A1 (en) * 1991-07-08 1993-01-21 Seiko Epson Corporation Risc microprocessor architecture with isolated architectural dependencies
KR100299691B1 (en) 1991-07-08 2001-11-22 구사마 사부로 Scalable RSC microprocessor architecture
EP0547240B1 (en) * 1991-07-08 2000-01-12 Seiko Epson Corporation Risc microprocessor architecture implementing fast trap and exception state
US5274770A (en) * 1992-07-29 1993-12-28 Tritech Microelectronics International Pte Ltd. Flexible register-based I/O microcontroller with single cycle instruction execution
JPH08212185A (en) * 1995-01-31 1996-08-20 Mitsubishi Electric Corp Microcomputer
US7487339B2 (en) 2001-10-12 2009-02-03 Mips Technologies, Inc. Method and apparatus for binding shadow registers to vectored interrupts
US7552261B2 (en) * 2001-10-12 2009-06-23 Mips Technologies, Inc. Configurable prioritization of core generated interrupts

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4471461A (en) * 1977-12-02 1984-09-11 Texas Instruments Incorporated Variable function programmed system
US4349870A (en) * 1979-09-05 1982-09-14 Motorola, Inc. Microcomputer with programmable multi-function port
US4447881A (en) * 1980-05-29 1984-05-08 Texas Instruments Incorporated Data processing system integrated circuit having modular memory add-on capacity
US4393464A (en) * 1980-12-12 1983-07-12 Ncr Corporation Chip topography for integrated circuit communication controller
DE3121174C2 (en) * 1981-05-27 1985-11-07 Siemens AG, 1000 Berlin und 8000 München Circuit arrangement in a processor
US4471426A (en) * 1981-07-02 1984-09-11 Texas Instruments Incorporated Microcomputer which fetches two sets of microcode bits at one time
JPS59119925A (en) * 1982-12-27 1984-07-11 Toshiba Corp Logical circuit
US4649474A (en) * 1983-09-23 1987-03-10 Western Digital Corporation Chip topography for a MOS disk memory controller circuit

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6941447B2 (en) 1991-07-08 2005-09-06 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US7487333B2 (en) 1991-07-08 2009-02-03 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US7721070B2 (en) 1991-07-08 2010-05-18 Le Trong Nguyen High-performance, superscalar-based computer system with out-of-order instruction execution
US7739482B2 (en) 1991-07-08 2010-06-15 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6954847B2 (en) 1992-03-31 2005-10-11 Transmeta Corporation System and method for translating non-native instructions to native instructions for processing on a host processor
US7343473B2 (en) 1992-03-31 2008-03-11 Transmeta Corporation System and method for translating non-native instructions to native instructions for processing on a host processor
US6230254B1 (en) 1992-09-29 2001-05-08 Seiko Epson Corporation System and method for handling load and/or store operators in a superscalar microprocessor
US6434693B1 (en) 1992-09-29 2002-08-13 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US6965987B2 (en) 1992-09-29 2005-11-15 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US8019975B2 (en) 1992-09-29 2011-09-13 Seiko-Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor

Also Published As

Publication number Publication date
DE3545937A1 (en) 1986-07-10
GB2172142B (en) 1988-10-19
CA1242803A (en) 1988-10-04
AU5147885A (en) 1986-07-03
AT401695B (en) 1996-11-25
AU582409B2 (en) 1989-03-23
CN85109704A (en) 1986-07-02
GB8531799D0 (en) 1986-02-05
NL193475C (en) 1999-11-02
NL193475B (en) 1999-07-01
US5025368A (en) 1991-06-18
NL8503492A (en) 1986-07-16
GB2172142A (en) 1986-09-10
FR2575564A1 (en) 1986-07-04
CN1033293C (en) 1996-11-13

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Legal Events

Date Code Title Description
ST Notification of lapse