CN103441915A - Information processing apparatus and operation method thereof - Google Patents

Abstract

The present invention relates to an information processing device and an operating method thereof. The information processing apparatus includes a plurality of modules connected to the ring bus, and each module receives a packet storing data from an adjacent module and transmits the packet to another adjacent module after predetermined processing. At least one module includes: an identification unit for identifying a packet received from the one adjacent module to determine whether the received packet is a packet to be processed by the own module; a receiver for if the identification unit determines that the received The package is a package to be processed by its own module, then receive the data to be processed; the processor is used to process the received data; the setting unit is used to if the processor is not ready to process data, then in the A reservation flag is set in the received packet to indicate that at least one of the processors is not ready to process data in the received packet; and a transmitter is configured to transmit the packet with the reservation flag to another module.

Description

Information processing device and operating method thereof

This application is a patent application with an application date of February 17, 2010, an international application number of PCT/JP2010/052805, a national application number of 201080008604.0, and an invention title of "information processing device and its operating method, computer program and storage medium" divisional application.

technical field

The present invention relates to an information processing device, an operating method thereof, a computer program, and a storage medium.

Background technique

Various ring communication networks (circuit networks) have been proposed and prevailed. For example, the LAN (Local Area Network) specification includes the so-called Token Ring (see ISO/IEC8802-5:1998).

Data transmission in the Token Ring system will be briefly described below. Nodes that want to transmit data acquire tokens called free tokens that are not occupied by any node and are going around on the ring bus. A node that has acquired a free token copies the destination identifier and processing data to the token, and outputs the token on the ring bus to transmit it to the destination module. As mentioned above, in a token ring system, frames called tokens are sequentially transmitted from one node to another node, and then to the next node (these nodes are deployed on the ring bus), thus Pass the frame to the destination.

On the other hand, when a receiving node receives a token destined for its own node, the receiving node duplicates the processing data and puts the received token on the ring bus again, said received token indicating the received Completed receive complete flag is set. This cast is completed to notify the transfer source node of successful data transfer, and, if a token with no reception completion flag set is returned, the transfer source node retransmits the same token. In this way, the receiving node sets the reception completion flag in the token, and returns the token to the transmission source node, thereby realizing data transmission.

Contents of the invention

When an information processing system in which a plurality of modules performing data processing are connected to a ring bus adopts the token ring bus system described above, the token must be returned to the transmission source regardless of success or failure of reception. That is, even when reception is successful, data cannot be copied to the token before the transfer source releases the returned token, resulting in inefficiency.

The present invention realizes efficient packet transfer in an information processing system in which a plurality of modules performing data processing are connected to a ring bus.

An aspect of an embodiment of the present invention relates to an information processing device, the information processing device includes a plurality of modules, the plurality of modules are connected to a ring bus, and each of the plurality of modules is configured to transmit data from an adjacent A module receives a packet storing data and transmits the packet to another adjacent module after predetermined processing, characterized in that each module contains: identification means for identifying a packet received from another module to determine the received Whether the package is a package to be processed by its own module; the receiving unit is used to extract data to be processed from the package when the identification unit determines that the received package is a package to be processed by its own module; the processing unit uses for processing the extracted data; modifying means for setting a first flag indicating the validity of the data in the received packet to have a value indicating that the data is invalid when said processing means processes the data; and transmitting Part to pass the package to another module.

Other features of the present invention will become apparent upon reading the following description of exemplary embodiments (with reference to the accompanying drawings).

Description of drawings

Figure 1 is a block diagram representing an example of the arrangement of a data processing system;

FIG. 2 is a block diagram showing an example of the arrangement of the data processor 104;

FIG. 3 is a block diagram representing an example of the arrangement of modules;

FIG. 4 is a diagram representing an example of a format of a packet;

FIG. 5 is a flowchart showing an example of processing in the processing data transmission unit 303 and the reception unit 311;

FIG. 6 is a flowchart showing an example of processing in the processing data reception unit 305 and the transmission unit 312;

FIG. 7 is a block diagram representing an example of the arrangement of modules; and

FIG. 8 is a flowchart showing an example of processing in the processing data transmission unit 303 and the reception unit 311 .

Detailed ways

Embodiments of the present invention will be described below. The present embodiment relates to a data processing system in which a plurality of modules performing data processing are connected to a ring bus. Of course, the embodiments to be described below provide a disclosure that facilitates those skilled in the art to realize the present invention, and are only some embodiments included in the technical scope of the present invention defined by the scope of the claims. Therefore, those skilled in the art understand that even for embodiments not directly described in the specification of the present invention, they are included in the technical scope of the present invention as long as they have a common technical idea.

Note that a number of embodiments will be described for convenience. However, it is easily understood by those skilled in the art that not only these embodiments can form independent inventions, but also a plurality of embodiments can be combined as necessary to form inventions.

The arrangement of an information processing system according to an embodiment corresponding to an aspect of the present invention will be described below with reference to FIG. 1 . The CPU 101 is a control unit having a function of controlling the overall operation of the data processing system. The RAM 102 is a readable/writable memory that stores input data to be processed by the CPU 101 , output data after processing, preset parameter data for the data processor 104 , and the like. The ROM 103 is a readable memory that can hold the processing sequence of the CPU 101 and constants such as preset parameters. Data processor 104 comprises the arrangements and modules disclosed herein. The modules are connected to the ring bus. A programmable custom IC chip can implement the data processor 104 . The chips contain eg ASICs (Application Specific Integrated Circuits) or FPGAs (Field Programmable Gate Arrays).

The arrangement of the data processor 104 will be described below with reference to FIG. 2 . The data processor 104 includes a plurality of modules 201-204. A ring bus 205 is used to transfer packets between modules. The modules 201 to 204 are connected to the ring bus 205 . Each module is configured to receive a data packet from one neighboring module and transmit the data packet to another neighboring module after predetermined processing. Packets switched by the modules move in one direction on the ring bus. In the following description, a ring bus on which data (or packets) flow in one direction will be simply referred to as a ring bus.

The input/output buffer 206 is used to input/output data. Each of the modules 201 to 204 of the present embodiment has data processor identification information used to identify its own module, and is labeled "ID" in FIG. 2 for simplicity. In the following description of the embodiments of the present invention, this information is also described as "ID". Note that the module 201 with ID=1 is connected to the input/output buffer 206 to manage input and output data.

The arrangement of the modules 201 to 204 in the data processor will be described below with reference to FIG. 3 . Referring to FIG. 3 , the packet identification unit 301 checks whether to acquire a packet from another module. When the packet identification unit 301 receives a packet storing a transfer source ID that matches the ID that it waits for, it outputs the packet to the packet reception unit 302 .

The packet reception unit 302 performs packet reception processing. The processing data transfer unit 303 transfers the processing data to the processing unit 304 . The processing unit 304 performs actual data processing. The processed data receiving unit 305 receives processed data from the processing unit 304 . The packet generation unit 306 generates packets based on the processed data received from the processing unit 304 and the output from the packet modification unit 308 .

The packet transfer unit 307 outputs the packets onto the ring bus. The packet modifying unit 308 modifies the values of a data valid flag 401 and a stall flag 404 of a packet which will be described later with reference to FIG. 4 in accordance with an instruction from the packet receiving unit 302 . The selector 309 selects one of the packet from the packet transfer unit 307 and the packet from the packet modification unit 308 based on an instruction from the packet transfer unit 307 . If there is no instruction from the packet transfer unit 307, the selector 309 selects the packet output from the packet modification unit 308 and outputs the packet. Buffer 310 is used to transmit packets one after another.

In the above arrangement, each of the modules 201 , 202 , 203 and 204 contains a processing unit 304 and a communication unit 313 . The communication unit 313 includes a processing data transmitting unit 303 , a processing data receiving unit 305 , a selector 309 , a buffer 310 , a receiving unit 311 , and a transmitting unit 312 . In addition, the receiving unit 311 includes a packet identifying unit 301 , a packet receiving unit 302 and a packet modifying unit 308 . Furthermore, the transmission unit 312 includes a packet generation unit 306 and a packet transmission unit 307 .

In the following description, this embodiment will explain the case where the processing unit 304 outputs an output data by processing an input data. In this case, it is assumed that another input data cannot be input from when input data is input to the processing unit 304 to when output data is obtained. For this reason, the packet reception unit 302 must suspend reception of packets according to the state of the processing unit 304 .

Figure 4 shows the packet format required to exchange data between modules. The data validity flag 401 is first flag information for checking the validity of data in the packet. For example, if the data valid flag 401 is "1", then the data is valid; if the data valid flag 401 is "0", then the data is invalid.

The transfer source ID 402 is the identifier of the transfer source storing the module identifier of the transfer package. The data storage field 403 stores the processing data body. The hold flag 404 is second flag information that is set to "1" when the module suspends packet processing. That is, if the reserved flag 404 is "1," it indicates that packet processing is suspended. Note that processing is suspended, for example, when a module receives data but cannot process the data because the processing unit 304 is busy. The reserved flag 404 is set to "0" as an initial value. That is, when the reserved flag has an initial value, it means that the module on the ring bus to receive the packet has not processed the corresponding packet.

Each module can set the waiting packet ID. When the waiting packet ID matches the transfer source ID 402 of a packet flowing through the ring bus, the packet identification unit 301 acquires the packet. For example, a case where data paths are arranged in the order of module 1, module 4, module 2, module 3, and module 1 will be considered below. In this case, the waiting packet ID of module 1 is set to "3", the waiting packet ID of module 2 is set to "4", the waiting packet ID of module 3 is set to "2", and the waiting packet ID of module 4 is set to "2". The waiting packet ID is set to "1". By setting the waiting packet ID of each module in this way, a data path can be formed. It is assumed that a waiting packet ID is set in advance for each module, and its information is stored in the packet identification unit 301 .

The data receiving method in the communication unit 313 will be described below. For example, a case where data transfer is performed from module 1 with ID=1 to module 3 with ID=3 in FIG. 2 will be considered below. At this time, the packet identification unit 301 of the module 3 acquires the packet whose data validity flag 401 is valid, and compares the transmission source ID 402 of the packet with its own waiting packet ID. If the two IDs are equal to each other, the packet identifying unit 301 transfers the packet to the packet receiving unit 302 .

The processing data transfer unit 303 determines whether the processing unit 304 is ready to execute processing. If the processing data transfer unit 303 determines that the processing unit 304 is ready, the packet receiving unit 302 extracts the data to be processed from the acquired packet, and transfers the data to be processed to the processing data transfer unit 303 . In this case, since the packet is useless, the packet receiving unit 302 instructs the packet modifying unit 308 to set the data valid flag 401 of the packet to invalid (0).

On the other hand, if the processing data transfer unit 303 determines that the processing unit 304 is busy, the packet receiving unit 302 instructs the packet modification unit 308 to set the reservation flag 404 of the packet to "1". The packet modifying unit 308 modifies the data valid flag 401 or the reserved flag 404 according to an instruction from the packet receiving unit 302 , and transfers the packet to the selector 309 . The selector 309 selects one of the packet input from the packet modification unit 308 and the packet input from the packet transfer unit 307 , and transfers it to the buffer 310 .

Processing in the processing data transmission unit 303 and the reception unit 311 will be described below with reference to FIG. 5 . In step S501, the packet identification unit 301 acquires a packet from a module located at the previous stage. The packet identifying unit 301 checks in step S502 whether the data valid flag 401 of the packet is valid (1). If the data valid flag 401 is valid (YES in step S502 ), the process advances to step S503 . On the other hand, if the data valid flag 401 is invalid ("No" in step S502), the process ends.

The packet identifying unit 301 checks in step S503 whether the transfer source ID 402 of the packet is equal to the waiting packet ID set in the module. If it is determined that the two IDs are equal to each other (YES in step S503 ), the process advances to step S504 . On the other hand, if it is determined that the two IDs are not equal to each other (NO in step S503 ), the process ends.

The processing data transfer unit 303 checks in step S504 whether the processing unit 304 is ready to exchange data. If it is determined that the processing unit 304 is ready to exchange data (YES in step S504 ), the process advances to step S505 . On the other hand, if it is determined that the processing unit 304 is not ready to receive data (NO in step S504 ), the process advances to step S506 .

In step S505 , the packet reception unit 302 extracts the processing data from the packet, and transfers it to the processing data transfer unit 303 , and the processing data transfer unit 303 transfers the data to the processing unit 304 . The process then proceeds to step S507. In step S506, the packet receiving unit 302 instructs the packet modifying unit 308 to set the reservation flag 404 of the packet to "1". Then, the reserved flag 404 is modified from the initial value (0) to (1). In step S507, the packet receiving unit 302 instructs the packet modifying unit 308 to set the data valid flag 401 of the packet to "0".

The data transfer sequence in the processing data reception unit 305 and the transfer unit 312 will be described below. For example, a case where data transfer is performed from module 1 with ID=1 to module 3 with ID=3 in FIG. 2 will be explained below. At this time, the packet generation unit 306 of the module 1 acquires the packet in which the data validity flag 401 is invalid (0) from the packet modification unit 308 .

Then, the packet generating unit 306 stores the transfer data obtained from the processed data receiving unit 305 in the data storage field 303 of the packet, and stores “1” which is the ID of the module 1 in the transfer source ID 402 . Furthermore, the packet generating unit 306 sets the reserved flag 404 to an initial value (0), and sets the data valid flag 401 to "1". Then, the packet generation unit 306 transfers the packet to the packet transfer unit 307 . The packet transfer unit 307 outputs the packet acquired from the packet generation unit 306 to the selector 309 . At this time, the packet transfer unit 307 simultaneously outputs a selection signal to the selector 309 to select its output.

The packet generation unit 306 monitors the reservation flag 404 of the packet. When a packet output by itself is returned without setting the reserved flag to "1", the data valid flag 401 is set to "0" to prevent packets without receiving modules from occupying the ring bus. On the contrary, when the reserved flag 404 is set to "1", the packet is output onto the ring bus as it is.

Processing in the processing data receiving unit 305 and the transmitting unit 312 will be described below with reference to FIG. 6 . Referring to FIG. 6, the packet generation unit 306 acquires a packet from the packet modification unit 308 of the reception unit 311 in step S601. The packet generating unit 306 checks in step S602 whether the data valid flag 401 of the received packet is "0". If it is determined that the data valid flag 401 is not "0" (NO in step S602), the process advances to step S603. On the other hand, if it is determined that the data valid flag 401 is "0" (YES in step S602 ), the process advances to step S606 .

The packet generation unit 306 checks in step S603 whether the reserved flag 404 of the packet is "1". If it is determined that the reserve flag 404 is "1" (YES in step S603 ), the processing ends. In this case, the packet from the packet modification unit 308 is transferred to the next module via the selector 309 and the buffer 310 . On the other hand, if it is determined that the reserved flag 404 is not "1", that is, it still has the initial value ("No" in step S603), then the process advances to step S604.

The packet generating unit 306 checks in step S604 whether the transfer source ID 402 of the packet is equal to the ID of the own module. If it is determined that the two IDs are equal to each other (YES in step S604), the process advances to step S605. In step S605, the packet generating unit 306 sets the data valid flag 401 of the packet to "0", and the process then jumps to step S611. On the other hand, if it is determined that the two IDs are not equal to each other (NO in step S604 ), the process ends. In this case, too, the packet from the packet modification unit 308 is transferred to the next module via the selector 309 and the buffer 310 .

The packet generating unit 306 checks in step S606 whether valid processing data is obtained from the processing unit 304 . If valid processing data is obtained (YES in step S606 ), the process proceeds to step S607 . On the other hand, if valid processing data has not been obtained ("NO" in step S606), the processing ends.

In step S607, the package generation unit 306 copies the processing data acquired from the processing unit 304 to the data storage field 403 of the package. In step S608, the packet generation unit 306 sets the data valid flag 401 of the packet to "1". Furthermore, in step S609 , the packet generating unit 306 sets the reserved flag 404 of the packet to an initial value (0). Furthermore, in step S610, the packet generating unit 306 sets its own ID in the transfer source ID 402 of the packet. In step S611 , the packet generation unit 306 instructs the selector 309 to preferentially select the input from the packet transfer unit 307 .

As described above, according to this embodiment, when the receiving module can process the data of the received packet, it invalidates the packet; when the receiving module cannot process the data, it sets the reservation flag 404 of the packet to "1" and The packets are recast on the ring bus. The receiving module may manage packets to be received to prevent retransmission request packets to the transmitting module from being output on the ring bus. Since the transfer module monitors the reserved flag 404 of the outgoing packet and invalidates the packet as necessary, unnecessary packets can be prevented from being circulated on the ring bus, thereby improving the efficiency of data transfer between modules.

In this embodiment, the number of destination modules of a packet is one. However, the number of destinations is not limited to 1, and the data path may branch. This is the case, for example, in Figure 2 when modules 3 and 4 are waiting for an output packet from module 2. That is, the data path after module 2 branches.

In the above embodiments, when the data is successfully transmitted to the processing unit 304, the received packet is invalidated. However, if the packet is similarly invalidated because module 3 successfully received the packet, then module 4 can no longer receive the packet.

Therefore, each module according to the embodiment corresponding to another aspect of the present invention is characterized in that it further includes a packet invalidation processing instruction register, and the packet invalidation processing instruction register can specify when the data is successfully transmitted to the processing unit 304 Whether to allow invalidation of packets.

FIG. 7 is a block diagram showing an example of the arrangement of modules according to the present embodiment. The block diagram of the modules shown in FIG. 7 is basically the same as that shown in FIG. 3 . However, different from FIG. 3 , the receiving unit 311 further includes an invalidation instruction register 701 . In this embodiment, when the preset value of the register is "1", it is allowed to invalidate the received packet by setting the value of the data valid flag 401 when the processing unit 304 receives it successfully. On the other hand, if the preset value is "0", invalidation of the received packet by setting the value of the data valid flag 401 upon successful reception by the processing unit 304 is not allowed. However, the setting specification of the packet invalidation processing command register is not limited to the above.

The invalidation command register 701 is set as follows. When it is assumed that the data paths do not branch, the packet invalidation processing instruction registers of all modules are set to "1". In this case, upon successful reception, the packet is invalidated.

On the other hand, when a plurality of modules wait for an output packet from a certain module, a transmission source module that outputs the packet that the plurality of modules waits for is first specified, and, similarly, a plurality of destination modules that wait for the packet are specified.

Among the plurality of destination modules, a module disposed at a position farthest from the transfer source module along the ring bus is specified, and the invalidation instruction register 701 of this module is set to "1". The invalidation command register 701 of the modules other than this module is set to "0".

For example, when the data path is branched at one position as in the case of modules 3 and 4 in FIG. 2 waiting for an output packet from module 2, the ring bus is traced in the forward direction from module 2 which is the transfer source module . Among modules 3 and 4 waiting for packets, module 4 is deployed at a position farthest from module 2 . Thereby, the invalidation command register 701 of the module 3 is set to "0", and the invalidation command register 701 of the module 4 is set to "1".

Processing in the processing data transmitting unit 303 and receiving unit 311 in this embodiment will be described below with reference to FIG. 8 . Referring to FIG. 8 , the package identification unit 301 acquires a package from a module located in the previous stage in step S801 . The packet identifying unit 301 checks in step S802 whether the data valid flag 401 of the packet is "1". If the data valid flag 401 is "1" (YES in step S802 ), the process advances to step S803 . On the other hand, if the data valid flag 401 is not "1" ("No" in step S802), the process ends.

The packet identifying unit 301 checks in step S803 whether the transmission source ID 402 of the packet is equal to a preset waiting packet ID. If it is determined that the two IDs are equal to each other (YES in step S803), the process advances to step S804. On the other hand, if it is determined that the two IDs are not equal to each other (NO in step S803 ), the process ends.

The processing data transfer unit 303 checks in step S804 whether the processing unit 304 is ready to exchange data. If it is determined that the processing unit 304 is ready to exchange data (YES in step S804 ), the process advances to step S805 . On the other hand, if it is determined that the processing unit 304 is not ready to exchange data (NO in step S804), the process advances to step S806.

In step S805 , the packet reception unit 302 extracts the processing data from the packet, and transfers it to the processing data transfer unit 303 , which transfers the data to the processing unit 304 . Then, the process advances to step S807. In step S806, the packet reception unit 302 instructs the packet modification unit 308 to set the reservation flag 404 of the packet to "1".

On the other hand, the packet receiving unit 302 checks in step S807 whether the preset value of the invalidation command register 701 is "1". If it is determined that the preset value is "1" (YES in step S807), the process proceeds to step S808. On the other hand, if it is determined that the preset value is not "1" ("No" in step S807), the process ends. In step S808, the packet receiving unit 302 instructs the packet modifying unit 308 to set the data valid flag 401 to "0".

As described above, even when the data path is branched, since the module includes the invalidation instruction register 701 set as necessary, the packet can be transferred to all the plurality of waiting modules.

other embodiments

It is also possible to perform the functions of the above-described embodiments by reading and executing a program recorded on a storage device by a computer (or a device such as a CPU or an MPU) of a system or an apparatus, and by reading and executing a program by a computer of a system or an apparatus by, for example, reading and A method of executing a program recorded on a storage device to execute the functions of the above-described embodiments to perform the respective steps thereof realizes aspects of the present invention. For this purpose, the program is supplied to the computer, for example, via a network or from various types of recording media (for example, computer-readable storage media) serving as storage devices.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and equivalent structures and functions.

This application claims the benefit of Japanese Patent Application No. 2009-043148 filed on February 25, 2009, the entire contents of which are hereby incorporated by reference.

Claims (8)

1. an information processor, described information processor comprises a plurality of modules, described a plurality of module is connected with ring bus, and each in described a plurality of module is configured to receive the bag of storage data and after predetermined processing, this bag be sent to another adjacent block from an adjacent block, wherein, at least one in described a plurality of module comprises:

Recognition unit, whether be configured to bag that bag that identification receives from described adjacent block received to determine and be will be by the bag of self resume module;

Receiver is configured to: if described recognition unit is determined the bag receive, be by the bag of self resume module, to receive and to want processed data;

Processor, be configured to process the data that receive;

Setup unit is configured to: if described processor is not ready for deal with data, at least one that set in received bag in being used to indicate processor is not ready for processing the reservation mark of the data in the bag received; And

Conveyer, the bag that is configured to have described reservation mark is sent to another module.

2. according to the device of claim 1, wherein, in the situation that received bag is by self module output and have described reservation mark, the described conveyer bag that transmission receives with changing.

3. according to the device of claim 1, wherein, if described processor processes data, described setup unit is set as having the value that designation data is invalid by the significant notation of the validity of the designation data in received bag.

4. according to the device of claim 3, wherein, if described receiver receives the data and the bag with reservation mark of initial value that comprise by self resume module, described setup unit is set as having the value that designation data is invalid by the significant notation of the validity of the designation data in received bag.

5. the method for operation of an information processor, described information processor comprises a plurality of modules, described a plurality of module is connected with ring bus, and each in described a plurality of module is configured to receive the bag of storage data and after predetermined processing, this bag be sent to another adjacent block from an adjacent block, wherein, at least one execution in described a plurality of modules of described method comprise following steps:

Whether the bag that the bag that identification receives from described adjacent block is received to determine is will be by the bag of self resume module;

Data in the bag that control processor is identified with processing;

If described processor is not ready for deal with data, at least one that set in received bag in being used to indicate processor is not ready for processing the reservation mark of the data in the bag received; And

The bag that will have described reservation mark is sent to another module.

6. according to the method for claim 5, wherein, in the situation that received bag is by self module output and have described reservation mark, the conveyer bag that transmission receives with changing.

7. according to the method for claim 5, wherein, in setting step, if described processor processes data is set as the significant notation of the validity of the designation data in received bag having the value that designation data is invalid.

8. according to the method for claim 7, wherein, in setting step, if receiver receives the data and the bag with reservation mark of initial value that comprise by self resume module, the significant notation of the validity of the designation data in received bag is set as to there is the value that designation data is invalid.

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