JPH09114733A - Non-aligned data transfer mechanism in cache storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer non-aligned data between a cache and a register. SOLUTION: Two cache memories 10a and 10b for holding the copy of the main storage of addresses whose lower fifth bit is an odd number and an even number in terms of line units are provided and the respective cache memories 10a and 10b output a byte string for one word corresponding to the value of the lower four bits of the inputted address in a hit line. A data selector 42 selects one of outputs for respective bytes and outputs it to a general purpose register 21 based on byte selection signals 40. Based on the value of the lower five bits of a reference address 22, a cache selector 36 controls the independent operation of the cache memory 10a or the cache memory 10b by the reference address 22 or the parallel operation of the operation of the cache memory 10a by the reference address 22 and the operation of the cache memory 10b by the reference address 22 or the reference address for which '1' is added to the fifth bit in it and generates the byte selection signals 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor for performing image processing and encoding processing, and more particularly to a non-aligned data transfer mechanism in a cache storage device for transferring non-aligned data with a general-purpose register.

[0002]

2. Description of the Related Art When performing real image processing or computer graphics processing, it may be necessary to perform many low-precision calculations. Such an operation often does not require the operation accuracy of the arithmetic logic operation unit of a general-purpose microprocessor, and it is difficult to say that the operation unit is effectively used. To solve this problem, a method has been proposed in which an arithmetic unit is divided and a plurality of low-precision arithmetic operations are simultaneously performed.
It is used in some microprocessors such as the UltraSPARC from the Microsystems. When such a low-precision parallel operation instruction is used, the start address of the data required for calculation often changes dynamically, and the start address of the data is not always an address in word units. Data in which the start address is not a word unit address is called unaligned data. However, a microprocessor, especially a RISC processor, has a structure that can efficiently load and store data in the case of an address in word units that matches the register length, and when loading and storing unaligned data, it is special. In many cases, instructions and processing are required, and low-precision parallel operation instructions cannot always be used efficiently.

For example, MIPS Technology
Inc. R3000, R4000 and other instruction sets include lwl (Load Word Left), lw
r (Load Word Right), swl (St
ore Word Left), swr (Store
An instruction called "Word Right" is defined ("MIPS RISC Architecture").
e ", Prentice Hall, pp. A-42.
A-45, pp. A-76 to A-79). By using this instruction in combination, loading and storing of unaligned data can be realized. The lwl instruction loads the specified byte in memory into the rightmost byte of a register, loads the data sequentially toward the word in memory and the low byte of the word in register, and then loads the least significant byte of the word in memory. This is an instruction that performs the same processing up to bytes. On the other hand, lwr is an instruction to load from the leftmost byte to the upper byte. Therefore, using two instructions with the word unit of the memory as the boundary,
The lower data will be loaded. The swl and swr instructions for writing back the contents of the register to the memory are similar.

FIG. 8 shows a configuration example of a cache memory device in a conventional microprocessor having such an instruction and a connection example of a general-purpose register. In the example shown in the figure, the general-purpose register 21 has a length of 32 bits and 4 bytes, and corresponds to an architecture of 1 word and 4 bytes.

The cache memory 10 'is a cache memory for data, and has, for example, a memory section having a plurality of sets of a data memory array 11, a tag memory array 12, and an effective bit 13 each having a capacity of 16 bytes (4 words), and other than that. Control unit, that is, the index address 2 in the reference address 22 given to the cache memory 10 '.
Decoder 14 for selecting the corresponding set in the memory unit based on 4 and a total of four switch gates 26 'for selecting the data output from the data memory array of the selected set through the data line 16 in word units. Address 22
Selector 17 'for controlling the switch gate 16' based on the word / byte address 25 therein, reference address 2
Address comparator 18 for comparing the tag address 23 in 2 with the contents of the tag memory array 12 of the selected set, and the hit-miss result based on the output of the address comparator 18 and the valid bit 13 of the selected set. A validity determiner 19 for outputting a signal 20 and four data lines 27 connected to each byte output of each switch gate 26 '.
a-27d, a sense amplifier 32 connected to these data lines 27a-27d, and a control unit including a write cell 44 in which store data is set.

When the reference address 22 is given and a load request is issued to the cache memory 10 ', the decoder 14
Refers to the index address 24 of the reference address 22 and selects the corresponding set in the memory section. In the example of FIG. 8, a shaded group is selected. On the other hand, the address comparator 18 compares the tag address 23 of the reference address 22 with the output from the tag memory array 12 of the selected set, and the content of the selected data memory array 15 corresponds to the reference address 22. Check whether the contents. Then, this address comparator 18
Based on the result of the determination and the valid bit 13 of the selected group, the validity determiner 19 determines whether the contents of the data memory array 15 are valid or invalid, and outputs the determination result as a hit-miss result signal 20. As shown in FIG. 9, the selector 17 ′ has two bits (A 3, A 3) in the reference address 22.
2) is inputted as a word / byte address 25, and it is constituted by a decoder 30 which activates one of the switch gates 26 'according to the result of decoding, and the content of the corresponding line is valid and coincides with the reference address 22. In the case, one switch gate 26 'corresponding to the word byte address 25 is activated. Then, one word composed of 4 bytes on the right side of the data memory array 15 selected by the switch gate 26 ′ is amplified by the sense amplifier 32 via the data lines 27 a to 27 d and output to the read data line 35. .

Now, in order to execute the above-mentioned lwl and lwr instructions, the cache memory 10 'and the general-purpose register 2 are used.
1 and the read data alignment device 7 as shown in FIG.
0 and a data selection device 71 are provided. The read data alignment device 70 plays a role of aligning designated data in the memory with upper bytes and lower bytes. For example, [1
Byte data located at 5-8] bits is converted to [31-2]
4] Perform processing to restore the bit position. Further, the data selection device 71 selects the byte data from the general-purpose register 21 to hold the value stored in the general-purpose register for the byte field in which writing is not caused by lwl and lwr, and the byte in which the writing occurs. For the field, processing for selecting byte data from the read data alignment device 70 is performed. With such a device, loading of unaligned data can be realized using two instructions, that is, two instruction cycles.

In the case of the store operation, the input data to be stored is from the write data line 34 through the write data alignment device 72, and the size of the input data (1 byte, half word, 1 word) is the input data size information line. 33 is input to the cache memory 10 ′ and is set to any word position selected by the output of the selector 17 ′ in the write cell 44 and the output of the input data size information line 33. It is written to the appropriate word position in array 15.

However, as the operating frequency of the microprocessor is improved, the read data alignment device 7
It has become difficult to perform the operations including 0, the write data alignment device 72, and the data selection device 71 within one cycle which is a basic time unit of the processing of the microprocessor. So, for example, Digital Equipment
The tCorporation Alpha architecture does not define not only load and store of unaligned data but also byte load, store, etc. as an instruction set in order to realize a high operating frequency. Therefore, the read data alignment device 70, write The data aligning device 72 and the data selecting device 71 are not required, and a high operating frequency is realized.

Further, in a mode in which the register or arithmetic unit of the microprocessor is directly connected to the memory without passing through the cache memory, a mechanism for realizing loading and storing of unaligned data with one instruction is disclosed in, for example, Japanese Patent Laid-Open No. 4-35.
It is proposed in Japanese Patent No. 9334. FIG. 10 shows an example of the configuration. In the figure, a microprocessor 87
When the head address A of the data is output, the address increment signal generation block 82 causes the lower bits 83 and 84 of the address A and the byte control signals 80a-8.
0d is used to generate address increment signals 81a to 81c for the memory block 88. The memory block 88 has address increment signals 81a-8.
When 1c is input, the address area obtained by adding 1 to the specified address is accessed. This gives 1
It makes it possible to load and store unaligned data in every bus cycle.

[0011]

As described above, the loading and storing of unaligned data is an essential function when using a low-precision parallel operation instruction, etc., but it requires two instruction cycles to operate and operation. There is a problem that there is a great possibility that it will hinder the improvement of the frequency. Further, when it is not possible to determine whether the load data and the store data are the aligned data or the unaligned data only at the time of execution, it is necessary to judge the condition or to treat the data as the unaligned data.

Further, the method of directly connecting the memory does not correspond to the method of placing the cache memory inside and outside the microprocessor to load and store the data all at once to hide the latency of the main storage device. There is a problem that it is not suitable for the usage of the high speed microprocessor.

It is an object of the present invention to extend these cache memories, which are widely used in general-purpose processors, to provide a mechanism for efficiently transferring non-aligned data between the cache and general-purpose registers. To solve.

[0014]

According to the present invention, a selector in a cache memory, which conventionally selects data in word units, is expanded, and all address parts are decoded in the cache, so that data can be stored in byte units. I am able to select. This gives 1
Inconsistent data can be loaded and stored between lines. In addition, in order to deal with the case where the non-matching data exists across the cache line, in one configuration, the address bit that is one bit higher than the bit that identifies the data in the cache line is an even number. If a cache memory for odd numbers and a cache memory for odd numbers are prepared and both cache lines are crossed, both caches are accessed at the same time, and in the case of loading, the data output from each is stored, and in the case of storing Is solved by selecting the data to be input to each in byte units. In other configurations, the cache is configured with multiple ports so that multiple lines can be accessed at the same time. In the case of a load, the data output from each is stored, and in the case of a store, the data input to each is stored. It is solved by selecting in byte units. Hereinafter, the present invention will be described in more detail with reference to the drawings. However, the following disclosure is merely an example of the present invention, and does not limit the technical scope of the present invention.

[0015]

1 is a block diagram of an embodiment of a cache storage device according to the present invention. The cache memory device of this example is a cache memory 10a for odd lines.
A cache memory 10b for even lines, a data selector 42, a hit / miss determination device 41, and an adder 4
5 and a cache selector 36 for controlling them, a main part thereof is configured. Reference numeral 21 is a general-purpose register that holds data read from the cache storage device or data to be written in the cache storage device, and has a capacity of 32 bits and 4 bytes in this example.
It corresponds to the architecture of 1 word 4 bytes. Also,
Reference numeral 22 is a reference address related to the load request or the store request, and is composed of 32 bits in this example.
In this reference address 22, the lower 4 bits are the word / byte address 25, the 1st bit of the lower 5th is the odd / even selection bit 37, and the bit string from the lower 6th bit to the most significant bit is divided into two, and the upper side is As the tag address 23, the lower side is used as the index address 24, which is distributed and used in each unit as shown in the drawing.

Cache memory 10a for odd lines
Is a cache memory for holding a copy of the main memory of an address in which the lower 5th bit is an odd number (that is, 1), and the even line cache memory 10b is
On the contrary, it is a cache memory for holding a copy of the main memory at an address where the lower 5th bit becomes an even number (that is, 0) in units of lines. Which cache memory 1
For 0a and 10b, at the time of a cache hit, at the time of a load operation, one word length byte starting from the byte indicated by the lower 4 bits of the input address (that is, word / byte address 25) in the hit line The function of outputting a column, the value of the lower 4 bits of the input address (that is, the word / byte address 25), the input data size information from the input data size information line 33, and the byte selection signal 40 during the store operation Accordingly, it has a function of selectively setting the input data from the general-purpose register 21 in a byte unit to the internal write cell and then selectively writing to the corresponding byte position in the hit line.

FIG. 2 shows a configuration example of the cache memories 10a and 10b, and FIG. 3 shows a more detailed configuration example of a part thereof.
In FIGS. 2 and 3, reference numeral 11 denotes a data memory array for holding a copy of the main memory in line units (that is, in units of 4 words in this example), and a plurality of 4-word 16-byte capacity memories are prepared. . Each data memory array 11
The identification of each byte therein is performed by the lower 4 bits of the reference address 22, that is, the word byte address 25. Reading and writing of the same byte position in each data memory array 11 can be performed through a common data line 16, and these common data lines 16 have a total of 16 switch gates 26 and 16-byte 4-word long write cells. Connected to each byte position of 44, and also switch gate 2
Reference numeral 6 denotes four data lines 27a, 27b, 27c, each having a 1-byte width (the number equal to the number of bytes forming a word).
27d is connected in the relationship as shown by the solid line and the broken line in FIG. That is, through the switch gate 26, continuous 4 bytes (1 word) of data starting from an arbitrary byte position in the same data memory array can be taken out to separate data lines 27a, 27b, 27c and 27d. ing. Furthermore, each data line 27a, 27b,
A sense amplifier 32 is connected to 27c and 27d, and a read data line 35 is connected to the sense amplifier 32. In addition, the write cell 44 is provided with a gate 48 for controlling whether or not to set the data on the write data line 34 for each byte, and the gate 48 has an input data size information line 33, an output of the selector 17 and The byte selection signal 40 is input. Each data memory array 11 is provided with a tag memory array 12 and a valid bit 13 corresponding to it.

On the other hand, in FIG. 2, 29 indicates that the operation of the self cache memory 10 is valid when the cache selection signal 39 (corresponding to 39a and 39b in FIG. 1) applied to the self cache memory 10 is active. , Tag address 23 from outside, index address 24,
It is an enabler that distributes the word / byte address 25 to each internal section. The decoder 14 uses this enabler 29.
When the index address 24 is input from, the data memory array 11 holding the line corresponding to the index address is searched and selected. In the selected data memory array, the data of each byte is read and output to the switch gate 26 during the load operation, and the input data in the write cell 44 is written into the corresponding byte position during the store operation. The selected data memory array is designated by the reference numeral 15 in FIG.
To distinguish it from other data memory arrays.

The selector 17 inputs the word / byte address 25 from the enabler 29, and opens only the switch gate 26 necessary for the word / byte address 25 at the time of the load operation, thereby selecting the data selected by the decoder 14. A byte string for one word length starting from the byte indicated by the input word / byte address 25 in a line in the memory array 15,
The data lines 27a, 27b, 27c and 28d are connected. Further, at the time of the store operation, a signal for permitting writing is output only to the necessary gate 48 according to the value of the word / byte address 25, and together with the information of the input data size information line 33 and the information of the byte selection signal 40, Control is performed to set the input data only to the required byte position of the write cell 44.

The selector 17 as described above has four decoders 30a, 30b, 30c and 30 as shown in FIG.
d, three adders 31a, 31b, 31c, an AND gate 46, and a NOR gate 47.
The decoder 30a is the upper 2 of the word / byte address 25.
4 bits 16 in the data memory array 15 selected by the decoder 14 by decoding the bits A3 and A2
Among the bytes, the switch gate 26 and the gate 48 at the positions shown in the figure are controlled to select any one of the bytes of the lower addresses 0x3, 7, b and f. Decoder 30b
Is the upper 2 bits A3 of the word / byte address 25.
The 2 bits output from the adder 31a for adding the value of A2 and the logical product condition value of the lower 2 bits A1 and A0 are decoded, and one of the bytes of the lower addresses 0x2, 6, a, and e is decoded. The switch gates 26 and 48 at the positions shown in the figure are controlled to be selected. The decoder 30c decodes the 2 bits output from the adder 31b that adds the values of the upper 2 bits A3 and A2 of the word / byte address 25 and the value of the second bit A1 to the lower address 0x.
The switch gate 26 and the gate 48 at the positions shown in the figure are controlled to select any one of the bytes 1, 5, 9 and d. The decoder 30d receives the values of the upper 2 bits A3 and A2 and the lower 2 bits A1 and A0 of the word / byte address 25.
Of the lower address 0x0, 4,
The switch gates 26 and 48 at the positions shown in the figure are controlled to select either one of the bytes 8 and c.

Referring again to FIG. 2, 18 is the tag address 23 distributed from the enabler 29 and 18 is the decoder 1.
4 is an address comparator for comparing with the tag address in the tag memory array corresponding to the data memory array 15 selected by 4. Further, 19 is the output of the address comparator 18 and the valid bit 1 corresponding to the data memory array 15 selected by the decoder 14.
It is a validity determiner that generates a hit-miss result signal 20 indicating the presence or absence of a cache hit, based on the value of 3.

Referring again to FIG. 1, the cache selector 36 determines that the odd / even selection bits 37 of the reference address 22.
And the word / byte address 25 are input, and the index addition signal 38, the odd number cache selection signal 39a, and the even number cache selection signal 39b are supplied to each section according to their values. FIG. 4 shows the values of the odd / even selection bit 37 and the word / byte address 25 and the values of the odd cache selection signal 39a, the even cache selection signal 39b active (◯), inactive (×), and the index addition signal 38. Show the relationship. Further, the cache selector 36 uses the odd / even selection bits 37 of the reference address 22.
And a byte select signal 40 based on the word byte address 25. Based on the byte selection signal 40, the data selector 42 should select the byte string output from the cache memories 10a and 10b to the read data line 35 in each byte unit and output it to the general register 21 during the load operation. Generate word data.

FIG. 5 shows the cache memory 1 for odd lines.
An image of data stored in the cache memory 10b for 0a and even lines is shown. In the example of the figure, addresses 0x70ac3010 to 0x70 of the main memory
Address 0x70 in which 64-byte data at address ac304f is stored in the cache storage device of FIG. 1 and the value of the lower 5th bit of the address is 1
16 bytes of addresses ac3010 to 0x70ac301f and addresses 0x70 ac3030 to 0x70
The 16 bytes of the address ac303f are stored in the cache memory 10a for odd lines and the 16th byte of the addresses 0x70ac3020 to 0x70ac302f and the 16 bytes of the addresses 0x70ac3040 to 0x70ac304f are stored so that the value of the lower 5th bit of the address is 0. Is an even line cache memory 10
It is stored in b.

The operation of this embodiment will be described below with reference to FIGS.

(1) When the reference address is on a 4-byte boundary (A) Load operation For the general-purpose register 21, for example, 0x70ac3010
When loading the 4-byte data at address 0x70ac3013 from address number 0x70ac3 to reference address 22
By designating 010, a load request is issued to the cache storage device. In the case of such a reference address 22, since the odd / even selection bit 37 is odd and the word / byte address 25 is other than "1101" and "111X", the cache selector 36 activates the odd cache selection signal 39a, Even cache selection signal 39
b is made inactive (see FIG. 4). In addition, for all bytes, the byte selector signal 40 for selecting the output side of the cache memory 10a for odd lines is used as the data selector 42.
Output to

When the odd cache select signal 39a becomes active, the enabler 29 in the cache memory 10a for the odd line starts the operation of the load operation of the cache in response to the load request, and the tag address 23 of the reference address 22 is used as the address comparator. 18
The index address 24 is distributed to the decoder 14, and the word / byte address 25 is distributed to the selector 17. The decoder 14 refers to the index address 24 and
Select the data memory array 15 in which the line containing the byte at address x70ac3010 is to be stored. Further, the selector 17 selects 0x0 to 0 of the byte string output from the data memory array 15 to the data line 16 based on the word / byte address 25 (0000 in this case).
Control the appropriate switch gate 26 to select x3. Further, the address comparator 18 uses the tag address 2
3 and the output from the tag memory array 12 are compared, and the content of the selected data memory array 15 is the reference address 2
Check whether it is the contents of 2. And the validity judging device 1
9 based on the comparison result of the address comparator 18 and the content of the valid bit 13
It is determined whether the contents of 5 are valid or invalid, and the hit-miss result signal 20 is generated.

When the contents of the data memory array 15 are valid and match the reference address 22, the data lines 27a,
The data output to the switches 27b, 27c, and 27d through the switch gate 26 is amplified by the sense amplifier 32 and output to the read data line 35 as read data. Then, the data selector 42 uses the byte selection signal 4
According to 0, the data from the cache memory 10a for odd lines is selected in all bytes, and the general register 21
Write to. Therefore, in the case of the storage contents shown in FIG. 5, 0x70 is assigned to the data line 27a and 0x0 is assigned to the data line 27b.
a, 0x65 is output to the data line 27c, and 0x6e is output to the data line 27c, so one word having a value of 0x700a656e is stored in the general-purpose register 21.

In the above example, the odd / even selection bit 37 of the reference address 22 is odd and the word / byte address 25 is other than "1101" or "111X".
The cache memory 10a for the odd line is selected, but the odd / even selection bit 37 of the reference address 22 is even and the word / byte address 25 is "1101",
In cases other than "111X", the cache memory 10b for even lines is selected.

(B) Store Operation In the case of store operation, the data to be stored in the general-purpose register 21 is applied to the write cells 44 in the cache memories 10a and 10b for odd and even lines through the write data line 34 as shown in FIG. To be done.
Further, the size of the input data is notified to the cache memories 10a and 10b by the input data size information line 33. The input data size information line 33 is used to realize a 1-byte unit store or a half-word unit store other than the 1-word unit store, and is not essentially related to the unaligned data transfer of the present invention. Therefore, hereinafter, it is assumed that the input data size information line 33 is instructing to store in units of one word. Furthermore, the cache selector 36
From the byte selection signal 40 to each cache memory 10a,
It is input to the gate 48 in the previous stage of the write cell 44 of 10b. The operation when the reference address 22 is given and a store request is issued is almost the same as the load operation, but during the store operation, the output of the selector 17 and the byte select signal 40 cause the desired gate 48.
Only valid. For example, when data is stored in 4 bytes of addresses 0x70ac3010 to 0x70ac3013, 0x70ac30 is stored in the reference address 22.
A store request is made by designating address 10. At this time, under the control of the cache selector 36, a single caching operation is performed by the odd line cache memory 10a, and a byte selection signal 40 indicating that the odd line cache memory 10a side is selected for all bytes is output. Therefore, cache memory 1 for odd write
The selector 17 at 0a determines the write cell 44 based on the word / byte address 25 (0000 in this case).
The gate 48 is controlled so that 0x0 to 0x3 of the byte sequence of 0 are valid. Further, since the byte selection signal 40 instructs all bytes to select the odd line cache memory 10a side, the byte selection signal 40 controls the gate 48 to make all the byte strings of the write cell 44 valid. . Therefore, one word of 4 bytes of the general register 21 is set to the byte positions of 0x0 to 0x3 of the write cell 44, and then written to the byte positions of 0x0 to 0x3 of the hit data memory array 15 through the data line 16.

(2) When the reference address 22 does not come to a 4-byte boundary and does not straddle cache lines (A) Load operation When the reference address 22 does not come to a 4-byte boundary, a similar access is made in the conventional example. Is not allowed. However, according to the present invention, such access is possible. As a specific example, the operation when the reference address is 0x70ac3011 will be described.

0x70ac3011 at the reference address 22
When a load request is specified, the cache selector 36
Since the odd / even selection bit 37 is odd and the word / byte address 25 is other than "1101" and "111X", the odd cache selection signal 39a is activated and the even cache selection signal 39b is deactivated (FIG. 4). reference). In addition, a byte selection signal 40 for selecting the output side of the cache memory 10a for odd lines for all bytes is output to the data selector 42. The following operation is the same as the access to the address 0x70ac3010 described above, but the decoder 30 which constitutes the selector 17
Since 2 bits of 00 are input to a, 30b, and 30c, among the outputs of the selected data memory array 15,
The decoder 30a has the address 0x3, and the decoder 30b has the address 0x3.
For the address 2, the decoder 30c selects the value 0x1, and on the other hand, since 2 bits of 01 are input to the decoder 31d, the address 0x4 is selected.

Therefore, in the case of the storage contents shown in FIG. 5, 0x70 is assigned to the data line 27a and 0x0 is assigned to the data line 27b.
a, data 0x65 is output to the data line 27c, and data 0x85 is output to the data line 27c.
A value of 0x700a6585 is stored in the general-purpose register 21 via the read data line 35 and the data selector 42. That is, it means that the data string in which the reference address 22 is not on the 4-byte boundary can be read.

Referring now to FIG. 5, 0x70ac
The 4-byte value starting at address 3011 is 0x8570
0a65, the general register 2 as described above
The value read to 1 is 0x700a6585, and the data serving as the highest address is stored in the lowest byte position of the register in this case. Therefore, when handling this data as word data, it is necessary to rotate and shift this value, but when performing the low-precision parallel operation described above, the data that is the highest address is not always the position of the highest byte of the register. There is no problem because it is not necessary to be stored in, and it suffices that the registers that perform the calculation be associated with each other.

For example, In such a program, when the loop start location is specified by a variable and is indefinite, the conventional example cannot use the low-precision parallel operation instruction, but according to the present embodiment, the low-precision parallel operation instruction is used. It becomes possible to do. In this case, if the lower 2 bits of the addresses of the array variables a [0] and b [0] are the same, the registers that perform the operation can be associated with each other, and therefore the order of arrangement of the bytes in the registers does not matter.

In the above example, since the odd / even selection bit 37 of the reference address 22 is odd and the word / byte address 25 is other than "1101" and "111X", the cache memory 10a for the odd line is Although selected, the odd / even selection bit 37 of the reference address 22 is even and the word / byte address 25 is "110".
In cases other than "1" and "111X", the cache memory 10b for even lines is selected and the same operation is performed.

(B) Store Operation The operation when the reference address 22 is not on the 4-byte boundary and does not straddle the cache lines is almost the same as the store operation of (1). For example, 0x
When storing data in 4 bytes from address 70ac3011 to address 0x70ac3014, reference address 22
A store request is made by specifying the address 0x70ac3011, but at this time, the cache memory 10a for the odd-numbered line performs the independent caching operation, and the selector 17 selects the word / byte address 25 (in this case,
0001), the gate 48 is controlled so that 0x1 to 0x4 of the byte string of the write cell 44 are valid. Further, the byte selection signal 40 is instructed to select all the bytes from the odd line cache memory 10a. Therefore, one word of 4 bytes of the general register 21 is set to the byte positions of 0x1 to 0x4 of the write cell 44, and then written to the byte positions of 0x1 to 0x4 of the hit data memory array 15 through the data line 16.

(3) When the reference address 22 is not on a 4-byte boundary and straddles cache lines (A) Load operation: The reference address 22 is not on a 4-byte boundary and straddles cache lines. In this case, that is, when the word / byte address 25 is either "1101" or "111X" and word access is performed, the access is naturally not permitted in the conventional example, but it is possible in the present invention.
As a specific example, the operation when the reference address is 0x70ac301e will be described.

0x70ac301e at the reference address 22
When a load request is specified, the cache selector 36
Since the odd / even selection bit 37 is odd and the word / byte address 25 is "1110", both the odd cache selection signal 39a and the even cache selection signal 39b are activated, and the index addition signal 38 is set to "1". Also, a byte selection signal 40 indicating that the upper 2 bytes select data from the odd-numbered line cache memory 10a and the lower 2 bytes select data from the even-line cache memory 10b are output to the data selector 42. .

The operation of the cache memory 10a for odd-numbered lines is the same as that described above, but since 2 bits of 11 are input to the decoders 30a and 30b forming the selector 17, the selected data memory array is selected. Of the 15 outputs, the decoder 30a selects the address 0xf and the decoder 30b selects the address 0xe, while the decoders 30c and 30d receive 2 bits of 00,
The decoder 30c has the address 0x1, and the decoder 30d has the address 0x1.
Select address 0 respectively. Therefore, in the case of the storage contents shown in FIG. 5, 0x65 is used for the data line 27a, 0x6e is used for the data line 27b, 0x65 is used for the data line 27c, and data line 2 is used in the cache memory 10a for odd lines.
Data 0x6e is output to 7c, is amplified by the sense amplifier 32, and is output to the read data line 35 of the cache memory 10a for odd lines.

On the other hand, the cache memory 1 for even lines
In 0b, the adder 45 causes the index address 24
Reference address 22 with the value of +1 added, that is, 0x70a
c302e is given. The operation of the cache memory 10b for even lines is the same as the operation of the cache memory 10a for odd lines, and 2 bits of 11 are input to the decoders 30a and 30b forming the selector 17, so that they are selected. Of the outputs of the data memory array 15, the decoder 30a outputs the address 0xf to the decoder 30b.
Selects the address 0xe, while the decoder 30
Since 2 bits of 00 are input to c and 30d, the decoder 30c selects the address 0x1 and the decoder 30d selects the address 0x0. Therefore, in the case of the storage contents shown in FIG. 5, 0x75 is applied to the data line 27a and 0 is applied to the data line 27b in the cache memory 10b for even lines.
x7e, data line 27c has 0x55, data line 27c
Is output to the read data line 35 of the even-numbered cache memory 10b as a result of being amplified by the sense amplifier 32.

Then, the data selector 42 selects the data from the cache memory 10a for the odd lines for the upper 2 bytes and the data from the cache memory 10b for the even lines for the lower 2 bytes according to the byte selection signal 40. Then, the general register 21 is written. Therefore,
In the case of the storage contents shown in FIG. 5, 0 is stored in the general-purpose register 21.
One word having a value of x656e553e will be stored.

When both the odd and even cache memories 10a and 10b are accessed, the hit / miss result signal 20 of both caches may be different. In this case, the hit-miss determination device 41 outputs the hit-miss result signal 43 as a result of the miss.
If a cache miss occurs, the contents of the cache are replaced with the requested address, and then the access is performed again.

(B) Store Operation When the reference address 22 is not on a 4-byte boundary and straddles cache lines, parallel operations are performed by the cache memories 10a and 10b for odd and even lines. For example, from 0x70ac301e to 0x70a
To store data in 4 bytes at address c3021,
The address 0x70ac301e is designated as the reference address 22, and the store request is made. At this time, the selector 17 in the cache memory 10a for the odd line is based on the word / byte address 25 (1110 in this case) and the byte of the write cell 44. 0x0,0x of the columns
The gate 48 is controlled so that 1,0xe and 0xf are valid. However, since the byte selection signal 40 indicates that the upper 2 bytes select data from the cache memory 10a for odd lines, the upper 2 bytes of the 4 bytes 1 word of the general-purpose register 21 are the write cells 44. 0xe
Set to the byte position of 0xf, and then through the data line 16 to the 0 of the hit data memory array 15.
It is written in the byte position of xe to 0xf. On the other hand, the selector 1 in the cache memory 10b for even lines
7 also has a word byte address 25 (in this case, 111
0x of the byte sequence of the write cell 44 based on 0)
Gate 0 to make 0, 0x1, 0xe, 0xf valid
Control. However, since the byte selection signal 40 indicates that the lower 2 bytes select the data from the even-numbered line cache memory 10b, 4 of the general-purpose register 21 is selected.
The lower 2 bytes of the byte 1 word are set to the byte positions of 0x0 to 0x1 of the write cell 44, and then the data memory array 1 which is hit through the data line 16 is hit.
5 is written to the byte positions of 0x0 to 0x1.

FIG. 6 is a block diagram of another embodiment of the cache memory device of the present invention. The cache storage device of this example includes a data memory array 51 having a dual port structure,
A tag memory array 52 and a valid bit 53 are provided. Then, as these are expanded to the dual port structure, the decoders 14a and 14b, the selectors 17a and 1
7b, address comparators 18a and 18b, validity determiners 19a and 19b, sense amplifiers 32a and 32b, write cells 44a and 44b, and data lines 27a to 27h can be duplicated and a cache can be searched for two reference addresses at the same time. It is structured. Note that selector 1
The detailed configuration around 7a, 17b and the write cells 44a, 44b is the same as that shown in FIG.

In the cache selector 54, the values of the lower 4 bits of the reference address 22 are "1101" and "11".
In the case of other than "1X", the 2-line search signal 56 is invalidated. In the case of "1101" and "111X", the value of the index addition signal 37 is set to 1 and the 2-line search signal 56 is set.
Is a mechanism that enables. It also has a function of outputting the byte selection signal 40 corresponding to the value of the lower 4 bits of the reference address 22 to the data selector 42 and the cache memory 50.

The operation of the embodiment shown in FIG. 6 will be described below.

(1) When the reference address is on a 4-byte boundary (A) Load operation For the general-purpose register 21, for example, 0x70ac3010
When loading the 4-byte data at address 0x70ac3013 from address number 0x70ac3 to reference address 22
By designating 010, a load request is issued to the cache storage device. In the case of such a reference address 22, the word / byte address 25 is "1101", "111X".
Other than that, the cache selector 54 invalidates the 2-line search signal 56 and outputs the byte selection signal 40 to select the read data line 35a side for all bytes.

In the cache memory 50, when the 2-line search signal 56 is invalid, only the cache operation based on the reference address 22 itself is executed. First, the decoder 14a refers to the index address 24 in the reference address 22 and selects the data memory array 15a in which the line including the byte of value 0x70ac3010 is to be stored. In addition, the selector 17a sets the corresponding switch gate 26 to select 0x0 to 0x3 in the byte string output from the data memory array 15a to the data line 16 based on the word / byte address 25 (0000 in this case). Control. Further, the address comparator 18a compares the tag address 23 with the output from the tag memory array 52, and selects the selected data memory array 15
It is checked whether or not the content of a is the content of the reference address 22. Then, the validity determiner 19a determines whether the content of the data memory array 15a is valid or invalid based on the comparison result of the address comparator 18a and the content of the valid bit 53, and generates the hit-miss result signal 20a. .

When the content of the data memory array 15a is valid and coincides with the reference address 22, the data line 27
The data output to the a, 27b, 27c, and 27d through the switch gate 26 is amplified by the sense amplifier 32a and output to the read data line 35a as read data. Then, according to the byte selection signal 40, the data selector 42 reads the read data line 3 for all bytes.
5a side is selected and written in the general-purpose register 21. Therefore, in the case of the storage contents shown in FIG. 5, 0x70 is assigned to the data line 27a, 0x0a is assigned to the data line 27b, and data line 27 is assigned to the data line 27b.
Since 0x65 is output to c and 0x6e is output to the data line 27c, 0x70 is output to the general-purpose register 21.
One word having a value of 0a656e will be stored.

(B) Store Operation In the case of store operation, the data to be stored in the general-purpose register 21 is stored in both write cells 44a and 44 in the cache memory 50 through the write data line 34.
applied to b. In addition, the size of the input data is changed by the input data size information line 33 to the respective write cells 44a, 44a.
b is notified. Furthermore, the byte selector signal 40 is input from the cache selector 54 to the gate 48 (FIG. 3) in the previous stage of the write cells 44a and 44b of the cache memory 50. The operation when the reference address 22 is given and a store request is issued is almost the same as the load operation, but during the store operation, the selector 17a,
17b enables only the gate 48 (see FIG. 3) corresponding to the value of the word / byte address 25. For example, from 0x70ac3010 to 0x70ac301
When data is stored in the 4 bytes of the address 3, the address 0x70ac3010 is designated as the reference address 22 and a store request is made. At this time, the independent caching operation is performed by the reference address 22 itself, and the selector 17
a is a word / byte address 25 (000 in this case)
0) of the byte string of the write cell 44a based on 0).
The gate 48 is controlled so that x0 to 0x3 are valid. Further, in this case, the byte selection signal 40 instructs that all the bytes are selected on the read data line 35a side, and all the bytes of the write cell 44a are validated with respect to the byte selection signal 40. Therefore, based on the logical product of both, one word of 4 bytes of the general register 21 is 0x of the write cell 44a.
The data memory array 15a which is set to the byte position of 0 to 0x3 and then hits through the data line 16
Are written in the byte positions of 0x0 to 0x3.

(2) The case where the reference address 22 is not on a 4-byte boundary and does not extend across the cache lines (as a concrete example, the operation when the reference address is 0x70ac3011 will be described).

(A) Load operation When a load request is made by designating 0x70ac3011 as the reference address 22, the cache selector 54 invalidates the 2-line search signal because the word / byte address 25 is not "1101" or "111X". Also, a byte selection signal 40 for selecting the read data line 35a side for all bytes is output to the data selector 42. The following operation is the same as the access to the 0x70ac3010 value in (1), but since 2 bits of 00 are input to the decoders 30a, 30b and 30c of FIG. 3 which constitute the selector 17a, the selected data is selected. Of the outputs of the memory array 15a, the decoder 30a selects the address 0x3, the decoder 30b selects the address 0x2, and the decoder 30c selects the value 0x1. On the other hand, since the decoder 31d receives 2 bits of 01, it selects 0x4. Select an address.

Therefore, in the case of the storage contents shown in FIG. 5, 0x70 is assigned to the data line 27a and 0x0 is assigned to the data line 27b.
a, data 0x65 is output to the data line 27c, and data 0x85 is output to the data line 27c.
A value of 0x700a6585 is stored in the general-purpose register 21 via a, the read data line 35a, and the data selector 42.

(B) Store operation The operation when the reference address 22 is not on a 4-byte boundary and does not straddle the cache lines is almost the same as the store operation of (2). For example, 0x
When storing data in 4 bytes from address 70ac3011 to address 0x70ac3014, reference address 22
The address 0x70ac3011 is specified for the store request, but at this time, the single caching operation is performed by the reference address itself, and the selector 17a determines the byte of the write cell 44a based on the word / byte address 25 (0001 in this case). Of the columns, 0x1-0x
Gate 48 is controlled so that 4 is valid. The byte selection signal 40 also instructs all the bytes to select the read data line 35a. Therefore, one word of 4 bytes in the general-purpose register 21 corresponds to 0x1 to 0x4 of the write cell 44a.
Of the hit data memory array 15a through the data line 16
Written to byte position 0x4.

(3) When the reference address 22 is not on a 4-byte boundary and straddles cache lines (A) Load operation: The reference address 22 is not on a 4-byte boundary and straddles cache lines. If the word / byte address 25 is "1101" or "111X", the reference address is 0x70ac301.
The operation in the case of e will be described.

0x70ac301e at reference address 22
When a load request specifying
Since the word / byte address 25 is "1110", the index addition signal 37 is set to 1 and the 2-line search signal 5
6 is valid. The above 2 bytes are the output on the read data line 35a side, and the lower 2 bytes are the read data line 35a.
Byte selection signal 40 for selecting each of the outputs on the b side
Is output to the data selector 42.

When the 2-line search signal 56 is valid, in the cache memory 50, the cache search using the reference address 22 itself and the cache search using the reference address obtained by adding 1 to the index address 24 in the reference address 22 are performed at the same time. Done. The former cache search is performed by the decoder 14a, selector 17a, address comparator 18a, validity determiner 19a, etc. (2)
It is executed in the same manner as described in. Further, the latter search based on the reference address 55 obtained by adding 1 to the index address 24 is performed by the decoder 14b, the selector 17b, the address comparator 18b, the validity determiner 19b, etc. in the same manner as the other cache search.

Therefore, the reference address 22 is 0x70ac.
At the time of a load request specifying 301e, 2 bits of 11 are input to the decoders 30a and 30b of FIG. 6 forming the selector 17a, so that the selected data memory array 1
Of the outputs of 5a, the decoder 30a selects the address 0xf and the decoder 30b selects the address 0xe. On the other hand, since 2 bits of 00 are input to the decoders 30c and 30d, the decoder 30c selects the address 0x1 and the decoder 30d.
Selects address 0x0. Therefore, in the case of the storage contents shown in FIG. 5, 0x65 is assigned to the data line 27a, 0x6e is assigned to the data line 27b, and 0x6 is assigned to the data line 27c.
5, data 0x6e is output to the data line 27c, amplified by the sense amplifier 32a and output to the read data line 35a.

On the other hand, in the cache search by the reference address obtained by adding 1 to the index address 24 in the reference address 22, the decoder 3 of FIG. 6 which constitutes the selector 17b.
Since 2 bits of 11 are input to 0a and 30b, of the outputs of the selected data memory array 15, the decoder 30a selects the address 0xf and the decoder 30b selects the address 0xe, while the decoders 30c and 30d. Since 2 bits of 00 are input to the decoder 30, the decoder 30c outputs 0.
The address x1 and the decoder 30d select the address 0x0. Therefore, in the case of the storage contents shown in FIG. 5, 0x75 is assigned to the data line 27e and 0x7e is assigned to the data line 27f.
0x55 for data line 27g and 0x for data line 27h
The data 3e is output, and this is the sense amplifier 32.
It is amplified by b and output to the read data line 35b.

Then, according to the byte selection signal 40, the data selector 42 sets the upper 2 bytes to the read data line 3
The data from 5a is selected, the lower 2 bytes are selected from the read data line 35b, and are written in the general-purpose register 21. Therefore, in the case of the storage contents shown in FIG. 5, one word having a value of 0x656e553e is stored in the general-purpose register 21.

In the case of parallel caching with two reference addresses, the hit-miss result signals 20a and 20b of both caches may be different. In this case, the hit-miss determination device 41 outputs the hit-miss result signal 43 as a result of the miss. If a cache miss occurs, the contents of the cache are replaced with the requested address, and then the access is performed again.

(B) Store operation When the reference address 22 is not on a 4-byte boundary and extends across cache lines, cache search based on the reference address itself and the reference address obtained by adding 1 to the index address is performed in parallel. Done. For example, 0x
When data is stored in 4 bytes from address 70ac301e to address 0x70ac3021, reference address 22
The address 0x70ac301e is specified for a store request, but at this time, in the cache search based on the reference address itself, the selector 17a uses the word / byte address 25 (1110 in this case) to determine the byte string of the write cell 44a. Of which, 0x0, 0x1, 0x
The gate 48 is controlled so that e and 0xf are valid. However, since the byte selection signal 40 indicates that the upper 2 bytes select the read data line 35a side, the upper 2 bytes of the 4 byte 1 word of the general-purpose register 21 are the byte positions of 0xe to 0xf of the write cell 44a. Is written to the byte position of 0xe to 0xf of the hit data memory array 15a through the data line 16. On the other hand, even in the cache search based on the reference address obtained by adding 1 to the index address, the selector 17
b is the word / byte address 25 (in this case, 111
0) of the byte string of the write cell 44b based on 0).
Gate 4 to validate x0, 0x1, 0xe, 0xf
8 is controlled. However, since the byte selection signal 40 indicates that the lower 2 bytes select the read data line 35b side, the lower 2 bytes of the 4 byte 1 word of the general register 21 are the byte positions of 0x0 to 0x1 of the write cell 44b. Is written to the byte position of 0x0 to 0x1 of the hit data memory array 15b through the data line 16.

In each of the above-described embodiments, the cache is duplicated and two lines are searched at the same time, so that the access across the cache lines is realized without increasing the number of cycles. Therefore, the cost may be slightly increased due to the duplication. However, there are some high-performance processors that can execute multiple load and store instructions at the same time. In that case, the cache memory is duplicated, and at the time of unaligned load and store across cache lines, simultaneous execution is possible. The cost increase can be minimized by expanding the configuration to no access.

Further, in each of the above-mentioned embodiments, there is a case where the data of the highest address is not stored in the position of the highest byte of the register. Therefore, when it is used for other than the low-precision parallel operation, it becomes necessary to rotationally shift the data value so that the data can be handled as word data. FIG. 7 is a block diagram of a further embodiment of the present invention which has been expanded to cope with such a problem. In the embodiment of FIG. 1, a byte rotator 60 for performing rotation shift in byte units and a shift amount. Alignment register 61 for holding is added. It should be noted that similar modifications can be made to the embodiment of FIG.

The alignment register 61 includes a general-purpose register 2
The byte information of the lower 2 bits of the address of the data loaded into 1 is stored. When the register alignment instruction is executed, the value loaded into the general-purpose register 21 by the unaligned load instruction is right-shifted in bytes by the byte rotator 60 by the value of the alignment register 61, and the value is written back to the general-purpose register 21. Be done.

For example, when the above-mentioned address 0x70ac3011 is accessed, values are initially stored in the general register 21 in the order of the register 700a6585.
By executing the alignment instruction, the alignment register 61
Since the content of 1 is 1 in this case, a 1-byte rotation shift occurs to the right and the value is written back to the general-purpose register 21, so the content of the general-purpose register 21 becomes 0x85700a65.

Therefore, although it is necessary to add one alignment instruction after the load instruction, it is possible to load the data into the registers in the memory arrangement order with a simpler mechanism than the conventional example.

The embodiments of the present invention have been described above.
The present invention is not limited to the above embodiments, and various other additions and changes are possible. For example, the same can be applied to the case of a cache memory structure in which all the lines are once read and then changed for writing to the cache.

[0069]

As described above, when transferring unaligned data stored across word boundaries between a cache and a register device, conventionally, the data is aligned and transferred in two steps. However, according to the present invention, the transfer can be completed by one transfer. This makes it possible to speed up the processing by combining it with a low-precision parallel operation instruction in the problem that data is stored in byte units or 2-byte units such as in image processing.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an odd line cache memory and an even line cache memory.

FIG. 3 is a block diagram showing a more detailed configuration example of a part of the cache memory.

FIG. 4 is a diagram showing a relationship between values of odd / even selection bits and word / byte addresses, states of odd cache selection signals and even cache selection signals, and values of index addition signals.

FIG. 5 is a diagram showing an image of data stored in a cache.

FIG. 6 is a block diagram of another embodiment of the present invention.

FIG. 7 is a block diagram of yet another embodiment of the present invention.

FIG. 8 is a block diagram showing a conventional cache configuration.

FIG. 9 is a block diagram showing a more detailed configuration example of a part of a conventional cache configuration.

FIG. 10 is a block diagram of a conventional technique for transferring non-aligned data.

[Explanation of symbols]

10, 10a, 10b ... Cache memory 11 ... Data memory array 12 ... Tag memory array 13 ... Effective bit 14, 14a, 14b ... Decoder 15, 15a, 15b ... Selected data memory array 16 ... Data line (8-bit width) 17, 17a, 17b ... Selector 18, 18a, 18b ... Address comparator 19, 19a, 19b ... Validity determination section 20, 20a, 20b ... Hit-miss result signal 21 ... General-purpose register 22 ... Reference address 23 ... Tag address 24 ... Index address 25 ... Word / byte address 26 ... Switch gate 27a, 27b, 27c, 27d, 27e, 27f, 2
7g, 27h ... Data line 29 ... Enabler 30, 30a, 30b, 30c, 30d ... Decoder 31a, 31b, 31c ... Adder 32, 32a, 32b ... Sense amplifier 33 ... Input data size information line 34 ... Write data line 35, 35a, 35b ... Read data line 36 ... Cache selector 37 ... Odd / even selection bit 38 ... Index addition signal 39a ... Odd cache selection signal 39b ... Even cache selection signal 40 ... Byte selection signal 41 ... Hit miss judgment device 42 ... Data selector 43 ... hit miss result signal 44, 44a, 44b ... write cell 45 ... adder 46 ... AND gate 47 ... NOR gate 48 ... gate 50 ... 2-port structure cache memory 51 ... 2-port structure data memory array 52 ... 2-port structure Tag memorial B 53 ... 2-port index address 56 ... 2 line search signal 60 ... byte rotator 61 ... alignment register valid bit 54 ... cache selector 55 ... after the addition of structure

Claims (7)

[Claims] 1. In a processor having means for transferring data required for calculation from a cache storage device to a register device and performing calculation, a basic data length (word length) of data to be transferred specifies a data area. When the length is longer than the unit (byte) to add the address to be transferred and the start address of the data to be transferred does not become an integer multiple of the word length, when loading or storing unaligned data, the byte alignment order of the data in word units,
By changing the start address of the desired data and the storage unit of the cache storage device, the unaligned data is loaded and stored in one transfer, and the cache storage device holds even and odd addresses, and byte unit And a structure for performing data transfer with the register device by one-time transfer by simultaneously accessing the cache storage device and selecting desired data in byte units. A non-aligned data transfer mechanism in a cache storage device. 2. The microprocessor is used in a microprocessor adopting an architecture in which a word length is a power of 2 times N (N is a positive integer) times a byte, which is a unit for adding an address designating a data area. In a cache memory device that holds a copy of the main memory in units of lines that is M times the size of M (M is a positive integer), a copy of the main memory at the address where the lower (M + N + 1) th bit is an odd number Hold, and at the time of a cache hit, start with the byte indicated by the lower (M + N) bits of the input address in the line hit
Holds a line-by-line copy of the odd-numbered cache memory that outputs a word-length byte string and the main memory at the address where the lower (M + N + 1) th bit becomes an even number. 1 starting from the byte indicated by the lower (M + N) bits of the address
An even cache memory that outputs a byte string for a word length, and a byte string output from the odd cache memory and a byte string output from the even cache memory are input, and each byte unit is based on a byte selection signal. And a data selector that selects one of the outputs to generate a word to be output to the register device and a reference address is given based on the value of the lower (M + N + 1) bits of the reference address for the cache during the load operation. Single cache operation by the odd cache memory, single cache operation by the even cache memory with a reference address, cache operation by the odd cache memory with a reference address, and a reference address or (M + N + 1) th bit in the reference address Add 1 to Controls the parallel operation of the caching operation by the even cache memory of giving reference address, unaligned data transfer unit in the cache memory, characterized in that it comprises a cache selector for outputting the byte selection signal. 3. The microprocessor is used in a microprocessor adopting an architecture in which a word length is a power of 2 times N of a byte (N is a positive integer), which is a unit for adding an address designating a data area, and 2 in a word unit is used. In a cache memory device that holds a copy of the main memory in units of lines that is M times the size of M (M is a positive integer), a copy of the main memory at the address where the lower (M + N + 1) th bit is an odd number When a cache hit occurs, after the input data is selectively set in the write cell in byte units from the register device according to the value of the lower (M + N) bits of the input address and the byte select signal, the data in the hit line is Odd cache memory that selectively writes to the corresponding byte position, and main memory at addresses where the lower (M + N + 1) th bit is even The copy is held in line units, and at the time of a cache hit, after input data is selectively set in the write cell from the register device in byte units according to the value of the lower (M + N) bits of the input address and the byte selection signal, By the even cache memory that selectively writes to the corresponding byte position in the hit line, and by the odd cache memory that gives the reference address based on the value of the lower (M + N + 1) bits of the reference address for the cache during the store operation. Single caching operation, single caching operation by the even cache memory given a reference address, caching operation by the odd cache memory given a reference address, and 1 is added to the (M + N + 1) th bit of the reference address or reference address reference Controls the parallel operation of the caching operation by the even cache memory of giving dresses, unaligned data transfer unit in the cache memory, characterized in that it comprises a cache selector for outputting the byte selection signal. 4. In a processor having means for transferring data required for operation from a cache storage device to a register device and performing calculation, a basic data length (word length) of data to be transferred specifies a data area. When the length is longer than the unit (byte) to add the address to be transferred and the start address of the data to be transferred does not become an integer multiple of the word length, when loading or storing unaligned data, the byte alignment order of the data in word units,
Data that loads and stores unaligned data in a single transfer by changing it according to the start address of the desired data and the storage unit of the cache storage device, and also that spans the boundaries of the data storage unit of the storage device. When a transfer is required, a cache storage device that enables a plurality of accesses at the same time and a means for selecting these outputs in byte units are provided. By simultaneously accessing the cache storage device, the register device can be transferred in one transfer. A non-aligned data transfer mechanism in a cache storage device, which is configured to transfer data to and from. 5. A microprocessor is used in a microprocessor adopting an architecture in which a word length is a power of 2 times N (N is a positive integer) which is a unit for adding an address designating a data area. In a cache storage device that holds a copy of the main memory in line units, which is a size that is M times (where M is a positive integer) times, a data memory array having a dual port structure that holds a copy of the main memory in line units. , The cache can be searched for two reference addresses at the same time, and at the time of each cache hit, the lower order of the reference address (M +
N) A cache memory that outputs a byte string for one word length starting with the byte indicated by the bit, and two byte strings output from the cache memory are input, and each byte unit is based on the byte selection signal. , A data selector which selects one of the byte strings to generate a word to be output to the register device, and the reference address itself is stored in the cache memory based on the value of the lower (M + N) bits of the reference address for the cache. The given independent caching operation, the reference address itself and (M + N
A cache selector that outputs a byte selection signal while controlling two parallel reference addresses, that is, a reference address obtained by adding 1 to the +1) th bit, to the cache memory and outputting the byte selection signal. A non-aligned data transfer mechanism in a cache storage device. 6. A word length is used in a microprocessor adopting an architecture in which a byte is a power of 2 times N (N is a positive integer), which is a unit for adding an address designating a data area, and 2 in a word unit is used. In a cache storage device that holds a copy of the main memory in line units, which is a size that is M times (where M is a positive integer) times, a data memory array having a dual port structure that holds a copy of the main memory in line units. , The cache can be searched for two reference addresses at the same time, and at the time of each cache hit, the lower (M +
N) A cache memory in which input data is selectively set in byte units from a register device according to a bit value and a byte selection signal and then selectively written to a corresponding byte position in a hit line. , A single caching operation in which the reference address itself is given to the cache memory based on the value of the lower (M + N) bits of the reference address for the cache, the reference address itself and (M + N) in the reference address
A cache selector that outputs a byte selection signal while controlling two parallel reference addresses, that is, a reference address obtained by adding 1 to the +1) th bit, to the cache memory and outputting the byte selection signal. A non-aligned data transfer mechanism in a cache storage device. 7. A byte rotator for rotating and shifting the byte string held in the register device according to the value of the reference address, and rearranging the byte arrangement order in the register device in the order of address. An unaligned data transfer mechanism in a cache storage device according to claim 1, 2, 3, 4, 5 or 6.