JP2574019B2 - DMA transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a method for directly transferring data between memories by a DMA controller in a processor system, a DMA transfer method that does not require a memory for editing and does not lower the processing performance of the CPU. Address conversion that outputs the same index address for each data block as the number of transfer words of each data block output by the DMA controller initialized and activated by the CPU under the control of the DMA controller for the purpose of realization A circuit, an index memory for storing the start address of each data block in the order of transfer, and outputting the start address of each data block corresponding to the index address as an upper address, and counting by the number of transfer words of each data block. Output the lower address of the data to be transferred next. And a data memory for storing data of each data block and outputting corresponding data in response to the upper address and the lower address under the control of the DMA controller.

[Industrial applications]

The present invention relates to a system in which data is directly transferred between memories by a direct memory access (hereinafter, referred to as DMA) controller in a processor system.

As the amount of information to be processed increases, the processing speed of the processor (hereinafter referred to as the CPU) decreases. Is needed.

[Conventional technology]

In general, in the DMA transfer method, data transfer is performed between memories by giving a start address of a data transfer source memory, a start address of a data transfer destination, and the number of data to be transferred to a processor program in advance. As a method of transferring data to data blocks in different spaces by DMA, there are the following methods.

(1) Editing by moving from the memory space consisting of the data blocks A, B, and C to the memory space,
U controls the DMA controller to combine the data blocks A to C from the memory space and perform DMA transfer as one piece of information (see FIG. 7).

(2) A method in which the CPU individually controls the DMA controller for data blocks A, B, and C in the memory space to perform DMA transfer (see FIG. 8).

[Problems to be solved by the invention]

The conventional method shown in FIG. 7 requires a separate memory space for editing, and the conventional method shown in FIG. 8 prevents underflow when the transfer speed from the output port is high. CPU is DMA for each data block
The transfer end is detected as soon as possible, and the DMA of the next data block is
Since the transfer settings must be made, there is a problem that the amount of information processed by the CPU is increased and the processing capability is reduced.

Therefore, an object of the present invention is to realize a DMA transfer method that does not require a memory for editing and does not lower the processing performance of a CPU.

[Means for solving the problem]

FIG. 1 shows a DM according to the present invention for achieving the above object.
In the present invention, the same index address for each data block as the number of transfer words of each data block output by the DMA controller 1 initialized and activated by the CPU is assigned to the data block. DMA
Address conversion circuit 2 that outputs under the control of controller 1
And an index memory 3 for storing the top address of each data block in the transfer order and outputting the top address of each data block corresponding to the index address as an upper address; A counter circuit 4 for counting the number of words to be transferred and outputting the lower address of data to be transferred next; storing data of each data block and storing corresponding data in response to the upper address and the lower address; A data memory 5 for outputting under the control of the DMA controller 1.

[Action]

Regarding the operation of the configuration of the present invention shown in FIG. 1, data blocks A, B, and C having different memory spaces are rearranged to A, C, and B.
FIGS. 2 and 3 show an example of an operation when a DMA transfer is performed.
This will be described with reference to the drawings.

First, the start address AA, AB, A of each data block A, B, C
Write C to the index memory 3 in the order of transfer, and
For the MA controller 1, the total number of words of transfer information NA +
NC + NB and the index address AI in the index memory 3 are set and activated.

The DMA controller 1 outputs a head address AI storing an index address for transferring the first word. The address conversion circuit 2 gives the same address AI to the index memory 3 by the number of words of the data block A according to the table shown in FIG. 3 and resets the counter circuit 4 at the same time. The index memory 3 gives the head address AA stored in the address AI to the data memory 5 as an upper address.

The data memory 5 sequentially outputs each word of the data block A based on the upper address AA and the lower addresses corresponding to the number of words counted by the counter circuit 4 under the control of the DMA controller 1.

In this way, as shown in FIG. 3, the DMA controller 1 keeps incrementing and outputting the address until the transfer of the total number of words NA + NB + NC of the transfer information is completed.

For example, the transfer of the n-th (NA <n <(NA + NC)) word is
The upper address AB and the lower address (n-NA) are given to the data memory 5, and the (n-NA) word of the data block B is output and transferred.

In this way, it is possible to store the head address of each data block in a predetermined memory in the transfer order prior to the data transfer, and then perform DMA transfer of all the data blocks in the specified order only by setting and starting the DMA controller once. It becomes possible.

〔Example〕

FIG. 4 is a block diagram showing one embodiment of the DMA transfer system according to the present invention. In this embodiment, fixed data blocks stored on a table ROM are combined, and header data as arbitrary data is added. According to the present invention, a function of transferring one packet information from an output port to another device is realized. Therefore, between the CPU 10 and the DMA controller 1, an I / O
An O access control circuit 11 is provided, and the selector 12 selects data output from the data memory 5 and header data output from the index memory 3 by a select signal from the address conversion circuit 2 to control the DMA controller 1. Output is provided from the output port 13 below. The index memory 3 is constituted by a dual port RAM in order to separate the CPU bus and the DMA bus, and the data memory 5 has the same word length N as one embodiment as shown in FIG. 5 (2). It has a table ROM configuration in which fixed data blocks are stored. The address conversion circuit 2 includes the function of the counter circuit 4 in FIG. 1, and is constituted by a ROM circuit because the header data length of packet information and the length of each data block are constant. Note that a is a CPU address, b is CPU data, and c is
CPU control signal, d is DMA address, e is DMA control signal, f
Denotes an output address from the address conversion circuit 2, g denotes an upper address to the data memory 5, h denotes a lower address to the data memory 5, and s denotes a select signal to the selector 12.

Hereinafter, the operation of the embodiment shown in FIG. 4 will be described with reference to FIGS.
This will be described with reference to the drawings.

When transferring the packet information shown in FIG.
U10 writes the data of FIG. 5 (1) into the index memory 3 by the CPU address a, the data b, and the control signal c, and further sends the data to the DMA controller 1 via the I / O access control circuit 11 in FIG. 3) Total word length of packet information
Start by setting NH + 3N and the index address AI at the head of the data in FIG. 5 (1). The DMA controller 1 outputs the DMA address d in the order of AI, AI + 1, AI + 2,... Every transfer cycle. In response, the address conversion circuit 2
Outputs an index address f given to the index memory 3, a lower address h given to the data memory 5, and a select signal s according to the address conversion table shown in FIG. For the header data, the index address f is incremented by one for each word.

The select signal s connects the index memory 3 and the output port 13 during the transfer of the header data, and the data memory 5 and the output port during the subsequent transfer of the data block.
The selector circuit 12 is controlled so that the selector circuit 13 is connected to the selector circuit 13.

In addition, during the transfer of the data block, the address data output from the index memory 3, that is, the position AA, AB, AC, AD of the transfer block in the data memory 5 shown in FIG. The position of the transfer word in the transfer block (N word) is specified by the lower address h output from the address conversion circuit 2, and is output from the data memory 5 for each word to be transferred.

Therefore, the data in the data memory 5 shown in FIG. 5 (2) is read out in the order of the index addresses shown in FIG. 5 (1), and the header data + each N
The word data blocks A, D, and B will be transferred from the output port 13.

The read / write control of the index memory 3, the data memory 5, and the output port 13 in the above operation is performed by the DMA control signal e output from the DMA controller 1.

In the above description, the DMA address d from the DMA controller 1 to the address conversion circuit 2 is particularly the address AI if the head address AI of the index memory 3 is “0”.
It is needless to say that the address increment for the total word length may be performed without the need for the address.

〔The invention's effect〕

According to the present invention, prior to data transfer, each head address (index) and the number of words of a data block having a different memory space to be transferred to an address conversion circuit, an index memory, and a data memory are stored in advance, Since all data blocks are DMA-transferred in the specified order only by initial setting / starting of the controller, the CPU only needs to set / start the DMA controller once and transfer all data blocks to the output port in the specified order.
It becomes possible to transfer. Therefore, without having to edit a large amount of data and setting and starting up the DMA controller many times, the processing capacity of the CPU is improved, and the data memory is separated from the memory space of the CPU and managed only by the index. Therefore, there is an effect that memory resources can be saved.

In addition, since the lower address is output from the counter circuit, the data memory can be completely separated from the CPU address bus, thereby separating a large amount of data area from the CPU memory space and making the memory space effective. Can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of a DMA transfer system according to the present invention. FIGS. 2 and 3 are explanatory diagrams of the operation of the present invention shown in FIG. 1. FIG. FIGS. 5 and 6 are explanatory diagrams of the operation of the embodiment of FIG. 4, and FIGS. 7 and 8 are explanatory diagrams of the operation of the conventional system. . In FIG. 1, 1 ... DMA controller, 2 ... address conversion circuit, 3 ... index memory, 4 ... counter circuit, 5 ... data memory. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-851 (JP, A) JP-A-60-247764 (JP, A)

Claims (1)

(57) [Claims] 1. The same index address for each data block as the number of transfer words of each data block output by the DMA controller (1) initialized and activated by the CPU under the control of the DMA controller (1). An address conversion circuit (2) for outputting, an index memory (3) for storing the head address of each data block in the transfer order, and outputting the head address of each data block corresponding to the index address as an upper address; A counter circuit (4) controlled by an address conversion circuit (2) for counting the number of words to be transferred of each data block and outputting the lower address of data to be transferred next
And storing the data of each data block and storing the corresponding data in response to the upper address and the lower address in the DMA.
A data memory (5) for outputting data under the control of a controller (1).