EP0275176A3 - Data transferring buffer circuits for data exchange - Google Patents

Data transferring buffer circuits for data exchange Download PDF

Info

Publication number
EP0275176A3
EP0275176A3 EP19880300216 EP88300216A EP0275176A3 EP 0275176 A3 EP0275176 A3 EP 0275176A3 EP 19880300216 EP19880300216 EP 19880300216 EP 88300216 A EP88300216 A EP 88300216A EP 0275176 A3 EP0275176 A3 EP 0275176A3
Authority
EP
European Patent Office
Prior art keywords
data
buffer
buffer circuits
generating circuit
signal generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19880300216
Other languages
German (de)
French (fr)
Other versions
EP0275176A2 (en
EP0275176B1 (en
Inventor
Fumiyasu Hirose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62004523A external-priority patent/JPH07104828B2/en
Priority claimed from JP62004522A external-priority patent/JPS63172362A/en
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0275176A2 publication Critical patent/EP0275176A2/en
Publication of EP0275176A3 publication Critical patent/EP0275176A3/en
Application granted granted Critical
Publication of EP0275176B1 publication Critical patent/EP0275176B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Computer And Data Communications (AREA)

Abstract

Data transferring buffer circuits for data exchange include a plurality of buffers corresponding to a plurality of data sources for receiving and storing independently data sent from the plurality of data sources, and a buffer limit signal generating circuit for delivering a buffer limit signal when the amount of data stored in the buffer reaches a predetermined limit. The buffer circuits also include a data read signal generating circuit for selecting one of the buffers and generating a data reading signal for the selected buffer based on the remaining amount of data and information concerning a vacancy at a buffer to which data is to be supplied, and a selected data delivery circuit for adopting data selected by the data read signal generating circuit and delivering the adopted data.
EP88300216A 1987-01-12 1988-01-12 Data transferring buffer circuits for data exchange Expired - Lifetime EP0275176B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP62004523A JPH07104828B2 (en) 1987-01-12 1987-01-12 Data transfer buffer circuit
JP4523/87 1987-01-12
JP62004522A JPS63172362A (en) 1987-01-12 1987-01-12 Inter-processor communication system
JP4522/87 1987-01-12

Publications (3)

Publication Number Publication Date
EP0275176A2 EP0275176A2 (en) 1988-07-20
EP0275176A3 true EP0275176A3 (en) 1991-05-08
EP0275176B1 EP0275176B1 (en) 1994-05-18

Family

ID=26338320

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88300216A Expired - Lifetime EP0275176B1 (en) 1987-01-12 1988-01-12 Data transferring buffer circuits for data exchange

Country Status (4)

Country Link
US (1) US5740468A (en)
EP (1) EP0275176B1 (en)
KR (1) KR910002325B1 (en)
DE (1) DE3889550T2 (en)

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US5983025A (en) * 1995-06-07 1999-11-09 International Business Machines Corporation Computer system buffers for providing concurrency and avoid deadlock conditions between CPU accesses, local bus accesses, and memory accesses
US6240065B1 (en) * 1996-01-08 2001-05-29 Galileo Technologies Ltd. Bit clearing mechanism for an empty list
IL116707A (en) * 1996-01-08 2000-01-31 Galileo Technology Ltd Method and apparatus for managing packet memory
IL116988A (en) 1996-01-31 1999-12-31 Galileo Technology Ltd Bus protocol
IL116989A (en) 1996-01-31 1999-10-28 Galileo Technology Ltd Switching ethernet controller
JP3253547B2 (en) * 1996-03-28 2002-02-04 株式会社沖データ Data transfer system
US6212567B1 (en) * 1996-09-12 2001-04-03 Compaq Computer Corporation Method and apparatus for performing raw cell status report frequency mitigation on receive in a network node
US5987496A (en) * 1996-12-03 1999-11-16 Mitsubishi Electric Information Technology Center America, Inc. (Ita) Real-time channel-based reflective memory
DE19717548A1 (en) * 1997-04-25 1998-11-05 Philips Patentverwaltung Transmission system
US6094696A (en) * 1997-05-07 2000-07-25 Advanced Micro Devices, Inc. Virtual serial data transfer mechanism
DE19830625B4 (en) * 1998-07-09 2008-04-03 Robert Bosch Gmbh Digital interface unit
CA2282882C (en) * 1998-09-22 2005-11-01 Kabushiki Kaisha Toshiba Serial transmission path switching system
US6973559B1 (en) 1999-09-29 2005-12-06 Silicon Graphics, Inc. Scalable hypercube multiprocessor network for massive parallel processing
US6898638B2 (en) * 2001-01-11 2005-05-24 International Business Machines Corporation Method and apparatus for grouping data for transfer according to recipient buffer size
US7711844B2 (en) * 2002-08-15 2010-05-04 Washington University Of St. Louis TCP-splitter: reliable packet monitoring methods and apparatus for high speed networks
JP2004318540A (en) * 2003-04-17 2004-11-11 Hitachi Ltd Performance information monitoring apparatus, method and program
US7254389B2 (en) * 2003-08-25 2007-08-07 Cohen Alain J Wireless link simulation with generic caching
JP4376040B2 (en) * 2003-11-27 2009-12-02 株式会社日立製作所 Apparatus and method for performing information processing using a plurality of processors
US9166989B2 (en) * 2006-12-28 2015-10-20 Hewlett-Packard Development Company, L.P. Storing log data efficiently while supporting querying
US7761084B2 (en) * 2007-02-21 2010-07-20 Bridgewater Systems Corp. Systems and methods for session records correlation
US7945745B2 (en) 2007-09-17 2011-05-17 General Electric Company Methods and systems for exchanging data

Citations (1)

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US4325120A (en) * 1978-12-21 1982-04-13 Intel Corporation Data processing system

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US3936600A (en) * 1974-08-21 1976-02-03 World Computer Corporation Keyboard-printer terminal interface for data processing
US4114750A (en) * 1975-08-06 1978-09-19 Hydra Corporation Printer system having local control for dynamically alterable printing
US4169991A (en) * 1975-08-20 1979-10-02 International Business Machines Corporation Variable print speed control
US4396307A (en) * 1978-04-07 1983-08-02 Qume Corporation Method and apparatus for automatically feeding cut sheets to a character printer
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Patent Citations (1)

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US4325120A (en) * 1978-12-21 1982-04-13 Intel Corporation Data processing system

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN. vol. 33, no. 5, March 1985, HASBROUCK HEIGHTS, N pages 153 - 159; B.Greer: "Scientific computer simulates VLSI circuit in record time" *
IEE PROCEEDINGS D. CONTROL THEORY & APPLICATIONS. vol. 132, no. 2, March 1985, STEVENAGE GB pages 102 - 107; M.Soegaard-Knudsen: "Hierarchical specification and switch-level simulation of digital circuits" *
IEEE DESIGN & TEST OF COMPUTERS. vol. 2, no. 5, October 1985, LOS ALAMITOS US pages 61 - 73; N.Koike: "HAL : a high-speed logic simulation machine" *
The 13th Annual International Symposium on Computer Architecture 2 June 1986, Tokyo Japan pages 434 - 442; M.Dubois: "Memory access buffering in multiprocessors" *

Also Published As

Publication number Publication date
US5740468A (en) 1998-04-14
DE3889550D1 (en) 1994-06-23
EP0275176A2 (en) 1988-07-20
DE3889550T2 (en) 1994-09-01
KR880009498A (en) 1988-09-15
KR910002325B1 (en) 1991-04-11
EP0275176B1 (en) 1994-05-18

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