JPH0259961A - Information processor - Google Patents

Abstract

PURPOSE:To perform a vector operation at high speed by executing a vector instruction without executing another vector instruction having mask control for the part of an array element string in which the same vector master data is continued longest. CONSTITUTION:The number of array elements in the part of the array element string in which the same vector mask data continue longest is stored in a maximum element number holding register 14, and the element number of the leading array element in the part is stored in an inverted element number representative register 16. Further, while the vector instruction, for which it is unnecessary to refer to vector mask data, is executed for the part indicated by the contents of the maximum element number holding register 14 and the inverted element number representative register 16, the vector instruction having the mask control is executed for the other parts. Consequently, a deciding operation for the vector mask data is not to be executed for the part having the maximum number of array elements out of the part in which the same vector mask data is continued. Thus, an overhead caused by the deciding operation can be minimized, and the processing speed of the vector operation can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device capable of performing vector operations with a mask function.

[Conventional technology]

Array data is often handled in scientific and technical calculations, and operations on array data often involve repeating the same operation on each array element. In order to perform operations on such array data at high speed, information processing apparatuses that can use so-called vector instructions have been put into practical use.

By the way, when performing operations on array data, there are cases in which operations can be performed on all array elements unconditionally;
An example of the latter example is a program written in the FORTRAN language as shown in FIG. 3, in which arithmetic operations may only be performed on array elements that satisfy specific conditions.

The program shown in FIG. 3 uses array data A (i), B (i), C (
i), D (i) and another numerical data E, if the first array element of array AO (i = 1 to N) is 1 zero" or more, each of array C and array i Calculate the product of the ith array element, set the result as the ith array element of array B, and if the ith array element of array A is a negative value, fix the value to the ith array element of array B. This indicates that E should be inserted.

By the way, when performing a conditional operation on array data as shown in the program of FIG. 3, vector instructions with mask control are generally used to execute the operation at high speed. FIG. 4 is a flowchart showing the execution procedure when executing a program using vector instructions with mask control. First, a mask generation instruction is executed, and the vector corresponding to statement number 20 of the program in FIG. Mask data is obtained. That is, when Ai≧00, the content of the corresponding vector mask data MASKi is set to “1”, and otherwise, it is set to “0”. This vector mask data MASKi is generally stored on the main storage device or in a register file or the like provided exclusively as a vector mask register.

Next, a vector multiplication instruction with mask control is executed on the vector mask data M generated by the mask generation instruction according to SKi. By executing this command,
Multiplication is performed only on array element i corresponding to vector mask data MASKi=1, and the multiplication result is stored in array B.

When this is completed, a vector transfer command with mask control is further executed, and numerical data E is transferred only with respect to array element i corresponding to vector mask data MASKi=O. In this example, the vector mask data MASKi corresponding to the array element to be operated on is set to "1", and the vector mask data MASKi corresponding to the array element to be transferred is set to "0". The data MASKi may be set to 10'', and the vector mask data MASKi corresponding to the array element to be transferred may be set to 1''.
1" at which the operation is enabled can be specified by a software instruction code or the like.

[Problem to be solved by the invention]

As mentioned above, by using vector instructions with mask control, it is possible to execute vector operations at high speed on an information processing device even when executing an array processing program that includes a conditional statement in a loop. It has become possible to increase the ratio.

However, in the conventional example described above, whether the corresponding vector mask data for all array elements is "1" or
Since it is determined whether it is "0" and it is decided whether or not to perform vector calculation based on the determination result, the overhead of the determination operation is large and the effect of vector calculation cannot be fully demonstrated. The problem is that there are cases.

An object of the present invention is to speed up processing by reducing overheavy caused by vector mask data determination operations.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a vector instruction that performs an operation on array data, a vector mask generation instruction that generates vector mask data for suppressing operations on a specific array element depending on a condition, and a vector mask generation instruction that generates vector mask data based on the vector mask data. In an information processing device capable of executing a vector instruction with mask control that performs an operation on an array element other than the array element whose operation is suppressed, A maximum element number holding register that stores a value indicating the number of array elements, and an inverted element number representative that stores the element number of the first array element in the part where the value indicating the number of array elements is stored in the maximum element number holding register. and execute the vector instruction for the part indicated by the number of array elements stored in the maximum element number holding register in the array element string and the element number stored in the inverted element number representative register. The vector command with mask control is executed for other parts.

[For production]

The maximum number of elements holding register stores the number of array elements in the longest consecutive part of the same vector mask data in the array element sequence, and the inverted element number representative register stores the element number of the first array element in that part. be done. Then, for the portion indicated by the contents of the maximum element number holding register and the inverted element number representative register, a vector instruction that does not require reference to vector mask data is executed, and for other portions, a vector instruction with mask control is executed. .

Therefore, the vector mask data determination operation will not be performed for the part with the largest number of array elements among the consecutive parts of the same vector mask data.
The overhead due to the vector mask data determination operation can be reduced, and the processing speed of vector calculations can be improved.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a mask generation operand register 1.2, a comparison circuit 3.13, a mask data register 4, an instruction word register 5, an instruction decoder 6, and an operation Control unit 7 and element number register 8
, inverted element number register 9, and element number holding register 1
0, an element number history register 11, an element number comparison register 12, a maximum element number holding register 14, an exclusive OR circuit 15, an inverted element number representative register 16, and an upper control unit 17. .

Next, the operation of this embodiment will be explained by taking as an example the case where the program shown in FIG. 3 is executed.

First, as shown in the flowchart of FIG. 2, a mask generation instruction is sent to the instruction word register 5 (step 31).
), vector mask data is generated. When generating vector mask data, mask generation operand register 1
. In this example, one of mask generation operand registers 1 and 2 (for example, mask generation operand register 1) contains array data A(1), and the other (for example, mask generation operand register 2) contains numerical data. “0” is set.

When the mask generation instruction is set in the instruction word register 5, the instruction decoder 6 decodes it and sends a magnitude comparison instruction to the comparison circuit 3. When the comparison circuit 3 receives a magnitude comparison instruction, it compares the array data A (i) set in the mask generation operand register 1.2 with the numerical data "0", and the comparison result is A.
(i) If ≧0, output “1”; if A (+) < O, output “0”. In other words, the output signal of comparator circuit 3 is the array that is stored in operand register 1 for mask generation. It becomes vector mask data corresponding to elements.

The vector mask data output from the comparator circuit 3 is added to the mask data register 4 and also to the exclusive OR circuit 15. When vector mask data is added, the mask data register 4 sets it to the least significant bit and shifts the previously set vector mask data bit by bit to the upper bit. Every time vector mask data for one word is stored in the mask data register 4, the vector mask data for one word is transferred from the mask data register 4 to a main storage device (not shown) and stored therein.

The element number register 8 is a register that holds the element number of the array element currently being processed during vector data calculation or vector mask data generation, and its output is added to the inverted element number register 9. The inversion element number register 9 compares the vector mask data set in the least significant bit of the mask data register 4 with the comparison circuit 3.
The output of the element number register 8 is held only when the output signal of the exclusive OR circuit 15 which calculates the exclusive OR with the vector mask data output from the element number register 8 becomes "1".

Here, the output signal of the exclusive OR circuit 15 becomes "1" because the vector mask data corresponding to the array element currently set in the mask generation operand register l is the vector mask data corresponding to the immediately preceding array element. Therefore, the element number of the newest array element among the array elements whose corresponding vector mask data differs from the vector mask data of the immediately preceding array element is stored in the inverted element number register 9. is stored.

The contents of the element number holding register 10 are counted up each time processing for a new array element is started, and is reset when the output signal of the exclusive OR circuit 15 becomes "1". Further, the contents of the element number holding register IO immediately before being reset are stored in the element number history register 11. Therefore, the element count history register 11 stores a value indicating how many consecutive array elements have the same vector mask data.

The contents of the number of elements history register 11 are the number of elements comparison register 1.
It is compared with the contents of No. 2 in the comparator circuit 13.

Note that the initial value of the element number comparison register 12 is "0". Comparison circuit 13 is element number washing history register 1
1 and the contents of the element number comparison register 12, the larger value is stored in the element number comparison register 12 and the maximum element number holding register 14. Further, when the contents of the element number employment history register 11 are larger than the contents of the element number comparison register 12, the comparison circuit 13 applies a set signal to the inverted element number representative register 16 to store the contents of the inverted element number register 9. Therefore, the maximum number of elements holding register 14 stores a value indicating the number of array elements in the longest consecutive part of the same vector mask data in the array element sequence, and the inverted element number representative register 16 stores the value indicating the number of array elements in the longest continuous part of the same vector mask data in the array element string. The number is stored.

When the execution of the mask generation instruction is completed, the upper control unit 17 stores the value indicating the number of array elements stored in the maximum number of elements holding register 14 (assuming that m is stored) and the value stored in the inverted element number representative register 16. The first element number (
Suppose that n is stored.

However, n-1) is read, and it is checked whether the vector mask data corresponding to the first element number n stored in the main storage device is "1" or "O".

Next, as shown in FIG.
,DΦVector multiplication instruction with mask control targeting the 1st to (n-1)th elements, that is, from the 1st element to the one before the element with the element number stored in the inverted element number representative register 16. A vector multiplication instruction with mask control that targets elements up to is set in the instruction word register 5 (step 32). As a result, the arithmetic control unit 7 multiplies the elements whose corresponding vector mask data is "l" among the first to (n-1)th elements of the arrays C and D. and the multiplication result is stored in array B.

Next, as shown in FIG. 2, the higher-level control unit 17 sends a mask-controlled vector transfer instruction targeting the first to (n-1)th elements to the instruction register 5 (
Step S3), as a result, in the calculation control section 7,
Numerical data E is stored in the elements whose corresponding vector mask data is "0" among the first to (n-1)th elements of array B.

When the execution of the vector transfer command with mask control for the 1st to (n-1)th elements is completed, the upper control unit 17 has already checked that the vector mask data corresponding to element number n is "1". In some cases, the nth to (04m)th elements of arrays C and D, that is, the same vector mask data, are the longest (a vector multiplication instruction without mask control that targets consecutive partially corresponding elements is stored in the instruction word register). 5, and if it is “0”, start from the nth (04m
) A vector transfer instruction without mask control is set in the instruction register 5 (step 34). When a vector multiplication instruction is set in the instruction word register 5, the arithmetic control unit 7
Corresponding elements of the (04m)th to (04m)th elements are multiplied, and the multiplication results are stored in the corresponding elements of the array B. Furthermore, when a vector transfer instruction is set in the instruction word register 5, the arithmetic control unit 7
Numerical data E is stored from the nth element to the (n8m)th element.

When the execution of the vector multiplication instruction or vector transfer instruction without vector control is completed, the upper control unit 17 transfers the array C,
A vector multiplication instruction with mask control that targets the (n+m+1)th to the last element of D is sent to the instruction word register 5.
(step S5), so that the corresponding vector mask data from the (n+m+1)th element to the last element of arrays C and D becomes "1" in the arithmetic control unit 7. Multiplying the elements is performed, and the multiplication result is stored in the corresponding element of array B.

Next, the upper control unit 17 stores a vector transfer command with mask control for the (n + m + 1)th element to the last element into the command register 5 (step S
6), As a result, in the arithmetic control unit 7, (
Numerical data E is stored in elements whose corresponding vector mask data is "1" from the (n+m+1)th element to the last element.

Therefore, the portion indicated by the contents of the maximum element number holding register 14 and the inverted element number representative register 16 in the array element (the above example is the portion from the n-th element to the n+m-th element, and the same vector A vector instruction without mask control is executed for the part where the mask data is longest continuous, and a vector instruction with mask control is executed for the other parts.

(Effects of the Invention) As explained above, the present invention executes a vector instruction without executing a hector instruction with mask control for the longest continuous portion of the same vector mask data in an array element sequence. Since there is no need to check the vector mask data for that part, it has the effect of speeding up vector calculations.In particular, "1" and "0" in the vector mask data
'' is extremely different and the same vector mask data continues for a long time, the effect is very large.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a flowchart showing the execution procedure of a FORTRAN program in the embodiment, Fig. 3 is a diagram showing an example of a FORTRAN program, and Fig. 4 is a conventional example. 2 is a flowchart showing the execution procedure of a non-FORTRAN program. In the figure, l, 2...operand register for mask generation, 3.13...comparison circuit, 4...mask data register, 5...instruction word register, 6...instruction decoder, 7 ... Arithmetic control unit, 8... Element number register, 9... Inverted element number register, 10... Element number holding register, 11... Element number layer layer register, 12...
- Element number comparison register, 14... Maximum element number holding register, 15... Exclusive OR circuit, 16... Inverted element number representative register, 17... Upper control unit.

Claims (1)

[Scope of Claims] A vector instruction that performs an operation on array data, a vector mask generation instruction that generates vector mask data for suppressing an operation on a specific array element depending on a condition, and a vector mask generation instruction that generates vector mask data for suppressing an operation on a specific array element based on a condition. In an information processing device capable of executing a vector instruction with mask control that performs an operation on an array element other than the array element in which The maximum element number holding register stores the value indicating the number of array elements, and the inverted element number representative register stores the element number of the first array element in the part where the value indicating the number of array elements is stored in the maximum element number holding register. The vector instruction is executed for the part indicated by the number of array elements stored in the maximum number of elements holding register in the array element string and the element number stored in the inverted element number representative register, and the other An information processing apparatus characterized in that the vector instruction with mask control is executed for the part shown in FIG.