CN103746796A - Coprocessor for realizing intelligent card SM4 password algorithm - Google Patents

Abstract

The invention discloses a coprocessor for realizing an intelligent card SM4 password algorithm. The coprocessor comprises an interface module, a finite state machine module, a register file module and a logic function module, wherein the interface module is used for realizing the data interaction with an external control module; the finite state machine module is used for controlling the register file module and the logic function module and returning an operation state signal back to the interface module; the register file module is used for performing reading/writing operation on a corresponding register, sending data to the logic function module for processing and getting back a corresponding result; the logic function module is used for performing secret key-expanded wheel operation and encryption/decryption wheel operation by turns on the data sent from the register file module till 32 wheels are finished as well as returning the operation result each time back to the register file module. By implementing the technical scheme, the size of the coprocessor is small and the application flexibility is high.

Description

A kind of coprocessor of realizing smart card SM4 cryptographic algorithm

Technical field

The present invention relates to communication field, relate in particular to a kind of coprocessor of realizing smart card SM4 cryptographic algorithm.

Background technology

Along with improving constantly that scientific and technological progress and people require information security, smart card is used widely in daily surviving.In fields such as traffic, finance, education, all can see the figure of smart card.

SM4 algorithm is a kind of block cipher of being announced in January, 2006 by national commercial cipher management board, is mainly used in the communication of WLAN (wireless local area network), is the commercial cipher algorithm that first official announces.Commercial cipher management board of country ratifies it for commercial cipher industry standard, called after SM4 algorithm.SM4 algorithm adopts nonequilibrium Feistel structure, has the ability of stronger opposing differential attack, and security intensity reaches international block cipher standard.

The plaintext of SM4 algorithm and key length are 128 bits, and encryption round number is 32.In first round operation, be directly the data of input to be taken turns to computing.In wheel computing below, SM4 algorithm is taken turns computing to the output data of last round of function.Take turns after computing having carried out 32, data are carried out exporting after order inversion.Wherein every round key of using of taking turns is obtained the cipher key spreading of input by key schedule, expansion algorithm and cryptographic algorithm are similar, often through a next round computing, just export a round key, altogether need to generate 32 round key, be used in successively in different encryption round computings.The deciphering conversion of SM4 algorithm is identical with enciphering transformation structure, and different is only the use order of round key.

Yet, at present, conventionally for expansion algorithm and cryptographic algorithm, two cover computing modules are set respectively, therefore, make the area of harmonizing processor chip larger, the flexibility of application is lower.

Summary of the invention

The technical problem to be solved in the present invention is, the low defect of flexibility of, application large for the above-mentioned harmonizing processor chip area of prior art, provides a kind of coprocessor of realizing smart card SM4 cryptographic algorithm, and area is little and application flexibility is high.

The technical solution adopted for the present invention to solve the technical problems is: construct a kind of coprocessor of realizing smart card SM4 cryptographic algorithm, comprising: interface module, finite state machine module, register file module and logic function module, wherein,

Described interface module is carried out data interaction for realizing with outside control module;

Described finite state machine module is used for according to the enciphering/deciphering order of described interface module, described register file module and described logic function module being controlled, and returns to operating state signal to described interface module;

Described register file module is used for, according to the read/write command of described interface module, corresponding registers is carried out to read/write operation, and under the control of described finite state machine module, data is delivered to described logic function module and process and fetch corresponding result;

Described logic function module is under the control of described finite state machine module, the data that described register file module is sent are carried out the wheel computing of cipher key spreading and the wheel computing of enciphering/deciphering in turn, until 32 take turns end, and to described register file module, return to the result of each computing.

In the coprocessor of realizing smart card SM4 cryptographic algorithm of the present invention, described logic function module comprises:

Constant generation module, for the wheel number of exporting according to described finite state machine module, generates the constant for cipher key spreading;

First selector, for cipher key spreading wheel s operation control signal or the enciphering/deciphering wheel s operation control signal of exporting according to described finite state machine module, selects output from the constant of described constant generation module or from the round key of described register file module;

The first XOR module, first group of bright/encrypt data, second group of bright/encrypt data, the 3rd group of bright/encrypt data for data that described first selector is exported and described register file module, exported carry out XOR;

S box computing module, carries out nonlinear operation for the data that described the first XOR module is exported;

The first linear computing module, carries out the first linear operation for enciphering/deciphering for the data that described S box computing module is exported;

The second linear operation module, carries out the second linear operation for cipher key spreading for the data that described S box computing module is exported;

The second XOR module, the 4th group of bright/encrypt data exporting for data that described the first linear computing module is exported and described register file module carries out XOR;

The 3rd XOR module, the 4th group of bright/encrypt data exporting for data that described the second linear operation module is exported and described register file module carries out XOR;

Second selector, for cipher key spreading wheel s operation control signal or the enciphering/deciphering wheel s operation control signal of exporting according to described finite state machine module, select output from the data of described the second XOR module or from the data of described the 3rd XOR module.

In the coprocessor of realizing smart card SM4 cryptographic algorithm of the present invention, described S box computing module comprises four parallel S box arithmetic elements, and each S box arithmetic element is carried out nonlinear operation to the input data of 8 bits.

In the coprocessor of realizing smart card SM4 cryptographic algorithm of the present invention, the Mathematical Modeling of described S box arithmetic element is:

S=(a*A ₁+C ₁) ^-1*A ₂+C ₂

Wherein, S is the output data of S box arithmetic element, and a is input data, C ₁, C ₂for (1,1,0,0,1,0,1,1);

${\mathrm{<figure-callout\; id="1"\; label="A"\; filenames="HDA0000459164540000011.png"\; state="\{\{state\}\}">A</figure-callout>}}_1={\mathrm{<figure-callout\; id="2"\; label="A"\; filenames="HDA0000459164540000011.png"\; state="\{\{state\}\}">A</figure-callout>}}_2=\left[\begin{array}{c}11100101\\ 11110010\\ 01111001\\ 10111100\\ 01011110\\ 00101111\\ 10010111\\ 11001011\end{array}\right].$

Implement technical scheme of the present invention, the logic function module of this coprocessor is under the control of finite state machine module, by to multiplexing key expansion function and the enciphering/deciphering function of realizing of round function, without for cipher key spreading wheel mathematical algorithm and encryption round mathematical algorithm, two cover computing modules being set, therefore, can on very little harmonizing processor chip, realize complete SM algorithm, reduced the area of harmonizing processor chip, strengthened the flexibility of application, reduced and realized cost, had a good application prospect.

Accompanying drawing explanation

Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:

Fig. 1 is the logic diagram that the present invention realizes the coprocessor embodiment mono-of smart card SM4 cryptographic algorithm;

Fig. 2 is the logic diagram of logic function module preferred embodiment in Fig. 1.

Embodiment

Fig. 1 is the logic diagram that the present invention realizes the coprocessor embodiment mono-of smart card SM4 cryptographic algorithm, this coprocessor comprises interface module 1, finite state machine module 2, register file module 3 and logic function module 4, wherein, interface module 1 is connected with register file module 3 with finite state machine module 2 respectively, finite state machine module 2 respectively with interface module 1, register file module 3 is connected with logic function module 4, register file module 3 respectively with interface module 1, finite state machine module 2 is connected with logic function module 4, logic function module 4 is connected with register file module 3 modules with finite state machine module 2 respectively.And interface module 1 is carried out data interaction for realizing with outside control module (not shown), for example, from outside control module, receive read/write command or enciphering/deciphering order, and receive data to be written or treat the data of enciphering/deciphering; The data of also reading to outside control module transmission or the data after enciphering/deciphering.Finite state machine module 2 is for according to the enciphering/deciphering order of interface module 1, register file module 3 and logic function module 4 being controlled, and returns to operating state signal to interface module 1.Register file module 3 is for carrying out read/write operation according to the read/write command of interface module 1 to corresponding registers, and under the control of finite state machine module 2, data are delivered to logic function module 4 and process and fetch corresponding result, at this, it should be noted that, when carrying out write operation, divide four groups to be stored in memory 128 Bit datas for the treatment of enciphering/deciphering that receive from interface module 1, every group of 32 Bit datas.Logic function module 4 is under the control in finite state machine module 2, the data that register file module 3 is sent are carried out the wheel computing of cipher key spreading and the wheel computing of enciphering/deciphering in turn, until 32 take turns end, and to register file module 3, return to the result of each computing.

Implement the technical scheme of the present embodiment, the logic function module 4 of this coprocessor is under the control of finite state machine module 2, by to multiplexing key expansion function and the enciphering/deciphering function of realizing of round function, without for cipher key spreading wheel mathematical algorithm and encryption round mathematical algorithm, two cover computing modules being set, therefore, can on very little harmonizing processor chip, realize complete SM algorithm, reduced the area of harmonizing processor chip, strengthened the flexibility of application, reduced and realized cost, had a good application prospect.

Fig. 2 is the logic diagram of logic function module preferred embodiment in Fig. 1, and this logic function module comprises: constant generation module 41, first selector 42, the first XOR module 43, the linear computing module 45 of S box computing module 44, first, the second linear operation module 46, the second XOR module 47, the 3rd XOR module 48 and second selector 49.Wherein, the wheel number of constant generation module 41 for exporting according to finite state machine module 2, generates the constant for cipher key spreading; Cipher key spreading wheel s operation control signal or the enciphering/deciphering wheel s operation control signal of first selector 42 for exporting according to finite state machine module 2, selects output from the constant of constant generation module 41 or from the round key of register file module 3; First group of bright/encrypt data, second group of bright/encrypt data, the 3rd group of bright/encrypt data that the first XOR module 43 is exported for data that first selector 42 is exported and register file module 3 carry out XOR; S box computing module 44 carries out nonlinear operation for the data that the first XOR module 43 is exported; The first linear computing module 45 carries out the first linear operation for enciphering/deciphering for the data that S box computing module 44 is exported; The second linear operation module 46 is carried out the second linear operation for cipher key spreading for the data that S box computing module 44 is exported; The 4th group of bright/encrypt data that the second XOR module 47 is exported for data that the first linear computing module 45 is exported and register file module 3 carries out XOR; The 4th group of bright/encrypt data that the 3rd XOR module 48 is exported for data that the second linear operation module 46 is exported and register file module 3 carries out XOR; Cipher key spreading wheel s operation control signal or the enciphering/deciphering wheel s operation control signal of second selector 49 for exporting according to finite state machine module 2, selects output from the data of the second XOR module 47 or from the data of the 3rd XOR module 48.

Below in conjunction with Fig. 1 and Fig. 2, illustrate the operation principle of this coprocessor: interface module 1 is processed the order that outside control module is sent, and realizes the control to finite state machine module 2 and register file module 3.If outside control module sends, write data command, 1 of interface module writes data in register file module 3 in corresponding register; If outside control module sends read data order, 1 of interface module reading out data issue outside control module in corresponding register from register file module 3; If it is enciphering/deciphering order that outside control module sends, 1 of interface module is issued finite state machine module 2 order, and monitors the operating state signal of finite state machine module 2, until computing finishes.

When finite state machine module 2, receive after the enciphering/deciphering order that interface module 1 sends, by control register file module 3 and logic function module 4, complete 32 cipher key spreading of taking turns and 32 enciphering/decipherings of taking turns, and a final running status is sent to interface module.

Logic function module 3 is under the control of finite state machine module 2, and the data that register file module 3 is sent here are carried out the wheel computing of cipher key spreading and the wheel computing of enciphering/deciphering in turn, and operation result is sent to register file module 3.

When carrying out cipher key spreading computing, the wheel that constant generation module 41 is exported according to finite state machine module 2 is counted formation constant, and meanwhile, first selector 42 is selected this constant of output under the control of finite state machine module 2.First group of bright/encrypt data of the first 43 pairs of XOR modules, second group of bright/encrypt data, the 3rd group of bright/encrypt data and this constant carry out XOR; The operation of S box is carried out in the output of 44 pairs of the first XOR modules 43 of S box computing module; Linear operation is carried out in the output of the second 46 pairs of linear operation modules S box computing module 44; The output of the 3rd 48 pairs of XOR modules the second linear operation module 46 and the 4th group of bright/encrypt data carry out XOR.Finally, second selector 49, under the control of finite state machine module 2, is selected output from the data of the 3rd XOR module 48, and these data is deposited in the corresponding registers of register file module 3.And, every through cipher key spreading wheel computing just export a round key, altogether need to generate 32 round key, be used in successively in different enciphering/deciphering wheel computings.

When carrying out enciphering/deciphering computing, first selector 42 selects output from the round key in the corresponding registers of register file module 3 under the control of finite state machine module 2; First group of bright/encrypt data that the data that the first 43 pairs of XOR modules first selector 42 is exported and register file module 3 are exported, second group of bright/encrypt data, the 3rd group of bright/encrypt data carry out XOR; S box computing module 44 carries out nonlinear operation for the data that the first XOR module 43 is exported; Linear operation is carried out in the output of 45 pairs of S box computing modules 44 of the first linear computing module; The output of second 47 pairs of XOR modules the first linear computing module 45 and the 4th group of bright/encrypt data carry out XOR.Finally, second selector 49, under the control of finite state machine module 2, is selected output from the data of the second XOR module 47, and these data is deposited in the corresponding registers of register file module 3.

In addition, preferably, S box computing module comprises four parallel S box arithmetic elements, and each S box arithmetic element is carried out nonlinear operation to the input data of 8 bits.In addition, this S box arithmetic element adopts the generation method based on Algebraic Structure.For the input data a of 8 bits, first carry out affine transformation and obtain a*A ₁+ C ₁, secondly, to a*A ₁+ C ₁at finite field gf (2 ⁸) on carry out inversion operation and obtain (a*A ₁+ C ₁) ^-1, then to (a*A ₁+ C ₁) ^-1carry out again affine transformation and obtain (a*A ₁+ C ₁) ^-1* A ₂+ C ₂, wherein, vectorial C ₁, C ₂for (1,1,0,0,1,0,1,1), GF (2 ⁸) by irreducible function x ⁸+ x ⁷+ x ⁶+ x ⁵+ x ⁴+ x ³+ x ²+ 1 generates transformation matrix A ₁and A ₂ $\left[\begin{array}{c}11100101\\ 11110010\\ 01111001\\ 10111100\\ 01011110\\ 00101111\\ 10010111\\ 11001011\end{array}\right].$

Therefore the Mathematical Modeling that, can determine each S box arithmetic element is:

S=(a*A ₁+C ₁) ^-1*A ₂+C ₂

Wherein, S is the output data of S box arithmetic element, and a is input data.

The S box implementation method of this employing based on Algebraic Structure, compares traditional look-up table, can further reduce the cost that realizes that coprocessor is realized SM4 algorithm.

The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in claim scope of the present invention.

Claims (4)

1. a coprocessor of realizing smart card SM4 cryptographic algorithm, is characterized in that, comprising: interface module (1), finite state machine module (2), register file module (3) and logic function module (4), wherein,

Described interface module (1) is carried out data interaction for realizing with outside control module;

Described finite state machine module (2) is for according to the enciphering/deciphering order of described interface module (1), described register file module (3) and described logic function module (4) being controlled, and returns to operating state signal to described interface module (1);

Described register file module (3) is for carrying out read/write operation according to the read/write command of described interface module (1) to corresponding registers, and under the control of described finite state machine module (2), data are delivered to described logic function module (4) and process and fetch corresponding result;

Described logic function module (4) is under the control in described finite state machine module (2), the data that described register file module (3) is sent are carried out the wheel computing of cipher key spreading and the wheel computing of enciphering/deciphering in turn, until 32 take turns end, and to described register file module (3), return to the result of each computing.

2. the coprocessor of realizing smart card SM4 cryptographic algorithm according to claim 1, is characterized in that, described logic function module (4) comprising:

Constant generation module (41), for the wheel number of exporting according to described finite state machine module (2), generates the constant for cipher key spreading;

First selector (42), for cipher key spreading wheel s operation control signal or the enciphering/deciphering wheel s operation control signal of exporting according to described finite state machine module (2), select output from the constant of described constant generation module (41) or from the round key of described register file module (3);

The first XOR module (43), first group of bright/encrypt data, second group of bright/encrypt data, the 3rd group of bright/encrypt data for data that described first selector (42) is exported and described register file module (3), exported carry out XOR;

S box computing module (44), carries out nonlinear operation for the data that described the first XOR module (43) is exported;

The first linear computing module (45), carries out the first linear operation for enciphering/deciphering for the data that described S box computing module (44) is exported;

The second linear operation module (46), carries out the second linear operation for cipher key spreading for the data that described S box computing module (44) is exported;

The second XOR module (47), the 4th group of bright/encrypt data exporting for data that described the first linear computing module (45) is exported and described register file module (3) carries out XOR;

The 3rd XOR module (48), the 4th group of bright/encrypt data exporting for data that described the second linear operation module (46) is exported and described register file module (3) carries out XOR;

Second selector (49), for cipher key spreading wheel s operation control signal or the enciphering/deciphering wheel s operation control signal of exporting according to described finite state machine module (2), select output from the data of described the second XOR module (47) or from the data of described the 3rd XOR module (48).

3. the coprocessor of realizing smart card SM4 cryptographic algorithm according to claim 2, is characterized in that, described S box computing module comprises four parallel S box arithmetic elements, and each S box arithmetic element is carried out nonlinear operation to the input data of 8 bits.

4. the coprocessor of realizing smart card SM4 cryptographic algorithm according to claim 3, is characterized in that, the Mathematical Modeling of described S box arithmetic element is:

S=(a*A ₁+C ₁) ^-1*A ₂+C ₂

Wherein, S is the output data of S box arithmetic element, and a is input data, C ₁, C ₂for (1,1,0,0,1,0,1,1);

$A_1=A_2=\left[\begin{array}{c}11100101\\ 11110010\\ 01111001\\ 10111100\\ 01011110\\ 00101111\\ 10010111\\ 11001011\end{array}\right].$

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