CN1125006A - Field Programmable Logic Devices Dynamically Interconnected to a Dynamic Logic Core - Google Patents

Field Programmable Logic Devices Dynamically Interconnected to a Dynamic Logic Core Download PDF

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CN1125006A
CN1125006A CN94192286A CN94192286A CN1125006A CN 1125006 A CN1125006 A CN 1125006A CN 94192286 A CN94192286 A CN 94192286A CN 94192286 A CN94192286 A CN 94192286A CN 1125006 A CN1125006 A CN 1125006A
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logic
dynamic
input
field programmable
buffer
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N·B·巴特
K·乔哈里
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University of California San Diego UCSD
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University of California San Diego UCSD
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06C—DIGITAL COMPUTERS IN WHICH ALL THE COMPUTATION IS EFFECTED MECHANICALLY
    • G06C13/00—Storage mechanisms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

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  • Engineering & Computer Science (AREA)
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  • Computing Systems (AREA)
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  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The structure, operation and design of a new field programmable logic device is described. The apparatus (20) implements a circuit using a dynamic logic core (22) that executes hierarchical logic corresponding to the logic level of the implemented circuit. The logic inputs of the dynamic logic core are obtained from a dynamic interconnect array (26). The appropriate logic inputs for a given logic level are dynamically selected and routed by the dynamic interconnect array (26). The dynamic interconnect array (26) buffers signals required at subsequent logic levels when needed. A dynamic interconnect array (26) selects logic inputs from the circuit output signals, the buffer signals, and the dynamic logic core output signals for a given logic level.

Description

Dynamically be interconnected to the field programmable logic device of a dynamic logic kernel
Concise and to the point description of the present invention
The present invention is relevant with field programmable logic device.More particularly, the present invention relates to a kind ofly utilize logic kernel of dynamic interconnect access, and this kernel can structure dynamic change, field programmable logic device, operation and design in classification logic level.Background of the present invention
Field programmable logic device (PLD) is widely used in the logic function that realizes the control electronic equipment.The mask-programmable logical device is to realize programming by manufacturer in the process of this equipment of manufacturing.Contrast with it, field programmable logic device is sold with programming state not by manufacturer.The buyer of this equipment programmes to carry out desired function to its at " scene " subsequently.Present invention is related to field programmable logic device (FPLD).Field programmable gate array (FPGA) is a kind of form of FPLD.
The principal benefits of FPLD is that user-programmable provides fast and not expensive prototyping.Another important benefits relevant with FPLD is the programming again that they can realize different designs.
The particular design that realizes in given structure is with electric design automation (EDA) technology, is also referred to as computer-aided design (CAD) (CAD) technological development development.Eda tool comprises logic compositor, physical design tool and fixed time testing device.The logic compositor changes into a net table of describing circuit component and interelement binding with a senior description of a circuit.A given net table, physical design tool are then determined the location of element and are to realize that interelement links required lead line segment.Normally calculated amount is huge for this step in the design process.Therefore, this process that becomes more meticulous is one to be ready the work carried out.
The timing characteristic of circuit described in the fixed time testing device analysis net table.Based on the timing characteristic of this circuit, the slip-stick artist can revise the net table to improve the performance of circuit.
People's expectation fully automatically realizes a given circuit in a FPLD structure.Realize this expectation, the structure that importantly designs this FPLD can accurately be estimated its regularly characteristic to guarantee eda tool, and to given circuit place and route easily.The structure of this FPLD should have aforesaid feature and don't weaken the ability that realizes complicated circuit.
Look-up table (Look-Up Table-LUT) is widely used among the FPGA.LUT is a digital device that a given input value set is provided an output valve.This output valve be stored in one can storage unit by the input value addressing in.
FPGA based on LUT uses a LUT sequence to construct a multilevel hierarchy.In such equipment, in second LUT, combine to produce a new output valve with new input value from the output of first LUT.This second LUT can be considered one second logic level.Equally, the output valve from second LUT can combine with the input value that increases in the 3rd LUT then.In such equipment, three logic levels are arranged, a LUT is arranged in each logic level.
There are a lot of problems relevant with traditional FPGA based on LUT.As described in the earlier paragraphs, these equipment have a sequential structure, and LUT is distributed on the silicon chip of realizing this logic in this structure.This method expends the space.Another problem relates to the line between each LUT.Connection between LUT may be introduced unpredictable undesirable signal propagation delays.This propagation delay may require the layout again of circuit and rewiring till whole timing constraints all satisfy.In some cases, on a FPGA, perhaps can not satisfy rational timing constraint to a given circuit layout and wiring.Summary of the present invention
New structure, operation and the design of field programmable logic device have been disclosed.This equipment uses a dynamic logic kernel to realize a circuit, and this dynamic logic kernel is carried out and the corresponding classification logic of circuit logic level that is realized.From a dynamic interconnection array, obtain the logic input of dynamic logic kernel.By dynamic interconnection array is that a given logic level is selected suitable logic input and selected the path.When needs, can be by dynamic interconnection array required signal of buffer memory on logic level in succession.Dynamically interconnection array is that a given logic level is selected the logic input the nuclear export signal in circuit input signal, buffered signal and dynamic logic.The Short Description of figure
For understanding essence of the present invention and target better, in conjunction with the accompanying drawings the present invention is made detailed description, wherein:
Fig. 1 is the high-rise graphic representation of FPLD of the present invention.
Fig. 2 is the sketch of FPLD of the present invention.
Fig. 3 has described one can work in coordination with the level counter that uses with the present invention.
Fig. 4 has described one based on the used dynamic logic module of the present invention.
Fig. 5 represents based on the present invention and treatment step that design is relevant of realization in a FPLD.
Fig. 6-1 has described an equipment that can be used for the treatment step in the execution graph 5.
Fig. 6-2 has described the download logic (downloadedlogic) that equipment generated of Fig. 6 A and has used relation between this FPLD that downloads logic in succession.
Fig. 7 describes the control sequence relevant with the operation of FPLD of the present invention.
Fig. 8 be one in order to show the sketch of a circuit of the present invention, this circuit is realized in FPLD of the present invention.
Fig. 9 describes logical table or the look-up table relevant with Fig. 8 electrical schematic diagram; These tables are realized by dynamic logic module of the present invention.
Figure 10-13 has described becomes the realization of Fig. 8 of FPLD of the present invention circuit.
Figure 14 is a diagram of showing a circuit of the present invention, and it is realized in FPLD of the present invention.
Figure 15 describes logical table or the look-up table with the decorrelation of Figure 14 circuit diagram; These tables are realized in dynamic logic module of the present invention.
Figure 16-20 is described as being Figure 14 circuit of a FPLD of the present invention and realizes.
In each accompanying drawing, identical reference number refers to corresponding parts.Detailed description of the present invention
Fig. 1 has described one based on field programmable logic device of the present invention (FPLD) 20.FPLD20 comprise one its contain the dynamic logic kernel 22 of dynamic logic module 24 arrays.With more detailed description, each dynamic logic module 24 is carried out a logical operation collection as here.This logical operation set has a lot of independent logical stages or level.The logical set that each logical set is represented corresponding to the gate leve of being realized among the FPLD20 with circuit.
The dynamic logic kernel is two to be coupled with a dynamic interconnection array 26.Dynamically interconnection array 26 dynamically changes to the connection of dynamic logic kernel 22, so each logic level of logic kernel 22 receives suitable input signal.Because identical line resource is used to realize entire circuit, therefore, the present invention optimizes silicon resource.Another advantage of this technology is that the circuit of circuit is directly, thereby can simplify the design automation of circuit.
Interface lock storage 28 is at dynamic logic kernel 22 with dynamically between the interconnection array 26.As what below will describe in detail, a buffer array 30 is used for the selected logic level of bypass dynamic logic kernel 22.At last, input latch 32 and output latch 34 have been used in the realization of FPLD20 of the present invention.
Fig. 2 is that Fig. 1 FPLD20 represents in more detail.Dynamic logic module 24 is by a crossed logic switches (L-Cross Bar) module 40 signal of feeding, and the L-cross switch module has constituted the part of dynamic interconnection array 26 simultaneously.As what below will discuss, L-cross switch module 40 can have a variety of implementations.L-cross switch module 40 should be regarded a final equipment giving dynamic logic module 24 delivery values as now.L-cross switch module 40 is handled by a L-cross bar switch dynamic-configuration controller 42.
An input of controller 42 is " level " values.As what below will describe in detail, this grade value is the logic level of the circuit realized.The suitable control that decides L-cross switch module 40 of this one-level value.
Fig. 3 describes a level counter controls module 44 that can be employed according to the present invention.Module 44 is closed the counter of a tracking circuit level.The operation of controller 48 control internal level counters 50.If select multicore tablet mode to realize the present invention, as what below will illustrate, the control that activates next chip of controller 48 so, and use is from the signal of previous chip.Otherwise, no matter these signals.Internal level counter 50 is according to this pattern and be stored in word controlled device 48 in the counter 46 and increase progressively or reset.As illustrated in fig. 2, the word in the counter 50 is sent to the various kinds of equipment among the FPLD20 subsequently, and L-cross bar switch 40 is sent input value, buffer values with from the output of dynamic logic module 24 into dynamic logic pattern 24.To illustrate that as following legend the interconnection to dynamic logic module 24 dynamically changes L-cross bar switch 40 according to each grade of realizing circuit.Describe according to Fig. 2, input and latch 32 receives input value.These input values are sent to traffic pilot 54 subsequently.Traffic pilot 54 also receives the value from cache array 30.Control by 56 pairs of selection signals of an elementary input/buffer (PI/Buffer) selection control from input or cache array 30.
The output of traffic pilot 54 passes to a buffer cross switch module 58 (B-Cross Bar).B-cross switch module 58 is given and is appeared at first logic level value, also determines the path for the value of logic level in the future.Particularly, the value that is bypassed to another logic level is reached array cache 30 from the B-cross switch module.As below the traffic pilot 61 of explanation being used for choosing from the value of B-cross switch module 58 or choosing a output valve from dynamic logic kernel 22.Latch 34 is traffic pilot 61 storage control signals.
B-cross switch module 58 is by 60 controls of B-cross bar switch dynamic-configuration controller.A logic level value forms an input of B-cross bar switch dynamic-configuration controller 60.As what represent already, this grade value is corresponding to the logic level of the circuit of realizing.So figure describes, but value bypass B-cross bar switch 58 and be linked to L-cross switch module 40.As noted earlier, be sent to dynamic logic module 24 subsequently from the value of L-cross bar switch.The output of dynamic logic module 24 all is being sent to output latch 34 after the logic level execution.
Fig. 4 has described one based on dynamic logic module 24 of the present invention.Can use look-up table, with module based on traffic pilot, or other makes up and realizes the dynamic logic module.The present invention preferably adopts the module based on look-up table, because they allow to realize whole combination functions to an input value collection.Look-up table can have single or multiple output.
Fig. 4 has described one and has had the K input, the dynamic logic module 24 of 2 output LUT forms.K input value can be considered the number of the address wire that is used for LUT.Therefore, if K equals 3, then module 24 realizes with the LUT form with 3 address wires.Except input value, also need the level input.As previously mentioned, this grade is corresponding to the logic level of a circuit of just realizing.In case input and level are set up, traffic pilot 66 is used to select suitable logical bit by its selection wire.
24 each output of dynamic logic module need L * 2 KThe storer of position." L " is corresponding to the upper limit of the progression that can realize in a given FPLD equipment.There are a lot of methods level selection wire and K address wire can be combined.The unique technique that is used for a given realization of this structure depends on the use and the storer of silicon area and reads the time, and they depend on employed technology.
General structure of the present invention has been described now.Notice turns to the structure and the operation of this structure now.At first structure of the present invention and operation are carried out recapitulative description.With reference to several examples, will give detailed especially explanation subsequently to structure of the present invention and operation.
Fig. 5 described with a FPLD structure of the present invention on realize the treatment step that circuit design is relevant.The first step of processing procedure is the description (frame 70) that receives a circuit.Usually, the description of circuit will adopt hardware description language (HDL), register transfer language or a circuit diagram to describe, and all these is well known to a person skilled in the art.
Next step of this process is to confirm various logic level in circuit (frame 72).This step carries out with well-known logic synthetic technology.
Circuit can be divided into a lot of logic levels.Promptly an input signal collection is at first handled to produce the first order of output valve by first group of circuit component.First order output valve subsequently, and may also have some initial input signal to be delivered to second group of circuit component.This process constantly repeats by a lot of logic levels.The specific example of this operation will be described below.
Next step of this process is to create a logical table (frame 74) for each logic level.In this step,, need to create a logical table in order to define the performed logical operation of logic module on each logic level.
Next step of this process produces logic (frame 76) for the PI/Buffer controller.This logic that produces cause one group different the processing stage (logic level) be delivered to the traffic pilot selective value of traffic pilot 54.For example, when handling in second logic level in order to be transferred into from a value in first logic level of buffer array 30, a suitable selection signal will be generated to allow this signal transmission by traffic pilot 54.
Producing B-intersection (B-Cross) controller logic is next step (frame 78) of this process.In this step, the logic of generation will allow B-cross bar switch 58 to give to the term of execution value being buffered at a logical stage then and select the path.
Next step of this process is that definition L-intersects (L-Cross) controller logic (frame 80) in this step, and logic is defined as allowing L-cross bar switch 40 to give a value that is latched to dynamic logic kernel 22 then selected path.
The logic of front is 74,76, and after the definition, it is downloaded (frame 82) to a configuration memory 99 in 78,80 steps.As below with illustrational.In case download, this logic can be performed.
Fig. 6 A has described a device 90 that can be used for execution graph 5 processes.Device 90 comprises a CPU (central processing unit) (CPU) 92, and this CPU is by a bus 93 and user interface 94 couplings.User interface facilities 94 is any combination of known computing machine input and output device, as keyboard, Genius mouse, scanner, monitor, printer etc.User interface 94 receives the description of a circuit 96 that is implemented in FPLD of the present invention.
CPU92 carries out a large amount of programs that are stored in memory 98.This logic of class compositor that these programs are known with the supplementary copy field usually.
CPU92 carries out a logic level recognizer 100 (corresponding step 72), a logical table generator 102 (corresponding step 74), a PI/Buffer controller maker (corresponding step 76), a B-Switch Controller maker 106 (corresponding step 78) and a L-Switch Controller definition device (corresponding step 80).These modules produce logic level, logical table, elementary input/buffer (PI/Buffer) logic, B-Switch Controller logic and L-Switch Controller logic separately.
Under the guiding of CPU92, the logic of generation is downloaded a non-volatile config memory 99 by a suitable interface.Being used at the scene, the interface of programmable logic device storing value is known in the art.
Fig. 6 B has described the relation between non-volatile config memory 99 and the FPLD20 of the present invention.Particularly, after non-volatile config memory 99 was mounted with suitable logical value, it can be independent of equipment 90 and be used.Particularly, non-volatile config memory 99 is connected with FPLD20.Standard memory download circuit 101 is used in FPLD20 and goes up to coordinate from the logical value of the reception of non-volatile config memory 99.Described in Fig. 6 B, FPLD20 receives the logic that is used for dynamic logic kernel 22, L-cross bar switch controller 42, PI/Buffer controller 56 and B-cross bar switch controller 60.
Fig. 7 has described and the relevant treatment step of FPLD20 operation of the present invention.Process at first is to read an input value (frame 120).This input value is to obtain by the traffic pilot 54 that is controlled by PI/Buffer selection control 56.Subsequently, determine the path for buffer values (frame 122) and logical value (frame 124).Buffer values is determined its path by B-cross bar switch controller 60, and logical value is determined its route by L-cross bar switch controller 42.These operations are normally carried out simultaneously, although they are described as sequential operation in Fig. 7.
Next treatment step relevant with FPLD of the present invention is that this logic is among dynamic logic module 24 for a given stage or logic level actuating logic (frame 126).Simultaneously, this logic level increases progressively (frame 128) by counter 4, and judges whether whole logic level has all been carried out handling (decision block 130).Although step 126,128 and 130 among Fig. 7 for for the purpose of illustrating, and be described as sequential operation, preferably they all are executed in parallel.If all logic level is all processed, then produce an output valve.Otherwise processing begins once more at frame 120 places.
The present invention has been described now fully.Yet, being more abundant understanding the present invention, we see some examples now.Fig. 8 is the gate level circuit figure of an exemplary circuit 140 that realizes according to the present invention, 3 inputs (" a ", " b ", " c ") of this circuit be delivered to or (OR) door export to produce one " G ".2 inputs (" d ", " e ") be transferred to one with (AND) door 144 with produce one " H " output.Or door 146 receives " c " input and " H " input.XOR (XOR) door 148 receives " G " and " H " input.The feature of circuit 140 can be showed by following Boolean expression:
G＝a＋b＋c (1)
H＝d*e (2)
x＝G* H＋ G＋H (3)
y＝c＋H (4)
Fig. 8 has constructed one " circuit description " corresponding to Fig. 5 step 70.Expression formula (1) provides in addition (but of equal value) a kind of " circuit description " by (4).According to the realization of Fig. 5 frame 70, must provide the special form of a kind of " circuit description ".Illustrative hereto example will be enough with a figure or expression formula form.
Fig. 5 point out accept a circuit describe after (frame 70), with a circuit is realized FPLD into of the present invention is associated next step be recognition logic level (frame 72).With regard to the circuit of Fig. 8, two logic levels are arranged.The first order is one or 142 and one and door 144.The 2nd grade be one or the door 146 and XOR gate 148.Handling relevant next step with Fig. 5 is to create a logical table (frame 74) for each logic level.Fig. 9 has described the logical table corresponding to Fig. 8 circuit.In the first order, a logical table provides for " G " output and " H " output.With reference to the logical table that is used for " G " output, 8 addressable values (2 have been noticed corresponding to 3 input values (" a ", " b ", " c ") 3).In hurdle " G ", provide the logic relevant with each input value.That is to say, for or door 142, unless all input value is 0, otherwise its output valve will be " 1 ".Logical table for " H " output only has 2 input values.Therefore, the highest input position can be considered " a haveing nothing to do " condition.Therefore, the logic of ensuing 4 values of the logical and of preceding 4 values is identical.Under any circumstance, the output " H " with door 144 will only be " 1 " when " d " and " e " is " 1 ".
The second level of Fig. 9 comprises the logical table of " x " output and " y " output.The logical table of " x " output has been described the logic of XOR gate 148 in the logic of description of " y " output logic table or door 146, notices that once more each table only has 2 inputs, thereby " a haveing nothing to do " condition is arranged that this condition causes the output pattern of a repetition.
Consistent with Fig. 5 step 76, the PI/Buffer controller logic can produce now.In this example, in the first order of circuit, PI/Buffer selection control 56 will produce selects signal, thereby can pass through traffic pilot 54 from whole input values (" a ", " b ", " c ", " d ", " e ") of input latch 32.In the second level of logic,, will produce one and select signal in order to allow buffer value " c " by traffic pilot 54.
The B-Switch Controller logic relevant with Fig. 5 step 78 also can derive in this junction.In this example, B-intersection dynamic-configuration controller must offer the logic that the value " c " that receives on the first order is determined the path.In second logic level, need not operation.
The L-Switch Controller logic relevant with Fig. 5 step 80 also can be as giving a definition.At first logic level place, L-cross bar switch dynamic-configuration controller 42 must be given input value " a ", and " b ", " c ", " d " and " e " determines the path.These values then are latched in the dynamic logic kernel 22.At second logic level place, storage input value " G ", " H " and " c ".
According to Fig. 5 step 82, logic is in front described as Fig. 7 after downloading, and equipment of the present invention can begin to carry out.
Figure 10 to 13 has illustrated of the present invention structure and the operation relevant with previous examples.These figure will be that train of thought is described with the treatment step of describing among Fig. 7.
Figure 10 has described a FPLD 20A who can be used for realizing Fig. 8 circuit.Device 20A is usually corresponding to the device of Fig. 2.Notice that L-cross bar switch 40 and B-cross bar switch 58 are described as the grid of a point of crossing 150.Figure 10 does not describe PI/Buffer selection control 56.Remaining figure will not describe L-cross bar switch controller 42 or B-cross bar switch controller 60.
Figure 11 has described the result after the execution in step 120,122 and 124 of Fig. 7.But should recall some the step executed in parallel in these steps.But with example explanation the present invention, these steps will usually be carried out in a sequential manner and be described out for clearly.
These figure have described input value " a ", and " b ", " c ", " d " and " e " are latched at (Fig. 7 step 120) among the input latch 32.This figure also describes with a black circle and gives buffer values " c " by B-cross bar switch 58 selected paths (Fig. 7 step 122).This figure has also described and has given input value " a ", and " b ", " c ", " d " and " e " determines the path by L-cross bar switch 40 (Fig. 7 step 124).
Figure 12 describes the result behind Fig. 7 execution in step 126,128,130 and 120.This figure describes from the value of L-cross bar switch 40 and B-cross bar switch 58 latch 28 of packing into.Subsequently, L-cross bar switch value is reached corresponding to " G " logical table of level 1 and the dynamic logic module 24A and the 24B of " H " logical table.Dynamic logic module 24A generation value G, and dynamic logic module 24B generation value " H " (Fig. 7 step 126).When carrying out this logic, counter 44 (Fig. 3's, be not presented among Figure 12) increases progressively this logic level (frame 128 among Fig. 7).In this example, only first logic level is processed, therefore also has a logic level necessary processed.
Because the 2nd logic level is last logic level, needn't determine path (Fig. 7 frame 122) therefore for buffer values.On the other hand, must select path (Fig. 7 frame 124) for logical value by L-cross bar switch 40.Attention is in Figure 12, give the selected direct path of coming from dynamic logic module 24A of passing through the L-cross bar switch on the point of crossing 152 of " G " output similarly, give " H " output the selected direct path of coming from dynamic logic module 24B of passing through the L-cross bar switch on point of crossing 154 and 156.At last, give the definite path of passing through the L-cross bar switch at 158 places, point of crossing of value " c " of buffering.
L-cross bar switch controller " is write " these cell enable.In definition L-cross bar switch controller logic (frame 80 among Fig. 5), well-known, for example " X " logical table of being realized by dynamic logic module 24A on second logic level needs input " G " and " H ".Therefore, two of dynamic logic module 24A input ends are enabled to receive " G " and " H " value.More particularly, 160 and 162 row are enabled so that receive data from dynamic logic module 24.The implementation of cross bar structure of the present invention is discussed below.
Figure 13 describes and Fig. 7 step 126,128 processing relevant with 130.Figure 13 represents that second level input value " G " and " H " are latched in the latch 28.These values are transferred in the logical table of being realized by dynamic logic module 24A " x " then.Second level input value " H " and " c " are latched similarly in the logical table of being realized by dynamic logic module 24B " y ".
These logic modules are carried out their logics (Fig. 7 step 126) separately then, and the unison counter (not shown) is incremented (Fig. 7 step 128).Because second level logic is processed, so " x " and " y " output valve is reached output latch 34.
Equipment 20A can handle the another one set (Fig. 7 step 120) of input value now.Figure 13 has described the new set of input value in the input latch 32.The mode that the processing of these values was described with the front is carried out.
Figure 14 describes the another one circuit 178 that can be implemented according to the present invention.Analysis circuit 178 has disclosed it 4 logic levels.First logic level is handled input signal, and does not rely on the output from the another one level.First logic level comprises XOR gate 180,182,184, with door 186 and with door 188.Second signal that logic level is handled input signal and produced at first logic level place.The door that is positioned at second logic level have XOR gate 190, with door 192, with door 194 or door 196 (it with 3 with a door 197A, 197B, 197C connection) and with door 198.The 3rd logic level is handled at first logic level and the 2nd signal that logic level produces; It also can handle input signal, but does not do so in this example.The 3rd logic level of this example has been closed or door 200, with door 202 with door 204 (it with or 205 be connected).The 4th logic level also is the last logic level of this example, produces output valve.The 4th logic level contain with door 206, XOR gate 208 with or door 210 (it be connected) with door 212.For more complicated circuit, the known directed acyclic graph of those of ordinary skill in the art can be used for simplifying classification process.
Therefore, Figure 14 represents a circuit description (Fig. 5 step 70).The preceding paragraph content identification the relevant logic level (Fig. 5 step 72) of circuit therewith.Figure 15 has described the logical table (Fig. 5 step 74) of each grade.The table " HO " of noting level 1 produces 2 output valves.Output valve " O " requires 3 inputs " b ", " c " and " d " (go to XOR gate 184 and with door 186).On the other hand, value " H " only needs 2 inputs " c " and " d ", therefore there is " a haveing nothing to do " state in input value b.Can construct this class combination to realize dynamic logic module 24 efficiently.The table " KI " of level 2 is another one examples of resource sharing example.
Be related to based on the relevant next treatment step of FPLD of the present invention with one of design and be that each controller produces suitable logic.For current example, PI/Buffer controller 56 must be selected the whole input values in the 1st logic level.In the 2nd logic level, PI/Buffer controller 56 will allow all initial input value to pass through traffic pilot 54 for further handling.In the 3rd logic level, PI/Buffer controller 56 will allow M signal " F " " H ", and " O " and input signal b pass through.In the 4th logic level, PI/Buffer controller 56 will allow terminal stage input value " H ", and " B ", " F ", " G " and " K " passes through for processing.
B-cross bar switch dynamic-configuration controller 60 will with 4 stages of logic to realize the circuit of Figure 14.To enable the B-cross bar switch at the chopped-off head B-of logic Switch Controller 60 and give whole input values selected path, because they are that back to back processing is required.In the 2nd logic level, B-Switch Controller 60 will enable the B-cross bar switch, so that seek the path only for " b " value that will need in the 4th logic level.In the 3rd logic level, B-Switch Controller 60 will enable the B-cross bar switch so that give the required value " F " of requirement processing on the 4th logic level, and " H " and " b " seeks the path.In last logic level, B-Switch Controller 60 needn't start any paths control.
The logic of L-cross bar switch dynamic-configuration controller 42 is necessary for dynamic logic module 24 and enables suitable input in each logic level.In the 1st logic level, L-Switch Controller 42 enables L-cross bar switch 40, and this is that value " c " and " d " for value " b ", " c " and " d " and the dynamic logic module 24C of the value " a " of giving dynamic logic module 24A and " e ", dynamic logic module 24B determines the path.In the 2nd logic level, L-Switch Controller 42 enables L-cross bar switch 40, and this is in order to give the value " H " of dynamic logic module 24A, value " a " and " e " of " F " and " b " dynamic logic module 24B, and dynamic logic module 24C " c ", " b " and " d " determines the path.In the 3rd logic level, L-Switch Controller 42 enables L-cross bar switch 40, this is in order to give value " G ", " M " and " K ", the value " F " of dynamic logic module 24B, " H " and " I " of dynamic logic module 24A, and the value " G " of dynamic logic module 24C, " P " and " O " are selected path.In the 4th logic level, L-Switch Controller 42 enables L-cross bar switch 40, this is the value " H " for the value " J " of giving dynamic logic module 24A, " N " and " Q ", dynamic logic module 24B, " F ", the value " G " of " b " and dynamic logic module 24C, " J " and " K " determines the path.
Return Fig. 5, the suitable logic that is used for logical table, PI/Buffer controller, B-Switch Controller and L-Switch Controller has been described now.This logic can download to nonvolatile memory (frame 82) now.
The input signal relevant with Figure 14 circuit handled and will be illustrated now with reference to Fig. 7 and Figure 16 to 20.Figure 16 has described the treatment step 120,122 and 124 of Fig. 7.Particularly, this figure illustrates the input value input latch 32 (Fig. 7 frame 120) of feeding.This figure also shows to the definite path of passing through the B-cross bar switch 58 (Fig. 7 frame 122) of point of crossing 220 to 228 of buffer values.Figure 16 has also described the logical value that is determined the path by L-cross bar switch 40.For example, attention point of crossing 230 determines the path for value " a ", and the path is sought by point of crossing 232 values of giving " e ".Each value in these values is transferred to a latch 28, then by dynamically logic module 24A execution.
Figure 17 has described the treatment step relevant with Fig. 7 126,120,122 and 124 (recall several steps in these steps be can executed in parallel) in a sequential manner.This Figure illustrates latch 28 and carry out loading dynamic logic piece 24 (Fig. 7 steps 126) for logic.This figure has also described latch 28 loading buffer devices 31.As shown in Figure 7, the treatment step of following will increase whether all levels all processed (decision block 130) of logic level (frame 128) and inquiry.Do not express the increase of logic level at Figure 17, but for this purpose and the Circuits System that discloses is revealed in Fig. 3.Because do not have in the whole logic levels of this joint processed, so obtain new input (Fig. 7 frame 120).Therefore, on this meaning, as noted earlier, the value during PI/Buffer controller 56 will allow all to delay is by traffic pilot 54.Then, suitable buffer values will be packed in the B-cross bar switch 58 (Fig. 7 frame 122).Figure 17 is described in and determines the path on the point of crossing 234 value " b ", and only gives then and must be selected the path by this this " b " value of handling on the abutment of usefulness.
At last, to have described be the logical value (Fig. 7 frame 124) that the 2nd logic level is loaded to Figure 17.For example, notice that output valve " F " is loaded into L-cross bar switch 40 on point of crossing 236.This value directly obtains from dynamic logic module 24A.It also is that the output valve " H " that directly receives from dynamic logic module 24A is determined the path that point of crossing 238 is given.Point of crossing 238 seeks the path for the value " b " of buffering before.
Figure 18 has described the continuation processing procedure relevant with Figure 14 circuit.This figure describes the 2nd grade of logical value of the latch 28 of packing into.This figure also describes the output of actuating logic.This figure has shown also how these outputs are handled again according to the present invention.For example, notice that output G is transmitted away by point of crossing 250 and 252, so they then can be used as the input of dynamic logic module 24A and 24C term of execution of the 3rd logic level.For the next one is handled (value " F " and " O " are used for logic level 3 and value " b " is used for logic level 4), Figure 18 also describes to value " F ", " O " and " B " point of crossing 254,256 and 258 on B-cross bar switch 58 and determines the path.At last, Figure 18 describes to the selected path by L-cross bar switch 40 of former buffer value.For example, point of crossing 260 seeks the path for the value " O " that cushioned in the past, and point of crossing 262 determines the path for the value " P " of former buffering.During logic level 3, these two values are all as the input of dynamic logic module 24C.
Figure 19 has described 3rd logic level relevant with the present invention and has handled.The 3rd logic level input value is revealed as the content in the latch 28.The 3rd logic level output valve is revealed as the input signal of dynamic logic module 24.This figure describes the logical value " N " that just is being transmitted by L-cross bar switch 40, " J " and " Q ".Logical value " N " sends by point of crossing 280, and logical value " J " sends by point of crossing 282 and 284, and logical value " Q " sends by point of crossing 286.Its residual value in the L-cross bar switch 40 is postponed and is obtained towards device 31.Buffer values " F " transmits by crossbar switch 290, and value " G " transmits by cross bar switch 292, and value " H " transmits by cross bar switch 294, and value " K " transmits by cross bar switch 296, and value " b " transmits by cross bar switch 298.Attention no value in B-cross bar switch 58 transmits, because final logic level will be carried out at once.
Turn to Figure 20 now, the 4th grade of logic input is indicated in the latch 28.Figure 20 also represents dynamic logic module output valve " x ", " y " and " z ".Because this is last logic level, these values are transferred to output latch 34.This figure also describes the input of the next stage of input circuit 20B.This configuration is identical with the configuration of Figure 16 that discussed the front.
Notice turns to some to realize considering now.Suppose that a given FPLD has L level and C dynamic logic module 24, each dynamic logic module 24 has m output.Suppose that the logical network that will realize is a feasible network, that is, each node in the network has＜=individual input of K (smaller or equal to K) and the individual output of C＜=m (smaller or equal to m).If not like this, known logic synthetic technology can be converted into it such network.The built-up section that makes this feasible network is by topological classification.Make ρ represent progression, arbitrary grade maximum number of modules in the Γ indication circuit.If ρ＜=L and Γ＜=C, (Fig. 9 for example, ρ=2, Γ=2, L=4, C=3; Figure 15, ρ=4, Γ=3, L=4, C=3), so in the one-level of circuit in each intercycle under calculated situation, mapping is direct.If ρ＞L or Γ＞C might organize together module and realize this circuit so by what is crossed over.Then, each group can realize in more than one intercycle before switching to next group.
When a design can not place on the one chip, it must be decomposed on several chips.If this decomposition is independently (that is, their do not share any common signal), so this decomposition can not cause any problem.
(level of ρ＞L), each grade has the situation of C module, and in the case, needs P/L chip and for synchronous their grade needed mechanism of counting circuit to consider ρ to be arranged combinational logic.Fig. 3 has shown " to next chip " and " from the front chip " 2 signals.These signals connect with the daisy chain form, thereby only at chip C I-1Be connected in chip C after arriving its maximum level I-1Chip C iJust begin its grade counter.If Γ＞C in this design, then the decomposition of chip chamber must be carried out logic copy.
As mentioned above, dynamic logic module 24 can be any logical organization of configuration again, and this structure can change repeatedly to realize different functions.Other possible logic module realizes comprising: the look-up table that (1) k-input and m-export, here k and m are integers, (2) interconnection of a lot of look-up tables, each has 1 or more output, and has input variation or similar number, (3) traffic pilot of logic-based module, (4) and have by read/write memory able to programme position control with or 2 grades of input with logic plane and its distortion, (5) use the heterogeneous dynamic logic module of a combinational logic realization.
Dynamically interconnection array 26 also has a large amount of may changing, and this variation can show general structure and two aspects of actual realization thereof.Following description will be described another realization in detail.
Can realize each point of crossing of cross bar switch with a transistor.Such as, a transistorized source electrode can be connected to from buffer array 30 or from an output line of logic kernel 22.This transistor drain can be connected to a suitable dynamic logic module 24.When a signal sent a given dynamic logic module to, L-cross bar switch controller 42 or B-cross bar switch controller 60 also can be used to provide a gate signal then.
Another method that realizes cross bar structure of the present invention is to use shift register.There is the storer of L position each point of crossing of this cross bar switch, and every grade is used one.These potential energies are arranged with the form of shift register, move 1 so the variation of level just means.The weak point of this realization is that will have to be shifted from the beginning to the end in whole L positions before returning the 1st grade, therefore can realize that 1 grade circuit is only arranged, and 1 is the aliquot of L here.One is better designed is that the L line storage is arranged, and every row is made of the storer that is positioned at whole point of crossing, and by grade row that the counter selection is used.
This cross bar structure also can use traffic pilot to realize.For example, the every row to cross bar switch can use a traffic pilot.The input of traffic pilot can be from the signal of buffer array 30 with from the signal of dynamic logic kernel 22.Output from each traffic pilot will be coupled to a dynamic logic module 22.L-Switch Controller 42 or B-Switch Controller 60 will be used to each traffic pilot to produce suitable selection signal.
Because (MC+B) KC point of crossing arranged in the L-cross bar switch, so will need (MC+B) KCL bank bit.Yet each of a logic module k-input is identical, and it and a signal are had nothing to do to which by assignment.In other words, (MC+B) individual signal only need be connected in K of each dynamic logic module 24 input one.This means that the k position can be reduced to every signal log 2The k position reduces to log with whole figure place 2KCL (MC+B).Yet this will guarantee that every grade has a code translator.Recognize that preferably the input in each dynamic logic module 24 needs one (MC+B) traffic pilot to k, rather than one (MC+B) is to the cross bar switch of K.One (MC+B) needs log to 1 traffic pilot 2(MC+B) an individual selection wire and K traffic pilot.Each selection wire needs 1 every grade, therefore, needs KCLlog 2(MC+B) position and KC (MC+B) code translator to 1.If KCLlog 2(MC+B)+and KC (MC+B) δ＜KCL (MC+B), this will have higher area efficiency, and δ is the position equivalence value of a code translator and door here.Because dynamic logic module 24 and interconnection all need code translator, so might share code translator.This will require to place extra latch in the output of dynamic logic module.
Connect the further reduction that can obtain the point of crossing number by hardwired.Each dynamic logic module can have a hardwired that is connected to K dynamic logic module, and each logic module will have the input of K dynamic logic module, it is desirable to make these modules adjacent with it.This is containing this cross bar switch (in this case or traffic pilot,) can be reduced to the cross bar switch of (MC-K+B) KC point of crossing, and, KC other 2-input multiplexer (one of each input) will be arranged because KCL auxiliary selection position arranged.The number of the fan-out point that this interconnect scheme can be exported the dynamic logic module reduces to (MC-K) K+K, rather than former KC.
By recognizing that whole dynamic logic module inputs are of equal value, just can adopt dissimilar interconnection strategies.Therefore, according to the contactor term, in input, interconnection box is one (MC+B) hub (concentrator) to K.In other words, necessary any K the signal of selecting in (MC+B) individual signal.The cross bar switch of these available 2 grades of sparse connection is finished.Known that this is technically as the binomial hub.The major advantage of using this interconnection strategies is to reduce all to intersect to count, and the result has reduced the figure place that is used to store.Its shortcoming, this signal have to pass through 2 point of crossing in the mode of series connection now.This may increase the delay of interconnection.
Other method will determine that the path is considered as " a duplicating " function.For example, consider a dynamic logic module (DLM) input.It can be connected to from (MC+B) individual signal of prime any one.It is the value that its value should be changed to one of (MC+B) individual signal.This is equivalent to a memory read operation, and the storer here is made of (MC+B) position, must read switch and export up for one in them.Therefore, available pre-charge circuit of this selection and sensor amplifier are finished.Be somebody's turn to do row of the corresponding memory of (MC+B) individual signal, one of unit selecting transistor is selected by code translator or local storage position.Advantage aspect silicon area and the speed two is arranged in the realization of using this type.If need one directly to connect between the switch input and output, so with will need the transistorized situation of large-scale transmission opposite, this unit selecting transistor, size is minimum.And utilize sensor amplifier, read operation can be carried out fast.Further, can replace mutually the precharge time of storer with the dynamic logic module time of tabling look-up, thereby can further shorten interconnect delay.This means that interconnect delay will postpone to be in same magnitude with logic module, even can be littler.
In another embodiment, can suppose to have C, each has the dynamic logic module 24 of K input and 1 output.If the dynamic logic module is divided into the K class, every class has C/K module.A module in the j class is connected to j the input (rather than to each input) of each dynamic logic module, j=1 wherein ..., k.This will be reduced the number of point of crossing and memory bit by the factor of a k.This might combine the one or more scheme of front the dynamic interconnection array 26 that develops into a mixing.
In a word, will see that an improvement structure that is used for a field programmable logic device emerges.Dynamic change logic kernel of the present invention and interconnected array have made things convenient for sharing of silicon resource, and because the layout of circuit and the simple and clear implementation procedure of simplifying circuit in path.Another benefit related to the present invention be improved timing performance and can accurately predicting the associated benefits of performance regularly.
For illustrated example and purpose of description, specific embodiments of the present invention has been introduced in the front.They are not limit or limit disclosed precise forms, according to top explanation, obviously a lot of corrections and variation can be arranged.For principle of the present invention and their practical application are described better, thereby select and described the various embodiment that these embodiment can make those skilled in the art go to utilize the present invention best and have various modifications, be intended to be applicable to specific use.Scope of the present invention is determined by following claim and equivalent thereof.

Claims (16)

1.一个现场可编程逻辑设备，其包括：1. A field programmable logic device comprising: 一个动态逻辑内核，它包括在一个输入信号集上执行第一逻辑操作以产生多个内部信号的装置，以及在一个选择的内部信号集上执行第二个操作的装置，所说的初始逻辑操作对应于一个电路的第一个逻辑级，所说的第二个逻辑操作对应于电路的第二个逻辑级；和A dynamic logic core comprising means for performing a first logical operation on a set of input signals to generate a plurality of internal signals, and means for performing a second operation on a selected set of internal signals, said initial logical operation corresponding to a first logic level of a circuit, said second logic operation corresponding to a second logic level of the circuit; and 一个动态互连阵列，它和所说的动态逻辑内核相耦合，所说的动态互连阵列包括：a dynamic interconnect array coupled to said dynamic logic core, said dynamic interconnect array comprising: 为了识别从所说的多个内部信号来的所说被选内部信号的装置，和means for identifying said selected internal signal from said plurality of internal signals, and 为了将所说的被选内部信号送至所说的动态逻辑内核的装置。means for sending said selected internal signal to said dynamic logic core. 2.根据权利要求1的现场可编程逻辑设备，其中所说的动态互连阵列进一步包含：2. The field programmable logic device according to claim 1, wherein said dynamic interconnection array further comprises: 用于缓冲一个所说的输入信号集以产生一个相应的缓冲的信号集的装置，以及所说的缓冲的信号形成所说的内部信号的一部分。means for buffering a set of said input signals to generate a corresponding set of buffered signals, and said buffered signal forms part of said internal signal. 3.根据权利要求2的现场可编程逻辑设备，其中所说的缓冲装置包括一个用于缓冲所说输入信号的缓冲器交叉开关互连结构。3. The field programmable logic device of claim 2, wherein said buffering means includes a buffer crossbar interconnect structure for buffering said input signal. 4.根据权利要求3的现场可编程设备，其中所说的缓冲装置包括一个耦合至所说的缓冲器交叉开关互连结构的缓冲器交叉开关控制器，所说的缓冲器交叉开关控制器执行一个逻辑命令集以选择所说的缓冲的信号。4. The field programmable device according to claim 3, wherein said buffer means includes a buffer crossbar controller coupled to said buffer crossbar interconnect structure, said buffer crossbar controller performing A set of logic commands to select said buffered signal. 5.根据权利要求2的现场可编程逻辑设备，进一步包括向所说的动态互连阵列引导所说的输入信号和所说的缓冲的信号的装置。5. The field programmable logic device of claim 2, further comprising means for directing said input signal and said buffered signal to said dynamic interconnect array. 6.根据权利要求5的现场可编程设备，其中所说的引导装置包括一个用于选择所说的输入信号和所说缓冲的信号的输入/缓冲器控制器。6. The field programmable device of claim 5, wherein said directing means includes an input/buffer controller for selecting said input signal and said buffered signal. 7.根据权利要求1的现场可编程逻辑设备，其中所说的动态互连阵列的所说的选定路径的装置包括用于给所说的被选内部信号选定路径的一个逻辑交叉开关结构。7. The field programmable logic device according to claim 1, wherein said means for selecting said routing of said dynamically interconnected array comprises a logic crossbar structure for routing said selected internal signal . 8.根据权利要求8的现场可编程逻辑设备，其中所说的动态互连阵列的所说的识别装置包含一个执行一逻辑命令集以识别所说的被选内部信号的逻辑交叉开关控制器。8. The field programmable logic device of claim 8, wherein said identifying means of said dynamic interconnect array comprises a logic crossbar controller executing a set of logic commands to identify said selected internal signals. 9.根据权利要求1的现场可编程逻辑设备，其中所说的动态逻辑内核是一个查找表，所说的第一个逻辑操作对应于所说的查找表中的第一个值集合，所说的第二个逻辑操作对应于在所说的查找表中的第二个值集合。9. The field programmable logic device according to claim 1, wherein said dynamic logic core is a look-up table, said first logic operation corresponds to the first set of values in said look-up table, said The second logical operation of corresponds to the second set of values in said lookup table. 10.根据权利要求1的现场可编程逻辑设备，其中动态逻辑内核包括一个用于选择所说的第一个逻辑操作和所说的第二个逻辑操作的计数器。10. The field programmable logic device of claim 1, wherein the dynamic logic core includes a counter for selecting said first logic operation and said second logic operation. 11.在一个现场可编程逻辑设备上实现一个电路的一种方法，所说的方法由下列步骤构成：11. A method of implementing a circuit on a field programmable logic device, said method consisting of the steps of: (A)接收一个输入信号集；(A) receiving an input signal set; (B)当所说的被选信号在一相继的逻辑级中需要时，缓冲自所说的输入信号中所选信号，所说的缓冲步骤产生所缓冲的信号；(B) buffering selected signals from said input signals when said selected signals are required in a successive logic stage, said buffering step producing buffered signals; (C)执行一个在所说的输入信号上的一组初级逻辑，以产生一个输入信号集；(C) performing a set of primary logic on said input signals to generate a set of input signals; (D)从所说的缓冲信号和所说的内部信号中选取一个中间信号集；(D) selecting an intermediate signal set from said buffered signal and said internal signal; (E)当所说的被指定的信号为相继的一个逻辑级所需要时，缓冲自所说的中间信号来的指定信号；(E) buffering assigned signals from said intermediate signals when said assigned signals are required by a successive logic stage; (F)在所说的中间信号上执行一个预选的逻辑集，以产生一个新的中间信号集；(F) executing a preselected set of logic on said intermediate signals to produce a new set of intermediate signals; (G)重复步骤(D)到(F)直到一个预定的逻辑集被执行，所说的预定的逻辑集对应一个电路中的多个逻辑级。(G) Repeating steps (D) through (F) until a predetermined set of logic is implemented, said predetermined set of logic corresponding to a plurality of logic stages in a circuit. 12.根据权利要求11的方法，其中所说执行集的所说的预选逻辑集是通过定义在所说的多个逻辑级内的一个逻辑级来指定的。12. The method of claim 11, wherein said preselected logical set of said execution sets is specified by defining a logical level within said plurality of logical levels. 13.根据权利要求12的方法，其中所说定义步骤的所说逻辑级在每个执行步骤后递增。13. The method of claim 12, wherein said logical level of said defining step is incremented after each executing step. 14.设计一个现场可编程逻辑设备的方法，所说的方法由下列步骤组成：14. A method of designing a field programmable logic device, said method consisting of the steps of: 接受一个要在所说的现场可编程逻辑设备内实现的一个电路的描述；accepts a description of a circuit to be implemented in said field programmable logic device; 标识所说电路内的逻辑级；Identify logic levels within said circuit; 为了执行对应于所说电路内每个所说逻辑级的逻辑创建逻辑表；creating a logic table for implementing logic corresponding to each of said logic levels within said circuit; 产生输入/缓冲逻辑以选择输入值和缓冲值，这些值将施加于所说的逻辑表；generating input/buffer logic to select input and buffer values to be applied to said logic table; 产生缓冲器控制器逻辑以使能在第一个逻辑级中存储且在相继的逻辑级中必须使用的缓冲值；generating buffer controller logic to enable buffered values stored in a first logic stage and must be used in subsequent logic stages; 定义逻辑控制器逻辑以使能存储、接着要用于所说逻辑表的输入值和缓冲值。Logic controller logic is defined to enable storage of input values and buffer values to be subsequently used in said logic tables. 15.根据权利要求14的方法，进一步包含下载所说的输入/缓冲逻辑、所说的缓冲器控制器逻辑、和所说的逻辑控制器逻辑至一个非易失存贮设备的步骤。15. The method of claim 14, further comprising the step of downloading said input/buffer logic, said buffer controller logic, and said logic controller logic to a non-volatile storage device. 16.根据权利要求15的方法，进一步包含的步骤是将所说的非易失存贮设备和一个包括一个输入/缓冲控制器、一个缓冲器控制器和一个逻辑控制器的现场可编程逻辑设备耦合起来。16. The method according to claim 15, further comprising the step of combining said non-volatile memory device with a field programmable logic device comprising an input/buffer controller, a buffer controller and a logic controller Coupled up.
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US5596743A (en) 1997-01-21
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