JPS6187194A - memory circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to RAM (R4m11, tm Ac b
aa -s M<tnt 4J= ), and particularly relates to a multi-functional memory circuit suitable for storing stored data act-M rlL71-YhL-.

[Background of the invention]

The prior art will be explained using image processing as shown in FIGS. 1 and 2 as an example. In Figure 1, Ml is CB'l'
(CaiJLtel<FunT-Image processing area 9A corresponds one-to-one with the screen, M2 is the storage area where the image data to be combined is stored, and FC is the storage area where the data of image area M1 and the data of storage area 91M2 are stored. M# d for performing synthesis
L71 function. In addition, in FIG.
2 is a processing step for R4acl data from storage area M2, 8, 6 is a number, 4ad, l, and image area M1.
and a processing step for synthesizing the data of the storage area M2,
Step 84 is a W4L14 processing step in which the composite data obtained in step S3 is sent to the image processing unit 91M1.

In the example of image processing shown in Figure 1, for simple compositing,
The processing steps in FIG. 2 are logical sum functions.

On the other hand, the amount of data in the target image area M1 is usually 1
It has a large capacity of 00 to several MBνχ. Therefore, in the series of processing shown in FIG. 2, the number of repetitions is on the order of 106 even when data is processed in units of Byi4.

For this reason, conventional methods have the following drawbacks.

In other words, (Re) As shown in Figure 2, most of the processing in this process is occupied by the bus cycle (s 1.828S4) that uses the path. increases.

(2) In addition, the actual processing time is long due to slow paths or overheads such as path occupancy control.

(3) Furthermore, in the column in Figure 2, the number of static steps and steps is small at 4 steps and steps, but because there are so many data companies to handle, the number of dynamic steps and steps is enormous. , the processing time is large.

In addition, the memory circuit that processes this cypress is related to the Tokukosho! No. 59-26031 is mentioned.

[Purpose of the invention]

The object of the present invention is to eliminate the drawbacks of the prior art mentioned above,
The object of the present invention is to provide a memory circuit with reduced path load and processing time.

[Summary of the invention]

In order to achieve the above object, the present invention is a storage circuit having the following two functions, for example, in order to speed up the above-described image compositing processing (data redirection processing).

(2) A process of modifying the data already stored in the memory element and re-asserting the modified data to the memory element at the same address.

4) A general external data write processing function to a storage element.

Further, in the present invention, a memory circuit having the above-mentioned two functions is realized by paying attention to the following points, and will be explained using FIG. 3. Fang 3 figure is D-几AM (Dy?La
mjc-Raxelam At, c, oi Nkmth
y) shows the data writing process, in which the D-RAM was 9-dry nite.

In Figure 3, ADH is an address from the outside, WE is a ride request from the outside, and these two signals (A
DR, WR) are given by a microprocessor, for example. Also, RAS is the row atrostrope,
CAS is a column address strobe, A is an address signal in which column and row addresses are generated in a time-division manner, Wli is a write enable, DO is read data, 2 is data from the outside (microprocessor, 9-), and these signals Except for 2, these are control signals generated from, for example, a DRAM controller.

That is, (1) As shown in Fig. 3, in a general VC9-dry write cycle, one memory access starts with a read cycle ([F]), and a write cycle (■) by write enable WEK is executed. Ru.

(1) Therefore, between the read cycle (■) and the write cycle (■), a section (■) in which the 9-de data DO and the external gator 2 are present simultaneously appears.

(II) Let this interval (■) be the modified interval, and (1v)
Furthermore, it is possible to perform this correction control using an external gator ZK.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 5 to 11. FIG. 3 is a time chart of the KD-RAM as described above. Fig. 4 is a diagram showing one embodiment of the present invention, Fig. 5 is an explanatory diagram of the operating principle of the embodiment shown in Fig. 4, and Fig. 6 is an illustration of the operating principle shown in Fig. 5. A diagram showing an example of a realized circuit and an off-line diagram are diagrams for explaining details of the operation of FIG. 6.

In FIG. 4, 1 is a control circuit, 2 is a memory element, and 3 is a D
-RAM controller, X, Y are external data, Z
is write data to the storage element, DO is 9 from the storage element
-Dodata, A, CAS.

RAS, WE, ADH, and WE are the same types of signals as in FIG. 3 described above. Note that the external data 2 shown in FIG. 3 is directly converted into the write data ZK to the storage element 2 via the control circuit 1 (FIG. 4).

As shown in FIG. 4, in the present invention, in the control circuit 1, 9
- Control and modify the stored data DO using external gates X and Y and input it into the storage element 2Vc4. This control operation is shown in FIG. In FIG. 5, mode I is a mode in which external data Y is used as write data Z, and mode I is a mode in which 9-dogta DO is used as write data 2. As shown in FIG. 5, the read data DO of the storage element 2 is corrected and committed (mode H) by external data X and Y, that is, by external control.
Alternatively, it is possible to control two modes of external gator Y commitment processing (mode I). These two modes are controlled by (1) specifying mode I and summer using external data X, and (1) specifying (correcting) non-inversion or inversion of 9-code data DO in mode INK using external data.

FIG. 6 shows a concrete example of the above-mentioned operation and a circuit that realizes it. Further, the detailed idX value of the operation is shown in the off-line diagram. 6th
As shown in the Figure, Off Diagram Button, the present invention is implemented by two logical combination buttons.

Moreover, the above operation is performed at 1 memo 9f as shown in FIG.
KN rows can be completed during one cycle. On the other hand, O6 (
The circuit shown in 8) is expressed by the following logical formula (ri).

z=x−y+x−(y■Do) ---1--(1) Also, the values obtained from externally controllable data 1. For example, by allocating and organizing the bus data D↓ and its inverted data ヱ from the microprocessor, a binary logic operation result as shown in Fig. 8 can be obtained.This can be made into an actual circuit and combined with Fig. 4. I'll show you what I've done in Figure 9.
o and t are 4-input selectors, So and Sl are selectors SE
LO- input selection signal, 82.83 is selector SEL
The input selection signal INV of 1 is an inverting element.

Hereinafter, an operation example will be specifically explained using the first factor, the eighth factor, the ninth factor, and FIG. 1o.

As shown in the eighth factor, the input selection signals So and S1 are the selection signals of the selector 5ELo, and this signal so.

S11, ζ determines the data XQ value. Data Y is determined by the same type input selection signals 82 and 85.

As mentioned above, the data X and Y are obtained by using the signal gol', the signal 61aj, the bus gate Djima and its inverted data, and the interspecies input selection signals So, 81, 82 shown in the ninth factor. .83 K, each selector S E
One of the above four signals is selected for each of L o and 1. The eighth factor is the input selection signal So, S1.82
．． 85 and <v number 8ELO, 1f) output data X
, Y, and furthermore, the operation of the control circuit 1 (which can be expressed by the equation 0) (value of the write data 2) is shown.For example, the image processing (08 calculation; Ca
, aal ), the input selection signal 80.81 = (1
1) By setting I 82.5 electric (10), data X,
For Y, X = D) and Y = DL are selected, respectively. When the values of these data X and Y are substituted into equation (1) representing the operation of the control circuit 1, 2= DA + DI O
It can be seen that the R operation can be executed. Therefore, the original fJ[
According to the image processing in Fig. 1, as shown in Fig. 10, the input selection signal So, 1, 2.3 is specified in the first step (
Ii"*?LcJL?z specification), and then convert the image data you want to combine from
, the image processing shown in FIG. 1 can be executed by simply performing the W4b 24 operation on the imager YA M1. Furthermore, the present invention allows the device shown in the eighth factor to perform various logical functions. Therefore, as shown in FIG. 11, for example, it is possible to easily draw a mask cursor that moves arbitrarily. As shown in FIG. 11, even if the cursor (M2) overlaps with the image in M1, the cursor must be displayed, so Fμ? EOR as L6χ↓t%
functionality is required. In other words, with this cursor indication,
Input selection signal 80.1=(01)*S2,3=(
10) The processing shown in FIG. 10 can be performed in the same way as in the case of image synthesis (FIG. 1) described above. Therefore, the input selection signals So, 1, 2 . By changing the value of s, various logical functions such as those shown in the 8th factor can be easily executed, and furthermore, 9-code, modify, and write with the memory element 2 can be executed with just W+L and t44. can.

In this way, by adopting a configuration like the ninth factor, the data D from the microprocessor f and the memory element 20 read gate f
) t and pdtdLfν can be used to perform the binary logical operation shown in the eighth factor. Note that the binary logic operation is specified by the input selection No. 1g SO to Ss K.

As described above, using the embodiment, FIG.
The conventional image composition process using FIG. 2 can be simplified as shown in FIG. 10.

In addition, the above-mentioned embodiment has three functions shown in the ninth factor, namely, a storage section made up of the storage element 2, a control section made up of the control circuit 1, and a selector SRL D,1.
It is divided into a selector section consisting of. However, the functions realized by the combination K of the above control and selector section are as follows.
This is the binary logical operation function shown in the 8th factor), and this function is
This can easily be achieved by other means as well.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(1) When processing as shown in the first factor is carried out, as shown in FIG. 10, the number of memo cycles can be reduced, thereby eliminating the drawbacks of the conventional method described above.

(2) Furthermore, since the microprocessor can execute three processes, 9-code, modify, and write, with a 1@J write cycle, it is possible to further speed up the processing time.

(3) Compared to the memory element group, the proportion of the entire circuit according to the present invention is small, so it can be easily implemented as an ICLSI.

(4) 64K x 4 bit D currently on the market
-Is most of the RAM one PL? L is N# - (:tx
Since n<clLpn, up to the point shown in FIG. 10, that is, even when the memory element 2 and the control circuit 1 are integrated into LSI, the number of pins does not increase, and it is extremely advantageous to implement LSI.

[Brief explanation of drawings]

Fig. 1 is a diagram for explaining the conventional technology using an example of image processing, Fig. 2 is a flowchart of Fig. 1, and Fig. 5 is a D-R
4 is a block diagram showing an embodiment of the present invention, FIG. 5 is a diagram for explaining the operating principle of FIG. 4, and FIG. 6 is a diagram for explaining the operating principle of FIG. 5. A diagram showing an example of a circuit that realizes the operating principle, an OFF diagram is a diagram for explaining the operation of FIG. 6, FIG. 8 is a diagram showing the relationship between the input selection signal and the selector output, and FIG. FIG. 10 is a flowchart when the present invention is applied to image processing, and FIG. 11 is a diagram for explaining another application example of the present invention. 1... Control circuit, 2... Memory element, Fig. 1

Claims (1)

[Scope of Claims] 1. In a memory element in which data can be read, written, and stored arbitrarily, the first data is transferred to the memory from external first data and second data within the memory element. A first mode in which the second data is stored in the storage element, a second mode in which the second data is stored in the storage element again, and a third mode in which inverted data of the second data is stored in the storage element again. A memory circuit characterized by being provided with a control circuit for acquiring data. 2. In claim 1, the control circuit selects the three modes by adding a third data input from the outside, and selects the first mode and the other second and third modes. The distinction between the two is controlled by the fifth data, and the second
. A storage circuit, wherein designation of the third mode is controlled by the first data. 3. In claim 2, two selectors are provided for selecting one data from a plurality of input data, and
1. A storage circuit, wherein one selector output of the two selectors is the first data, and the other selector output is the third data, and each of the two selectors can be selectively controlled independently. 4. In claim 3, the number of inputs of the two selectors is 4, and each of the 4 inputs is
A fixed logic "0", a fixed logic "1", external data whose logic arbitrarily changes to "0" or "1", and inverted data of the external data are used as inputs, and the above-mentioned assigned 4
A memory circuit characterized in that two input data are independently selected and controlled by the two selectors and combined. 5. A memory circuit according to claim 2, wherein the memory element and the control circuit are arbitrarily arranged to have an arbitrary data length (number of bits) or an arbitrary data capacity. 6. The memory circuit according to claim 5, wherein the arbitrarily arranged memory element group and the control circuit group are incorporated into the same LSI. 7. In claim 4, the storage element, the control circuit, and the two selectors are arranged in an arbitrary data table (
A memory circuit characterized in that the number of bits) or any data capacity can be arbitrarily arranged. 8. The memory circuit according to claim 7, wherein the arbitrarily arranged memory element group, the control circuit group, and the two selector groups are incorporated into the same LSI. 9. A memory circuit according to claim 2 or 3, comprising means having a function equivalent to a combination of the control circuit and the two selectors. 10. Claim 9 provides that the means has an arbitrary data length (number of bits) or an arbitrary data capacity;
A memory circuit characterized by being arbitrarily arranged. 11. A memory circuit according to claim 10, wherein the means group is incorporated into the same LSI.