Xie et al., 1995 - Google Patents
An SBus monitor boardXie et al., 1995
View PDF- Document ID
- 15553156395366891684
- Author
- Xie H
- Forward K
- Adams K
- Leask D
- Publication year
- Publication venue
- Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
External Links
Snippet
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. It is difficult to attach general-purpose logic analysers and in-circuit emulators to a multiple pin …
- 238000000034 method 0 abstract description 10
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3656—Software debugging using additional hardware using a specific debug interface
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
- G06F11/364—Software debugging by tracing the execution of the program tracing values on a bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/348—Circuit details, i.e. tracer hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/25—Testing of logic operation, e.g. by logic analysers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuit
- G01R31/31903—Tester hardware, i.e. output processing circuit tester configuration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6038686A (en) | System for providing real-time code coverage | |
| US6247147B1 (en) | Enhanced embedded logic analyzer | |
| US6286114B1 (en) | Enhanced embedded logic analyzer | |
| US6961872B2 (en) | Microcomputer and debugging system | |
| JP6557220B2 (en) | Programmable interface-based verification and debugging | |
| US7080283B1 (en) | Simultaneous real-time trace and debug for multiple processing core systems on a chip | |
| US6523136B1 (en) | Semiconductor integrated circuit device with processor | |
| US6829751B1 (en) | Diagnostic architecture using FPGA core in system on a chip design | |
| EP3369015B1 (en) | Methods and circuits for debugging circuit designs | |
| CN202267954U (en) | Bus monitoring and debugging control device | |
| CN117076337B (en) | Data transmission method and device, electronic equipment and readable storage medium | |
| US20040103336A1 (en) | Apparatus for alignment of data collected from multiple pipe stages with heterogeneous retention policies in an unprotected pipeline | |
| US8769357B1 (en) | System and method for evaluation of a field programmable gate array (FPGA) | |
| US7360117B1 (en) | In-circuit emulation debugger and method of operation thereof | |
| US8103496B1 (en) | Breakpoint control in an in-circuit emulation system | |
| EP1233341B1 (en) | Embedded logic analyser | |
| Xie et al. | An SBus monitor board | |
| CN115292760A (en) | Chip verification system, method and computer readable storage medium | |
| Kang et al. | A deep research on the chip verification platform based on network | |
| JP2642664B2 (en) | Emulator and multi-emulation break method | |
| JP2004348635A (en) | Method for developing program | |
| Xie et al. | An SBus Multi Tracer and its applications | |
| Conrad et al. | The Integration Of Microcomputer Hardware And Software Development Tools And Techniques | |
| Wilburn et al. | Step-27 development station | |
| Savvopoulos et al. | A Versatile Instrument for Analyzing and Testing the Interfaces of Peripheral Devices |