CN101963897B - Apparatus and method for dual data path processing - Google Patents

Abstract

A computer processor having control and data processing capabilities, including a decode unit for decoding instructions. The data processing device includes a first data execution path and a second data execution path, the first data execution path includes fixed operators, the second data execution path includes at least configurable operators, and the configurable operators have multiple pre-defined configurations, at least some of which are selectable via opcode portions of data processing instructions. a decoding unit operable to detect whether a data processing instruction defines a fixed data processing operation or a configurable data processing operation, the decoding unit causing the computer system to provide data for processing to the said fixed data processing instruction upon detection of said fixed data processing instruction A first data execution path is provided to the configurable data execution path upon detection of a configurable data processing instruction.

Description

Apparatus and method for dual data path processing

This application is a divisional application of a Chinese patent application with the same name filed on March 22, 2005 with application number 200580010665.X (PCT/GB2005/001073). the

technical field

The invention relates to a computer processor, a method of operating the computer processor, and a computer program product comprising an instruction set for a computer. the

Background technique

In order to increase the speed of computer processors, prior art architectures have used dual execution paths for executing instructions. Dual execution path processors may operate according to the Single Instruction Multiple Data (SIMD) principle, exploiting parallelism of operations for increasing processor speed. the

However, despite the use of dual execution paths and SIMD processing, there is a continuing need to increase processor speed. A typical dual execution path processor uses two roughly similar paths, so each path processes control code and data path code. While known processors support a combination of 32-bit standard encoding and 16-bit "dense" encoding, this scheme suffers from a number of disadvantages, including a lack of semantic content in the few bits available in 16-bit formats. the

Furthermore, conventional general-purpose digital signal processors cannot be matched to application-specific algorithms for many purposes, including performing specialized operations such as convolution, fast Fourier transform, Trellis/Viterbi coding, correlation, finite impulse response filtering, and others. the

Contents of the invention

In one embodiment according to the invention, a computer processor having control and data processing capabilities is provided. The computer processor comprises: a decoding unit for decoding instructions; a data processing device comprising a first data execution path comprising fixed operators and a second data execution path including at least configurable operators having a plurality of predefined configurations, at least some of which are selectable via an opcode portion of a data processing instruction; wherein the decode unit is operable to detect data Whether a processing instruction defines a fixed data processing operation or a configurable data processing operation, the decode unit causes the computer system to provide data for processing to the first data execution path upon detection of the fixed data processing instruction, and upon detection of the fixed data processing instruction, When a configurable data processing instruction is detected, it is provided to the configurable data execution path. the

In another related embodiment, the decode unit is capable of decoding a stream of instruction packets from the memory, each packet including a plurality of instructions. The decoding unit is also operable to detect whether an instruction packet contains a data processing instruction. The configurable operators are configurable at the level of multi-bit values, including multi-bit values having four or more bits, or at the level of words. According to the Single Instruction Multiple Data principle, multiple fixed operators of the first data execution path may be arranged to perform multiple fixed operations in independent lanes. Likewise, multiple configurable operators of the second data execution path may be arranged to perform multiple operations in different lanes according to the Single Instruction Multiple Data principle. the

In another related embodiment, the configurable operator of the second execution path may be arranged to receive configuration information determining characteristics of the operations performed. This information may be received from fields of instructions defining configurable data processing operations. The configurable operator of the second execution path may be arranged to receive configurable information comprising information controlling related interconnectivity. The computer processor further includes a control map associated with the configurable operator of the second data execution path, the control map operable to receive at least one configuration bit from a configurable data processing instruction, and to assign a configurable bit in response thereto. Configuration operators provide configuration information. The configuration information may determine characteristics of operation by said configurable operators; and control interconnectivity between two or more of said configurable operators. the

In another related embodiment, the configurable operators of the second execution path may be arranged to receive configuration information determining characteristics of operations to be performed, or to control interconnectivity, from sources other than configurable data processing instructions. configuration information. At least one configurable operator of the second data execution path is capable of executing data processing instructions with an execution depth greater than two computations before returning a result to a result store. The computer processor may comprise conversion means for receiving data processing operands from configurable data processing instructions and converting said data processing operands as appropriate for supply to one or more of said configurable operators. The computer processor may also include transformation means for receiving results from one or more of said configurable operators and transforming said results as appropriate for feeding to one or more of a result memory and a feedback loop . The computer processor also includes a plurality of control maps for mapping configuration bits received from the configurable data processing instructions to configuration information for providing configurable operators of the second data execution path. Likewise, the computer processor may comprise conversion means for receiving configuration information from the control map and converting the configuration information as appropriate for feeding to the configurable operators of the second data execution path. The computer processor may also include a configurable operator selected from one or more of: a multiply-accumulate operator; an arithmetic operator; a state operator; and a cross-path transcoder. Likewise, the computer processor may include a set of operators and instructions capable of performing one or more operations selected from: Fast Fourier Transform; Inverse Fast Fourier Transform; Viterbi encoding/decoding; Turbo encoding/decoding; and Finite impulse response calculations; and any other correlation or convolution. the

In another embodiment according to the present invention there is provided a method of operating a computer processor having control and data processing capabilities, the computer processor comprising a first data execution path and a second data execution path, the first The data execution path includes fixed operators, and the second data execution path includes configurable operators having a plurality of predefined configurations, at least some of which are operable via opcodes of the data processing instructions part to select. The method includes: decoding a plurality of instructions to detect whether at least one data processing instruction of the plurality of instructions defines a fixed data processing operation or a configurable data processing operation; causing a computer processor to process data for processing when the fixed data processing operation is detected providing instructions to said first data execution path and upon detection of a configurable data processing instruction to said configurable data execution path; and outputting a result. the

In another embodiment according to the present invention there is provided a computer program product comprising program code means for causing a computer processor to perform the following steps, wherein the computer processor comprises a first data execution path and a second data execution path, the first data execution path includes fixed operators, the second data execution path includes configurable operators, the configurable operators have a plurality of predefined configurations, in which At least some of the data processing instructions are selectable through the opcode portion of the data processing instructions, namely: decoding a plurality of instructions to detect whether at least one data processing instruction of the plurality of instructions defines a fixed data processing operation or a configurable data processing operation; causes the computer to process providing data for processing to the first data execution path upon detection of a fixed data processing instruction and to the configurable data execution path upon detection of a configurable data processing instruction; and outputting a result. the

In another embodiment according to the present invention there is provided a set of data processing instructions comprising a first plurality of instructions having a field indicating a fixed type of data processing operation and a second plurality of instructions, The second plurality of instructions has a field indicating a configurable type of data processing operation. the

In another embodiment according to the invention there is provided a computer processor comprising a data execution path of configurable operators, wherein the configurable operators comprise a plurality of predefined groups of operator configurations, each group consisting of Operators for individual operator classes. Operator classes may include classes selected from one or more of: multiply-accumulate operators; arithmetic operators; state operators; and escapers. Connections between operators selected from within each predefined group of operator configurations can be configured through opcode portions within instructions executed by a computer processor. Likewise, connections between operators selected from more than one predefined group of operator configurations can be configured through opcode portions within instructions executed by a computer processor. the

The present invention provides a computer processor comprising a decoding unit for decoding instruction packets from a memory, each instruction packet comprising a plurality of instructions; a processing channel comprising a plurality of functional units and operable to perform control processing operations; wherein the The decode unit is operable to receive an instruction packet having a bit length of 64 bits, and is operable to use an identification bit in the instruction packet to detect whether the instruction packet defines three instruction packets each having a bit length of 21 bits a control instruction, and wherein when the decoding unit detects that the instruction packet includes three such control instructions, the control instruction is provided to the processing channel for appearing in the The sequence in the instruction packet is executed. the

The present invention also provides a method of operating a computer processor comprising a processing channel and capable of performing control processing operations having a plurality of functional units, the method comprising (a) receiving a sequence of instruction packets from a memory, the instruction Each of the packets includes a plurality of instructions defining operations; (b) each instruction packet is decoded in turn by using the identification bits in the instruction packet to determine whether the instruction packet defines three each a control instruction having a bit length of 21 bits, and wherein when the decoding unit detects that the instruction packet includes three such control instructions, providing the control instruction to the processing channel for following the three such control instructions executed in the order in which they appear in the instruction packet. the

Other advantages and novel features of the present invention will be set forth in part in the following description, and in part will be apparent to those skilled in the art from the following examination and drawings; or can be learned by practicing the present invention . the

Description of drawings

For a better understanding of the invention, and to illustrate how it may likewise be implemented, reference will now be made, by way of example only, to the accompanying drawings, in which:

1 is a block diagram of an asymmetric dual execution path computer processor according to an embodiment of the invention;

Figure 2 represents an exemplary class of instructions for the processor of Figure 1 according to an embodiment of the invention; and

Fig. 3 is a schematic diagram representing components of a configurable deep execution unit according to an embodiment of the present invention;

Detailed ways

FIG. 1 is a block diagram of an asymmetric dual-path computer processor according to an embodiment of the present invention. The processor of FIG. 1 divides the processing of a single instruction stream 100 between two distinct hardware execution paths:

Control execution path 102 for processing control code, and data execution path 103 for processing data code. The data width, operators and other characteristics of the two execution paths 102, 103 differ according to the different characteristics of the control code and data path code. Typically, the control code supports fewer, narrower registers, is difficult to parallelize, is typically (but not exclusively) written in C code or another high-level language, and its code density is generally more important than its speed performance . In contrast, datapath code typically supports large files of wide registers, is highly parallelizable, is written in assembly language, and its performance is more important than its code density. In the processor of FIG. 1, two different execution paths 102 and 103 are dedicated to processing two different types of code, each side having its own architectural register file (such as control register file 104 and data register file 105), The difference is in register width and number; control registers have a narrower width in bits (in one example, 32 bits), while data registers have a wider width (in one example, 64 bits). The processor is asymmetric because the two execution paths of the registers perform different specialized functions and thus have different bit widths. the

In the processor of FIG. 1, instruction stream 100 consists of a sequence of instruction packets. Each instruction packet provided is decoded by an instruction decode unit 101, which separates control instructions from data instructions, as further described below. The control-execution path 102 handles control-flow operations for the instruction stream and manages the state registers of the machine with the branch unit 106, the execution unit 107, and the load-store unit 108, which in this embodiment is executed by the data Path 103 is shared. Only the control side of the processor needs to be visible to a compiler, such as a compiler for the C, C++, or Java languages, or another high-level language compiler. Within the control side, branch unit 106 and execution unit 107 operate in accordance with conventional processor designs known to those of ordinary skill in the art. the

In both the fixed execution unit 109 and the configurable depth execution unit 110, the data execution path 103 uses SIMD (Single Instruction Multiple Data) parallelism. As will be described further below, deep execution unit 110 can be configured to provide processing depth in addition to the width used by conventional SIMD processors in order to increase work per instruction. the

If the decoded instruction defines a control instruction, it is applied to the appropriate functional units (eg, branch unit 106, execution unit 107, and load/store unit 108) on the control execution path of the machine. If the decoded instruction defines an instruction with fixed or configurable data processing operations, it is fed to the data processing execution path. Within the data instruction portion of an instruction packet, designated bits indicate whether the instruction is a fixed or configurable data processing instruction, and in the case of a configurable instruction, additional designated bits define configuration information. Depending on the subtype of the data processing instruction being decoded, data is provided to a fixed or configurable execution subpath of the data processing path of the machine. the

Here, "configurable" denotes the ability to select an operator configuration from a number of predefined ("pseudo-static") operator configurations. A pseudo-static configuration of an operator is effective to cause the operator to (i) perform a particular type of operation or (ii) interconnect with related elements in a particular fashion or (iii) a combination of (i) and (ii) above. In fact, the selected pseudo-static configuration can determine the properties and interconnectivity of many operator elements at a time. It also controls the transformation configuration associated with the datapath. In a preferred embodiment, at least some of the plurality of pseudo-static operator configurations are selectable through the opcode portion of the data processing instruction, as further described below. Also according to embodiments herein, "configurable instructions" allow customized operations to be performed at the level of multi-bit values; for example at the level of four or more bit multi-bit values, or at the level of words. the

It should be noted that the control and data processing instructions, which are executed on their respective different sides of the machine, may define memory accesses (load/store) and basic arithmetic operations. Inputs/operands for control operations may be provided to/from the control register file 104 , while data/operands for data processing operations are provided to/from the register file 105 . the

According to an embodiment of the present invention, at least one input of each data processing operation may be a vector. In this regard, the configurable operators and/or transformation circuits of the configurable datapath may be considered configurable to perform vector operations utilizing the nature of the operations performed and/or the interconnectivity therebetween. For example, a 64-bit vector input to a data processing operation may include four 16-bit scalar operands. Here, a "vector" is a collection of scalar operands. Vector arithmetic can be performed on multiple scalar operands, and can include steering, shifting, and permutation of scalar elements. Not all operands of a vector operation need to be vectors; for example, a vector operation can have a scalar and at least one vector as input; and the output is either a scalar or a vector result. the

Here, "control instructions" include instructions dedicated to program flow and branching and address generation; but not data processing. "Data processing instructions" include instructions for logical operations or arithmetic operations for which at least one input is a vector. Data processing instructions may operate on multiple data instructions, such as in SIMD processing, or in processing wide, short vectors of data elements. The basic functions of the control instructions and data processing instructions described above do not overlap; however, the commonality is that both types of codes have logic and scalar arithmetic capabilities. the

FIG. 2 shows three types of instruction packets for the processor of FIG. 1 . Each type of instruction packet is 64 bits long. The instruction pack 211 is a 3-scalar type for dense control codes, and includes three 21-bit control instructions (c21). Instruction packets 212 and 213 are LIW (Long Instruction Word) type for parallel execution of datapath code. In this example, each instruction packet 212, 213 includes two instructions, but could include a different number if desired. The instruction packet 212 includes a 34-bit data instruction (d34) and a 28-bit memory instruction (m28); and is used to perform data-side arithmetic (d34 instruction) in parallel with a data-side load-store operation (m28 instruction). Memory class instructions (m28) can be read from, or written to, the control or data side of the processor using an address from the control side. Instruction packet 213 includes 34-bit data instructions (d34) and 21-bit control instructions (c21); and is used to execute data-side operations in parallel with control-side operations (c21 instructions) such as control-side arithmetic, branch, or load-store operations Arithmetic (d34 instruction). the

The instruction decode unit 101 of the embodiment of FIG. 1 uses the initial identification bits of each instruction packet, or some other designated identification bit at a predetermined bit position, for determining which type of packet is being decoded. For example, as shown in Figure 2, the initial bit "1" indicates that the instruction packet is a scalar control instruction type, with 3 control instructions; while the initial bits "01" and "00" indicate the instruction packets of types 212 and 213, in packet 212 There are data and memory instructions in or data and control instructions in packets 213 . Having decoded the initial bits of each instruction packet, the decoding unit 101 of FIG. 1 appropriately transfers the instructions of each packet to the control execution path 102 or the data execution path 103 according to the type of the instruction packet. the

In order to execute the instruction package of Fig. 2, the instruction decoding unit 101 of the processor of the embodiment of Fig. 1 obtains the program package sequentially from the memory; and the program package is executed sequentially. Within an instruction packet, the instructions of packet 211 are executed sequentially, wherein the least significant end 21 bit control instruction of a 64 bit word is executed first, then the next 21 bit control instruction, and then the most significant end 21 bit control instruction. Within instruction packets 212 and 213, instructions may be executed concurrently (in embodiments according to the invention, although this is not necessarily the case). Thus, in the program order of the processor of the embodiment of FIG. 1, the program packages are executed sequentially; but the instructions within the packages may be executed either sequentially (for package type 211) or simultaneously (for packages 212 and 213 ). In the following, the instruction packets of types 212 and 213 are referred to as MD and CD packets (respectively including a memory and a data instruction; and a control instruction and a data instruction). the

By using 21-bit control instructions, the embodiment of FIG. 1 overcomes many combinations of 32-bit standard encoding for data instructions and 16-bit "dense" encoding for control codes in processors with instructions of other lengths and in particular defects found in processors. In such dual 16/32-bit processors, due to the use of dual encoding for each instruction, or the use of two separate decoders with means for switching between encoding schemes by branching, fetching addresses, or other means redundancy. According to an embodiment of the present invention, this redundancy is eliminated by using a single 21-bit length for all control instructions. Furthermore, the use of 21-bit control instructions eliminates the drawbacks arising from insufficient semantic content in 16-bit "dense" encoding schemes. Processors using 16-bit schemes typically require some mix of design trade-offs due to insufficient semantic content, such as: use of two-operand destructive operations with corresponding code bloat for copying; A subset of the file has windowed access, where code bloats for overflow/fill or window pointer operations; or frequently reverses to 32-bit format, since not all operations can be done with the few opcode bits available in 16-bit format express. In an embodiment of the present invention, these drawbacks are mitigated by using 21-bit control instructions. the

According to embodiments of the present invention, a large number of instructions may be used. For example, an instruction signature can be any of the following, where C format, M format, and D format represent control, memory access, and data formats, respectively:

instruction signature parameters used instr The command has no parameters C format only instr dst Directives have a single purpose parameter C format only instr src0 Directives have a single source parameter C or D format only instr dst,src0 Directives have a single purpose, single source parameter D and M format instructions instr dst, src0, src1 Directives have a single destination parameter and two source parameters C, D and M format instructions

Equally, according to one embodiment of the present invention, C format instruction all provides SISD (single instruction single data) operation, and M format and D format instruction provide SISD or SIMD operation. For example, control instructions may provide general arithmetic, comparison, and logic instructions; control flow instructions; memory load and store instructions; and others. Data instructions may provide general arithmetic, shift, logic, and compare instructions; shuffle, sort, byte extension, and permutation instructions; linear feedback offset register instructions; and Directives defined by the user. Memory instructions may provide memory loads and stores; copy selected data registers to control registers; copy broadcast control registers to data registers; and immediate-to-register instructions. the

According to one embodiment of the invention, the processor of FIG. 1 is characterized by a first fixed data execution path and a second configurable data execution path. The first data path has fixed SIMD execution units split into lanes in a similar fashion to conventional SIMD processing designs. The second data path has a configurable depth of execution units 110 . "Deep execution" refers to the processor's ability to perform multiple sequential operations on data provided by a single issued instruction before returning the result to the register file. One example of deep execution is the conventional MAC operation (Multiply and Accumulate), which performs two operations (Multiply and Add) on data from a single instruction, and thus has a depth of order 2. Deep execution may also be characterized by the number of operand inputs equaling the number of result outputs; or equivalently, valency-in equals valency-out. Thus, for example, regular two-operand addition with one result is not an example of a preferred deep implementation, since the number of operands is not equal to the number of results; whereas convolution, fast Fourier transform, Trellis/Viterbi encoding, correlators, finite impulse response Filters and other signal processing algorithms are examples of deep implementations. Dedicated digital signal processing (DSP) algorithms typically perform deep execution at the bit level and in memory-mapped form. However, the algorithms of conventional register-mapped general-purpose DSPs do not perform deep execution, but, in MAC operations, execute instructions with a sequential depth of at most an order of two. In contrast, the processor of FIG. 1 provides a register-mapped general-purpose processor capable of executing dynamically configurable word-level instructions orders of magnitude greater than two in depth. In the processor of Figure 1, the characteristics of deeply executed instructions (the graph of mathematical functions to be executed) can be adjusted/customized by configuration information in the instructions themselves. In a preferred embodiment, the format instructions include bit positions assigned to configuration information. To provide this capability, the deep execution unit 110 has configurable execution resources, which means that operator modes, interconnections and constants can be uploaded to suit each application. Deep execution adds depth to the parallelism of execution, which is orthogonal to the width provided by early concepts of SIMD and LIW processing; thus it represents an additional metric for increasing the work-per-instruction of the target processor . the

FIG. 3 illustrates components of a configurable deep execution unit 310 according to an embodiment of the invention. As shown in FIG. 1 , the configurable depth execution unit 110 is part of the data execution path 103 and thus may be directed by data side instructions from the MD and CD instruction packets 212 and 213 of FIG. 2 . In FIG. 3 , instructions 314 and operands 315 are provided to deep execution unit 310 from instruction decode unit 101 and data register file 105 of FIG. 1 . The multi-bit configuration code in the decoded instruction 314 is used in an access control map 316, which expands the multi-bit code into a more complex set of configuration signals for configuring the operators of the deep execution unit. For example, control map 316 may be implemented as a look-up table in which different possible multi-bit codes for an instruction are mapped to different possible operator configurations for a deep execution unit. Based on the results of a lookup table lookup of the control map 316, the cross-connect 317 configures a set of operators 318-321, in whatever arrangement is necessary to perform the operator configuration represented by the multi-bit instruction code. For example, the operator may include: a multiply operator 318 , an arithmetic logic unit (ALU) operator 319 , a state operator 320 , or a cross-lane transcoder 321 . In one embodiment, the deep execution unit contains 15 operators: one multiply operator 318, eight ALU operators 319, four state operators 320, and two cross-lane transcoders 321; It is also possible. The operands 315 provided to the deep execution units may be, for example, 16-bit operands; these operands are provided to the second cross-connect 322, which may provide the operands to the appropriate operators 318-321. The second cross-connect 322 also receives feedback 324 of intermediate results from the operators 318-321, which in turn may likewise be provided by the second cross-connect 322 to the appropriate operators 318-321. A third cross-connect 323 multiplexes the results from the operators 318 - 321 and outputs a final result 325 . Various control signals may be used to configure the operator; for example, control map 316 of the embodiment of FIG. 3 need not be implemented as a single look-up table, but may be implemented as a sequence of two or more cascaded look-up tables. Entries in the first look-up table can be pointed from given multi-bit instruction codes to the second look-up table, thus reducing the amount of storage required in each look-up table for complex operator configurations. For example, the first look-up table may be organized as a library of configuration classes such that multiple multi-bit instruction codes are grouped together in the first look-up table, with each group pointing to a specific configuration for each multi-bit code of the group. Subsequent lookup table. the

According to the embodiment of Fig. 3, operators are preferably pre-configured into various operator classes. In practice, this is achieved through a hardwired policy layer. The advantage of this approach is that it means that fewer predefined configurations need to be stored and the control circuitry can be simpler. For example, operator 318 is preconfigured in the class of multiply operators; operator 319 is preconfigured as an ALU operator; operator 320 is preconfigured as a state operator; and operator 321 is preconfigured as a cross-lane escape implementor; and other preconfigured classes are possible. However, even if the classes of operators are pre-configured, for the final arrangement of a particular configuration for implementing a given algorithm, the runtime flexibility of the instructions enables the arrangement of at least the following: (i) the number of operators in each class Connectivity; (ii) connectivity with operators from other classes; (iii) connectivity with any associated transformations. the

It will be appreciated by those skilled in the art that while the above has described what is considered the best mode of the invention and where other modes of carrying out the invention are appropriate, the invention should not be limited to the described description of the preferred embodiments. Specific apparatus configurations or method steps disclosed in . It will also be appreciated by those skilled in the art that the invention has broad applicability and that the embodiments allow for a wide range of different implementations and modifications without departing from the inventive concept. In particular, the exemplary bit widths mentioned here are not limiting, nor are they arbitrary choices of bit widths referred to as halfwords, words, long, etc. the

Claims (2)

1. A computer processor, said processor comprising: The decoding unit is used to decode the instruction packet stream from the memory, and each instruction packet includes a plurality of instructions; a control execution path comprising a branch unit, an execution unit, and a load/store unit and operable to execute control processing operations; wherein the decoding unit is operable to receive an instruction packet having a bit length of 64 bits, and is operable to use an identification bit in the instruction packet to detect whether the instruction packet defines three bits each having a 21-bit bit length long control instructions, and wherein when the decoding unit detects that the instruction packet includes three such control instructions, the control instruction is provided to the control execution path for appearing in the instruction packet according to the three such control instructions order to execute. 2. A method of operating a computer processor comprising a control execution path and capable of performing control processing operations having a branch unit, an execution unit and a load/store unit, the method comprising: (a) receiving from memory a sequence of instruction packets, each of the instruction packets including a plurality of instructions defining operations; (b) sequentially decode each instruction packet by using the identification bits in the instruction packet to determine whether the instruction packet defines three control instructions each having a length of 21 bits, and wherein when the decoding unit When it is detected that the instruction packet includes three such control instructions, the control instructions are provided to the control execution path for execution in the order in which the three such control instructions appear in the instruction packet.

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