JPS59121540A - Operation control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a control method for an arithmetic unit using microprogram control. When a bit error (micro error) is detected in the control information at a step in the middle of the micro program in ff, to avoid unnecessary delay (-1
The present invention relates to a method for controlling the progress and stop of an arithmetic cycle according to the characteristics of the arithmetic processing to be executed.

[Conventional technology and problems]

FIG. 1 shows a schematic configuration of a general microprogram control arithmetic device, in which 1 is a microprogram control section, 2 is one arithmetic control section, and 3 is an arithmetic section.

4 is a control memory. The microprogram control unit is activated by an arithmetic instruction and executes a microprogram consisting of a series of microinstruction steps that require arithmetic processing (two steps). What needs to be confirmed and
The operation control unit sets the operation cycle according to the microinstruction, and the operation control unit sets the operation cycle according to the microinstruction. Cycle (second cycle) controls the arithmetic unit and controls the bus transfer gate.

Executes arithmetic processing operations such as setting registers, reading/writing memory, and checking data.

When all calculation processing is completed, the microprogram control unit is notified and the calculation is completed.

The arithmetic control section is equipped with an arithmetic cycle counter for controlling the arithmetic cycle when the microprogram is executed, and a cycle synchronization check is performed to ensure that each step of the microprogram is advanced in synchronization with the arithmetic cycle. is being carried out.

Therefore, when the microprogram control unit detects a bit error during the microinstruction read from the side memory and becomes unexecutable due to an ECC check, for example, the microprogram control unit unconditionally (two operation cycle stop the progress of , that is, stop the calculation operation,
It restarted after, for example, one cycle after the error correction was completed.

FIG. 2(α) shows an example of a normal operation sequence of a microprogram of arithmetic instructions.

The illustrated microprograms are A, B, C, and I).

The calculation cycle consists of 6 steps, E and F.

A total of 8 cycles from C1 to C8 are used. Therefore, when the arithmetic cycle counter counts 08, the arithmetic control unit determines the end of the arithmetic operation by the microprogram control unit (
= Notify 0 By the way, as shown in FIG. 2 (h) (=, if the microprogram control unit detects an error in the microinstruction read from the control memory in the C cycle of the C step, as described above, The calculation cycle is stopped by one cycle and is generated with a delay of 9th C4 cycle. Therefore, the C8 cycle occurs at the 9th cycle counting from the C1 cycle. Since the completion of the calculation is notified in the C8 cycle, Figure 2 (Compared to the case of α, there was a problem that the end of the calculation was delayed by one cycle).

[Object and structure of the invention]

An object of the present invention is to minimize the delay in arithmetic cycles when an error is detected in a microinstruction read from a control memory in an arithmetic device controlled by a microprogram.

The present invention therefore provides a solution during a series of computational cycles.

A cycle that operates in synchronization with a microprogram.

In other words, there are those in which the calculation cycle of the next step must be started after confirming the completion of the calculation cycle of the previous step, and cycles that operate asynchronously, that is, the next step without crossing the completion of the calculation cycle of the previous step. Focusing on the fact that there are certain things that are allowed to start execution, when the above error occurs in a synchronous operation cycle (limited to two)

The above object is achieved by delaying the arithmetic cycle and, on the other hand, starting the arithmetic cycle without delay when the arithmetic cycle occurs in a non-isomorphic arithmetic cycle.

The configuration of the present invention provides means for identifying, in a microprogram-controlled arithmetic device, a series of arithmetic cycles of a microprogram, arithmetic cycles that are synchronized with the microprogram, and arithmetic cycles that are asynchronous with respect to the microprogram. If a bit error is detected in the control information when the microinstructions for each step of the microprogram are sequentially read from the control memory when the microprogram is executed, the operation cycle is The feature is that the calculation cycle is temporarily stopped only when the calculation cycle is synchronized with the calculation cycle.

[Embodiments of the invention]

The present invention will be explained below based on nine examples.

FIG. 3 is a block diagram of a system according to an embodiment of the present invention. In the figure, reference numbers 1 to 4 are the same as those shown in FIG. Further, 5 is an instruction register, 6 is a decoder, 7 is an FCC circuit, 8 is a microinstruction decoder, and 9 is an operation cycle counter.

10 is a synchronous/asynchronous cycle type register, 11 is a logic circuit, Cn is the number of arithmetic cycles, and X/Y is a synchronous/asynchronous cycle type.

The operation instruction in the instruction register 5 is decoded by a decoder 6 (2), and the microinstruction address is given to the control memory 4 via the microprogram control section 1.

Control information such as microinstructions read from the control memory 4 is checked for errors in the ECC circuit 7, and if a 1-set error is detected, it is automatically corrected. Micro instructions are
Applied to microinstruction decoder 8. How does the microinstruction decoder 8 come out?

It is used to control the operation of the calculation unit 3 via the calculation control unit 2.

The number of calculation cycles Cn is predetermined for each calculation instruction, and is updated by the control information of the decoder 6 and microdecoder 8.

Synchronous/asynchronous cycle type information .

When the ECC circuit 7 detects an error in the data by checking the BCC, it sends an arithmetic cycle stop signal to the logic circuit 1](-, and if the arithmetic cycle is a synchronous cycle (
X/Y='1'), the supply of clocks to the arithmetic cycle counter 9, arithmetic control circuit, etc. is prohibited. Note that when the ECC circuit 7 completes error correction, the arithmetic cycle stop signal is released.

Subsequent clocks are provided.

In the logic circuit 11, the operation cycle is an asynchronous cycle (X/
If Y=="10"), even if an arithmetic cycle stop signal is applied, the clock supply is not inhibited and the arithmetic cycles proceed in a predetermined order.

FIG. 4 is a sequence diagram according to nine embodiments of the present invention when steps A and F of the microprogram are defined as synchronous cycles, and the other steps are defined as asynchronous cycles.

Assuming that an error is detected in +03 cycles as in the case of Fig. 2 (h), in this case, since it is an asynchronous cycle (Y), the operation cycle is not stopped and the entire operation is completed in 8 cycles. The processing time can be reduced by one cycle compared to the case shown in FIG.

〔Effect of the invention〕

As described above, (1) according to the present invention, when an error is detected in control information, an arithmetic unit based on program control (2) does not unconditionally delay the arithmetic cycle as in the past; This is because the calculation operation is progressing.

Computation time is reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an arithmetic unit based on general microprogram control (= Fig. 2 (α)), (A) is a diagram showing an example of a control sequence, and Fig. 3 is a block diagram of an example system. Figure 4 is a diagram showing an example of a control sequence in the embodiment system. In the figure, 1 is a microprogram control section, 2 is an arithmetic control section, 3 is an arithmetic section, 4 is a control memory, 7 is an ECC circuit, 8 represents a micro decoder, 9 represents an operation cycle counter, 10 represents a synchronous/asynchronous cycle type register, and 11 represents a logic gate.

Claims (1)

[Scope of Claims] Microprogram control (in a two-based arithmetic unit, means for identifying a series of arithmetic cycles of a microprogram into arithmetic cycles that are synchronized with the microprogram and arithmetic cycles that are asynchronous with respect to the microprogram) , when the microinstructions of each step of the microprogram are read out sequentially from the control memory when the microprogram is executed, the control information (if a two-bit error is detected, the calculation cycle is An arithmetic control method characterized by temporarily stopping the arithmetic cycle when the arithmetic cycle is synchronized.