JPH04145552A - Cache storage device - Google Patents

Abstract

PURPOSE:To make reading operations and writing operations simultaneously executable when a read level is not equal to a write level by registering the level obtained by indexing an address array with a write address in a storage buffer. CONSTITUTION:The need of indexing an address array 1 at the time of writing in data arrays 2 and 3 from a store buffer 8 is eliminated from this cache storage device by simultaneously registering a write level obtained by indexing an address array with the write address to a cache storage when the write address is registered in a store buffer 8 and, at the same time, the storage device is provided with divided data arrays which are obtained by dividing the data arrays 2 and 3 by addresses or levels and can independently make writing/reading operations. Therefore, when the divided data array to be read is different from the divided array to be written, reading operations can be performed simultaneously with writing operations.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device having cache memory.

[Conventional technology]

A conventional cache storage method using a set associative method consisting of multiple columns and multiple levels will be explained. Cache storage is a high-speed, small-capacity storage device designed to read data faster in an information processing device, and serves to store a portion of the data in the main storage device.

At that time, the main memory and cache memory are divided into blocks of a certain size, and a small memory is used to remember which location on the main memory the cache memory data is from. This is called an address array. Therefore, when an information processing device accesses a cache storage device, it indexes the address array by the address on the main memory of the data and identifies the cache storage device of the desired data. If the data exists, the address of the data in the cache storage device is determined. That is, the address array converts the main memory address into an address within the cache memory. In addition, conventional store buffers hold the write address until the operation result, that is, the write data, is output from the arithmetic unit, and when the write data is complete, the address array is indexed by the write address and the cache is stored. The level is determined and the write data is written to all data arrays. In other words, since reading from keyed storage and writing from store buffer to cache storage both index the same address array, if reading and writing conflict, one or the other must wait.

[Problem to be solved by the invention]

The conventional cache storage device described above indexes the same address array both when reading and when writing from the store buffer, so reading and writing cannot be performed simultaneously, which hinders high-speed processing.

[Failure to solve the problem]

The cache storage device of the first invention includes an address circuit that holds a read or write address, and an address of data registered in the cache storage, and when the address circuit is supplied with the address to be held, An address array that outputs the level in the cache memory if the target data block of this address is registered, a write address held in the address circuit, and the write address is supplied to the address array. A data array that is divided by the data width to be read and written at once, and each has an address register and a write enable register that instructs writing for each level. By comparing the read address held in the address circuit with the write address output from the store buffer, the divided data array to be read and the divided data to be written are determined.・Means for determining whether or not the arrays are the same, and if the determination result is negative, supplying the read address held in the address circuit to the address register of the divided data array to be read. At the same time, the write address and level output from the store buffer are supplied to the address register and write enable register of the divided data array to be written, thereby simultaneously reading and writing between different divided data arrays. The apparatus includes means for instructing an operation, and means for instructing an operation to give priority to reading if the determination results are the same.

A cache storage device according to a second invention includes the address circuit according to the first invention, an address array, a divided data array, a store buffer, and a write address and level output from the store buffer. means for supplying the read address held in the address circuit to all the divided data arrays to which the output of the store buffer is not supplied; means for fully determining whether or not the address can be supplied to the divided data array to which the desired operation is to be performed; and if the determination result is negative, sending the data read from the divided data array to the arithmetic unit;
If the determination result is negative, means is provided to continue supplying the same read address to the divided data array until the determination result is no longer negative.

A cache storage device according to a third invention includes the address circuit according to the first invention, an address array, a store buffer,
A divided data array that is divided into levels, each having an address register, and capable of instructing writing for each level, and an address array indexed by read addresses held in the address circuit. Means for fully determining whether or not the level at which reading is desired and the level at which writing is desired are the same by comparing the output and the writing level which is the output of the store buffer, and whether or not the judgment result is negative. For example, the read address held in the address circuit is supplied to the address register of the divided data array of the level to be read, and the write address output from the store buffer is supplied to the divided data array of the level to be written. Means for supplying data to the address register of the data array to perform a write operation, instructing simultaneous read and write operations between different divided data arrays, and operation for giving priority to read if the above judgment results are the same. shall be provided with means for instructing.

A cache storage device according to a fourth aspect of the invention includes the address circuit, an address array, a store buffer, a divided data array, and a write address that is an output of the store buffer at a level at which writing is desired. means for supplying the read address held in the address circuit to the divided data array of all levels to which the output of the store buffer is not supplied; means for determining whether or not the address has been supplied to the divided data array for which all read operations are to be performed, and if the determination result is negative, transmitting the data read from the divided data array to the entire arithmetic unit;
If the determination result is negative, means is provided to continue supplying the same read address to the divided data array until the determination result is no longer negative.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. The register 4 is an address circuit that receives and holds the read or write address money of the cache storage device output from the advance control device.

Address array 1 is a memory that stores the address of the cheater block in the cache memory on the main memory.
It is called. Address array 1 uses comparators 5 and 6 to compare the address indexed and output by a portion of the output of register 4 with the remainder of the output of register 4, thereby determining the purpose of the cache storage device. It indicates whether a cheater block exists, and if so, whether it belongs to level O or level 1, and sets the result in register 7 together with the output of register 4. Buffer 8
is a buffer that stores the contents of the register 7 that is set by indexing the address array using the contents of the register 4 when a write request is issued to the cache memory from the preceding control device. The buffer 9 is a buffer that receives the calculation results from the calculation device and stores the data until it is written into the cache memory. Register 10. Each register 11 has a buffer 8 . Contents of buffer 9 t - A register that receives and holds data in order, buffer 8 .
9. Registers 10 and 11 constitute a store buffer.

First data array2. The second data array 3 is a cache storage section divided into blocks of the same size as the main memory, and is called a data array (Dataλrray). Register 13° Register 16 is
First data array 2 and second data array 3, respectively.
address and level O.

This is a register that holds level 1 write enable. Register 14. The registers 18 are respectively connected to the first data array 2. This is a register that holds write data to the second data array 3. Selector 12. Selector 15
are the first data array 2., respectively. The data to be sent to the registers 13 and 16, which are the address and write enable registers of the second data array 3, is switched between the output of the register 4 and the output of the register 10. It is a selector that determines the read or write address of the second data array 3 and determines whether it is a read cycle or a write cycle.

Selector 18. The selectors 19 respectively select the first data array 2. Level 0 and Level 1 of the second data array 1
This is a selector for switching the data according to the level set in the register 7 and supplying it to the selector 20. The selector 20 selects the LSB (Least 51gn1fic) of the read address set in the register 7.
This selector is used to switch between the output of the selector 18 and the output of the selector 19 and supply it to the register 21 depending on the output of the selector 18 or the output of the selector 19. The register 21 is the selector 20
The receiver is a register for receiving the output of and sending it to the arithmetic unit.

The gates 22 to 25 control the first data array 2 . This is a gate that controls read and write operations of the second data array 3.

Next, the operation of this cache storage device will be explained in detail.

When the advance controller issues a write request to the cache memory, the write address is held in register 4, and the output from register 4 is set in register 7 together with the result of indexing address array 1. The data is then transferred to the content line buffer 8 of the register 7 and stored until the arithmetic operation result is written to the buffer 9 by the arithmetic unit. When the arithmetic result is stored in the buffer 9 by the arithmetic device and becomes ready to be written to the cache memory, the write address and the write data are stored in the buffer 8. Buffer 9 is transferred to register 10 and register 11, respectively.

When the advance control device issues a read request from the cache memory, the read address is held in the register 4. The LSB of the read address of register 4 is sent to gate 22 on signal line 104, and the LSB of the write address of register 10 is sent to gate 24 on signal 11105. Gate 22.
24 outputs the logic of the input signal as it is and the inverted logic. The gate 23 is configured such that the LSB of the read address is “
1” and the LSB of the write address is “0”
At this time, the output of the selector 12 becomes a write address, and the first data array 2 performs a write operation. The gate 25 outputs "1" when the LSB of the read array address is rOJ and the LSB of the write address is 11. At this time, the output of the selector 15 is not a write address, and the second data array 3 is not a write address. Do all the movements.

As can be seen from the above explanation, the data array to which you wish to write can perform a write operation only when the LSB of the write address is not the same as the LSB of the read address, while the data array to which you wish to read can perform the write operation. A read address can be supplied at any time, and the read data can be stored in the arithmetic unit. Register 4. Address array 1.
Comparator 5.6. Register 7, buffer 8. Buffer 9° register 10, 11 . First data array2. Second data array3. Register 13. register 16 register 1
4.17. Selectors 12, 15. selector 18.19,
20. The contents of the register 21 are the same as those described in FIG.

The gate 26 instructs the output of the selector 12 to become the write address when the LSB of the write address held in the register 10 is "0", and instructs the output of the selector 15 to become the write address when it is "1". It is a gate that instructs. The comparator 28 is a circuit that detects whether the LSB of the read address and the LSB of the write address match, and if they match, it is set in the register 29trlj.

The selector 27 is a selector that switches between the read address held in the register 4 and the read address held in the register 7 using the output of the register 29;
Read address and register 1 output from selector 27
If the LSB of the write address, which is an output of 0, is different, the register 29 remains "0" and the output of register 4 is selected. However, if the LSB of the read address and the write address are the same, the register 29 remains "0". This state continues until the register 29 becomes "0" and all the outputs of the register 7 are selected.

As can be seen from the above explanation, the write address is always supplied to the data array to be written indicated by the LSB of the write address and a write operation is performed, and the data array to be read is read out for the write operation. When an address cannot be supplied, the read address is held until it can be supplied, so that read and write operations can be performed at the same time unless the LSB of the read address and the LSB of the write address are the same. can.

FIG. 3 is a block diagram showing a third embodiment of the present invention. Register 4. Address array 1. Compare! 5, 6,
Register 7, back 8, 9. Register 10, 11, 1
4,17. Selector 18. For register 21, the first
It is the same as the explanation of the figure. First data array2. Second
The data array 3 is different from FIG. 1 in that it is divided into levels: level 02>; first data array 2. Level 1 is the second data array 3. Accordingly, the registers 13 and 16 are also different from those in FIG. 1, and the write enable is only one bit for each data array. The same goes for selectors 12 and 15. Gate 30 connects the inverted output of comparator 5 and the level O of register 10.
By taking the AND of the bits, if the desired level for writing is not the same as the level for reading, a write operation is performed to the first data array 2 using the output of the selector 12 as the write address. This is a gate that instructs the user to perform the following steps. The same applies to the gate 31.

As can be seen from the above explanation, a write operation can be performed on a round data array only when the level to which one wishes to write is not the same as the level from which one wishes to read; When is S! ! The outgoing address can be supplied and the arithmetic unit K
You can send the data you have generated.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention. Register 4. Address array l, comparators 5, 6 . Register 7, buffers 8, 9 . Registers 10, 11. Selectors 12, 15. Registers 13.14, 16117. first data array 2, second data array 3. Selector 18. The register 21 is the same as the explanation in FIG. The selector 12 outputs the write address when the level O bit of the register 10 is "1" and reads the data.
Cause array 2 to perform a write operation. The same applies to the selector 15. Gates 132, 33, and 34 are gates that detect whether or not the level at which reading is desired matches the level at which writing is desired. If they match, the register 29t is
- Set to rlJ. The selector 27 is a selector that switches between the read address held in the register 4 and the read address held in the register 7 using the output of the register 29. indexed result comparator 5,
If the level at which you want to read one line output from 6 and the level at which you want to write held in register IOK are different, leave register 29 at "0" and select register 4t, but the level at which you want to read and write is different. If the desired levels are the same, register 29 is set to "1".
This selects register 7, and this state continues until register 29 becomes rOJ.

As you can see from the above explanation, the data array at the level you want to write to is always supplied with a write address for a write operation, and the data array at the level you want to read is always supplied with a read address for a write operation. If this is not possible, by continuing to hold the read address until it can be supplied, it is possible to perform read and write operations at the same time unless the read and write levels are the same.6 [Effects of the Invention] As described above, in the present invention, when registering a write address to cache memory in a store buffer, 1) the write level obtained by indexing the address array with the write address is simultaneously registered, and the data is read from the store buffer.
By eliminating the need to index the address array when writing to the array, and by having the function to divide the data array by address or level and read and write the divided data arrays independently, it is possible to read round divided data. If the array and the divided data array to be written are different, there is an advantage that read and write operations can be performed simultaneously.

of

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
FIG. 3 is a block diagram showing a second embodiment of the invention, FIG. 3 is a block diagram showing a third embodiment of the invention, and FIG. 4 is a block diagram showing a fourth embodiment of the invention. . 1... Address array, 2... First data array, 3... Second data array, 4, 7, 10° 11.13, 14, 16, 17, 21.29...・Register, 5.6.28 - Comparator, 8, 9... Buffer, 12° 15.18, 19, 20.27... Selector, 22, 23° 24.25, 26, 30, 31, 32
,33.34...Gate. Agent Patent Attorney Susumu Uchihara Diagram 1 Nitomi Fba-Ljl Liquidator Tomi

Claims (1)

[Claims] 1. A set-associative cache storage device comprising multiple columns and multiple levels, including an address circuit that holds read or write addresses and an address circuit that stores addresses of data registered in the cache storage. an address array that, when an address held in the address circuit is supplied to the address circuit, outputs a level in the cache memory if a target data block of the held address is registered in the cache memory;
A plurality of sets of a write address held in the address circuit and a level obtained by supplying the write address to the address array, a store buffer for temporarily storing write data corresponding to the write address, and a store buffer for temporarily storing write data corresponding to the write address; each having an address register and a write enable register for instructing writing for each level, and a data array for storing write data from the store buffer, and a data array held in the address circuit. means for comparing a read address and a write address that is an output of the store buffer to determine whether the divided data array to be read and the divided data array to be written are the same; If the result is negative, the read address held in the address circuit is supplied to the address register of the divided data array to be read, and the write address and level output from the store buffer are written. means for simultaneously instructing read and write operations between the different divided zeta arrays by supplying the address register and write enable register of the divided data array; and if the determination result is the same, read is given priority; A cache storage device comprising means for instructing an operation to be performed. 2. In a set-associative cache storage device consisting of multiple columns and multiple levels, there is an address circuit that holds a read or write address, and an address circuit that stores the address of data registered in the cache storage and stores it in the address circuit. an address array that, when supplied with a retained address, outputs a level in the cache memory if a target data block of the retained address is registered in the cache memory;
A plurality of sets of a write address held in the address circuit and a level obtained by supplying the write address to the address array, a store buffer for temporarily storing write data corresponding to the write address, and a store buffer for temporarily storing write data corresponding to the write address; each having an address register and a write enable register for instructing writing for each level; a data array that stores write data from the store buffer; and a data array that stores write data from the store buffer; means for supplying addresses and levels to said divided data arrays for writing; and means for supplying read addresses held in said address circuit to all said divided data arrays to which the output of said store buffer is not supplied. means for determining whether or not the read address has been supplied to the divided data array that performs reading at the read address; and if the determination result is negative, the data read from the divided data array; A cache storage device, comprising means for sending a read address to an arithmetic unit and, if the determination result is negative, continuing to supply the same read address to the divided data array until the determination result is no longer negative. 3. In a set-associative cache storage device consisting of multiple columns and multiple levels, there is an address circuit that holds a read or write address, and an address circuit that stores the address of data registered in the cache storage and stores it in the address circuit. an address array that, when supplied with a retained address, outputs a level in the cache memory if a target data block of the retained address is registered in the cache memory;
a plurality of sets of write addresses held in the address circuit and levels obtained by supplying the write addresses to the address array; a store buffer for temporarily storing write data corresponding to the write addresses; and a store buffer for temporarily storing write data corresponding to the write addresses; Divided data is divided, each having an address register, writes independently according to instructions for each level, and stores write data from the store buffer.
The output of the address array indexed by the read address held in the address circuit is compared with the write level that is the output of the store buffer, and the level for reading and the level for writing are determined. means for determining whether they are the same or not; and if the determination result is negative, supplying the read address held in the address circuit to the address register of the divided data array at the level to be read; Means for supplying the write address output from the buffer to the address register of the divided data array at the writing level to perform a write operation, and simultaneously instructing read and write operations between different divided data arrays. and,
A cache storage device characterized by comprising means for instructing an operation to give priority to reading if the determination results are the same. 4. In a set-associative cache storage device consisting of multiple columns and multiple levels, there is an address circuit that holds a read or write address, and an address circuit that stores the address of data registered in the cache storage and stores it in the address circuit. an address array that, when supplied with a retained address, outputs a level in the cache memory if a target data block of the retained address is registered in the cache memory;
a plurality of sets of write addresses held in the address circuit and levels obtained by supplying the write addresses to the address array; a store buffer for temporarily storing write data corresponding to the write addresses; and a store buffer for temporarily storing write data corresponding to the write addresses; divided, each having an address register,
A divided data array that performs write operations independently according to instructions for each level and stores write data from the store buffer, and supplies a write address that is the output of the store buffer to the divided data array of the level that performs writing. means for supplying the read address held in the address circuit to the divided data arrays of all levels to which the output of the store buffer is not supplied, and the divided data read at the read address;・Means for determining whether or not the address could be supplied to the array, and if the determination result is negative, the divided data.
A cache storage device characterized by comprising means for sending data read from the array to an arithmetic unit and, if the determination result is negative, continuing to supply the same read address to the divided data array until the determination result is no longer negative.