KR102915344B1 - Processor memory access - Google Patents

Abstract

A computing device is provided, comprising: - a plurality of ALUs (9); - a set of registers (11); - a memory (13); - a memory interface between the registers (11) and the memory (13); - a control unit (5), the control unit (5) comprising: - at least one cycle i; - Controlling the ALUs (9) by causing at least one cycle ii following at least one cycle i, wherein at least one cycle i comprises implementing at least one first computing operation via the arithmetic logic unit (9) and downloading a first data set (AA4_7; BB4_7) from a memory (13) to at least one register (11), and at least one cycle ii comprises implementing a second computing operation via the arithmetic logic unit (9), during which at least a part (A4; B4) of the first data set (AA4_7; BB4_7) forms at least one operand.

Description

Processor memory access

The present invention relates to the field of processors and also to the interactions of memory units and processors.

Conventionally, a computing device includes a set of one or more processors. Each processor includes one or more processing units, or PUs. Each PU includes one or more computing units, referred to as arithmetic logic units, or ALUs. To achieve high-performance computing devices, i.e., to achieve fast computing operations, it is conventional to provide a large number of ALUs. Thus, the ALUs can process operations in parallel, i.e., simultaneously. In this case, the unit of time is a computing cycle. Therefore, it is common to quantify the computing power of a computing device in terms of the number of operations that can be performed per computing cycle.

However, if the elements of the device that interact with the ALUs are not designed (sized) to accommodate the number of ALUs required to operate concurrently, then having a large number of ALUs may be inappropriate or even unnecessary. In other words, if a large number of ALUs are present, the configuration of the ALUs' environment may be a limiting factor in the device's power. In particular, the device includes a memory assembly, which itself includes one or more memory units, each of which has a fixed number of memory locations where computational data can be permanently stored. During computational processing operations, the ALUs receive data from the memory units at their inputs and provide data at their outputs, some of which is stored on the memory units. In this case, it should be understood that in addition to the number of ALUs, the number of memory units is another factor in determining the device's computational power.

Data is routed between the ALUs and memory units, in both directions, by the device's bus. The term "bus" is used herein in its general sense of a system (or interface) for transferring data, including the protocols and hardware (interface circuitry) that govern the exchanges. The bus carries data itself, addresses, and control signals. Each bus itself also has hardware and software limitations that restrict the routing of data. In particular, the bus has a limited number of ports on the memory unit side and a limited number of ports on the ALU side. In the present context, the memory units are considered single-port, i.e., read and write operations are implemented during different cycles, in contrast to what are referred to as "double-port" memories (which are ostensibly more expensive and require larger dual control buses for reads and writes). Thus, during a computing cycle, a memory location is accessible via the bus in a single direction (either in "read" mode or in "write" mode). Furthermore, during a computing cycle, the memory location is accessible only to a single ALU. As a variant, the proposed technical solutions can be implemented as so-called "dual-port" memories. In such embodiments, read and write operations can be implemented during the same computing cycle.

Between the bus and the ALUs, the computing device typically includes a set of registers and local memory units, which can be viewed as memories separate from the aforementioned memory units. For ease of understanding, a distinction is made herein between "registers," which are intended to store data, and "local memory units," which are intended to store memory addresses. Each register is assigned to an ALU of a PU. A PU is assigned multiple registers. The storage capacity of the registers is significantly limited compared to the memory units, but the contents of the registers are directly accessible to the ALUs.

To perform a computing operation, each ALU must first obtain the input data for the computing operation, typically two operands of the elementary computing operation. Therefore, a "read" operation is implemented on the corresponding memory location via the bus to import each of the two operands into a register. The ALU then performs the computing operation itself, based on the data from the register and exporting the result in the form of an item of data onto the register. Finally, a "write" operation is implemented to record the result of the computing operation into the memory location. During this write operation, the result stored in the register is written into the memory location via the bus. Each of these operations typically consumes one or more computing cycles.

In known computing devices, it is common to attempt to execute multiple operations (or instructions) during a single computing cycle to reduce the overall number of computing cycles and thus increase efficiency. This is referred to as parallel "processing chains" or "pipelines." However, numerous interdependencies often exist between operations. For example, it is impossible to perform a basic computing operation while operands are not read and accessible in the registers for the ALU. Therefore, implementing processing chains involves checking interdependencies between operations (instructions), which is complex and therefore expensive.

Multiple independent operations are usually implemented during a single computing cycle. In general, it is possible to perform a computing operation and a read or write operation for a given ALU during a single computing cycle. In contrast, it is not possible to perform a read operation and a write operation simultaneously (in the case of single-port memory units) for a given ALU during a single computing cycle. On the other hand, memory access operations (buses) do not allow performing read or write operations for two separate ALUs during a single computing cycle and for a given memory location.

Therefore, to ensure that each ALU is as active as possible (without losing any compute cycles), it is intuitive to try to achieve a situation where three memory locations are accessible to each ALU in each compute cycle, two of which are intended to supply operands to the two inputs of the ALU (read mode), and one of which is intended to receive the result of the elementary compute operation from the ALU (write mode). Thus, the two read operations are chosen to obtain (store in registers) the operands required for the elementary compute operation to be implemented during the subsequent compute cycle. Therefore, to increase the compute power, it is intuitive to provide both a large number of ALUs and a proportional number of memory locations (e.g., at least three times as many memory locations as ALUs).

However, increasing the number of ALUs and memory units increases the complexity of the interactions between these two types of elements. Increasing the number of ALUs in a device and the memory units that can be connected to them leads to a non-linear increase in bus complexity. Therefore, increasing the number of ALUs and memory units is complex and expensive.

The present invention aims to improve this situation.

What is proposed is a computing device, which computing device comprises:

- Multiple arithmetic logic units;

- a set of registers (wherein the registers can supply data of operand type to the inputs of the arithmetic logic units and can supply data from the outputs of the arithmetic logic units);

- Memory;

- Memory interfaces (through which data is transferred and routed between registers and memory);

- A control unit (wherein the control unit is configured to control the arithmetic logic units according to a processing chain microarchitecture so that the arithmetic logic units perform computing operations in parallel with each other, and the control unit is also designed to control memory access operations via a memory interface). The control operations are:

- at least one cycle i (wherein at least one cycle i includes both implementing at least one first computing operation via an arithmetic logic unit and downloading a first dataset from memory to at least one register);

- at least one cycle ii subsequent to at least one cycle i, wherein at least one cycle ii includes implementing a second computing operation via an arithmetic logic unit, and during the second computing operation, at least a portion of the first dataset forms at least one operand.

Such a device enables reading a data set from a memory unit and temporarily setting said data in a register in a single operation. Not all data read in a computing cycle t may be used in the immediately subsequent computing cycle t+1. At least in some cases, some of the read data is not needed during the subsequent computing cycle t+1, but is used during another subsequent computing cycle t+1+n without the need to perform an additional read operation and thus consume additional computing cycles.

In the field of parallel data processing using computing devices, a common approach is to schedule dedicated memory access operations to read only the data required by the next elementary computing operation to be implemented, and only those data required for the next elementary computing operation. This general approach may be referred to as "just-in-time memory access." In this general approach, reading (and storing) data items that are not immediately required is considered unnecessary. Thus, each memory access operation temporally precedes (and is necessary for) the elementary computing operation itself, but each memory access operation is directly scheduled based solely on the next elementary computing operation. The present applicant has overcome the prior art in this field by implementing a different approach.

Therefore, the applicant proposes an approach in which, during each read operation, the number of data read is greater than the number of data absolutely necessary to implement the next computing operation. In contrast to the previous approach, this approach may be referred to as "provisional memory access." In this case, it is possible for one item of data among the read data to be used for a future computing operation rather than the computing operation implemented immediately after the read operation. In such cases, the required data is obtained during a single memory access operation (with an increase in memory bandwidth), whereas a typical approach would require at least two separate memory access operations. Therefore, the effect of the approach proposed by the applicant is, at least in some cases, to reduce the consumption of computing cycles for memory access operations, thereby enabling improved device efficiency. Over a long period of time (over multiple consecutive computing cycles), the number of memory access operations (in read mode and/or write mode) is reduced.

This approach does not eliminate the possibility of loss, where some of the data read and stored in the registers may be lost (e.g., erased by other data stored in the same registers) even before being used in a computing operation. However, over a large number of computing operations and computing cycles, the applicant has observed an improvement in performance (even without selecting the datasets to be read). In other words, despite not selecting (or randomly selecting) the data to be read, this approach statistically improves the efficiency of the computing device compared to conventional approaches.

According to another embodiment, what is proposed is a data processing method implemented by a control unit of a computing device, said device comprising:

- Multiple arithmetic logic units;

- a set of registers (wherein the registers can supply data of operand type to the inputs of the arithmetic logic units and can supply data from the outputs of the arithmetic logic units);

- Memory;

- Memory interfaces (through which data is transferred and routed between registers and memory);

- Includes a control unit (wherein the control unit is configured to control the arithmetic logic units according to a processing chain microarchitecture so that the arithmetic logic units perform computing operations in parallel with each other, and the control unit is also designed to control memory access operations via a memory interface).

At least the method is,

- generating cycle i, wherein at least one cycle i includes both implementing at least one first computing operation via an arithmetic logic unit and downloading a first dataset from memory to at least one register;

- generating a cycle ii subsequent to cycle i, wherein at least one cycle ii includes implementing a second computing operation via an arithmetic logic unit, and during the second computing operation, at least a portion of the first dataset forms at least one operand.

According to another embodiment, a computer program, in particular a compilation computer program, is proposed, wherein the computer program comprises instructions for implementing some or all of the methods defined herein when the program is executed by a processor. According to another embodiment, a non-transient computer-readable recording medium on which the program is recorded is proposed.

The following features may be optionally implemented. They may be implemented independently or in combination.

- The control unit is also configured to implement an identification algorithm for identifying a first dataset to be downloaded during at least one cycle i based on a second computing operation to be implemented during at least one cycle ii before controlling the arithmetic units and memory access operations. This makes it possible to adapt the read data based on the computing operations to be performed, thereby improving the relevance of data within the first dataset to be downloaded.

- The control unit is configured to implement two separate cycles i, such that two separate first data sets are downloaded to at least one register, and at least a portion of each of the two first data sets forms an operand for a second computing operation of at least one cycle ii. This makes it possible to combine computing operations and memory access operations during said at least two cycles. Thus, at the end of the two cycles i, all operands required for subsequent computing operations may have been downloaded.

- The control unit is configured to implement a plurality of cycles ii that are separated from each other, such that a portion of the first dataset forming at least one operand for a second computing operation of the cycles ii is configured to be different in one cycle ii and another cycle ii of the plurality of cycles ii. This makes it possible to implement a plurality of basic computing operations on a single downloaded dataset.

- The control unit is configured to perform at least two iterations of a series of at least one cycle i and one cycle ii, said two iterations being at least partially superimposed such that at least one cycle ii of a first iteration forms the cycle i of a subsequent iteration. This makes it possible to perform computing operations and memory access operations over a particularly limited number of computing cycles, thereby further increasing efficiency.

- The control unit is configured to perform an initialization phase, which comprises downloading from memory to at least one register at least one dataset forming operands for a first computing operation of said first cycle i, prior to the first cycle i. This enables the method to be initialized to repeat cycle i and cycle ii as many times as necessary for each of the datasets to be processed.

- The control unit is also designed to control memory access operations via the memory interface, such that the control operations are:

- During cycle i, implementation of a plurality of first computing operations by a plurality of arithmetic logic units;

- designed to cause the implementation of a plurality of second computing operations by a plurality of arithmetic logic units during cycle ii,

The grouping of data for the dataset to be downloaded is selected to match the distribution of allocations of computing operations to each of the plurality of arithmetic logic units, such that the arithmetic logic units are selected to have synchronous, asynchronous, or mixed operations. This enables further efficiency improvement by adapting the coordinated operation of the ALUs based on the processing operations to be performed and available resources.

Other features, details, and advantages of the present invention will become apparent upon reading the detailed description below and upon analyzing the accompanying drawings, in which:
- Figure 1 shows the architecture of a computing device according to the present invention;
- Figure 2 is a partial depiction of the architecture of a computing device according to the present invention;
- Figure 3 shows one example of a memory access operation according to the present invention; and
- Fig. 4 is a variation of the example from Fig. 3.

The drawings and descriptions below inherently include elements of specific nature. Therefore, they may serve to provide a better understanding of the present invention and, where appropriate, contribute to its definition.

Figure 1 shows an example of a computing device (1). The device (1) comprises a set of one or more processors (3) (sometimes referred to as central processing units or CPUs). The set of processor(s) (3) comprises at least one control unit (5) and at least one processing unit (7), or PU (7). Each PU (7) comprises one or more computing units (referred to as arithmetic logic units (9) or ALU (9)). In the example described herein, each PU (7) also comprises a set of registers (11). The device (1) comprises at least one memory (13) capable of interacting with the set of processor(s) (3). For this purpose, the device (1) also comprises a memory interface (15), or “bus”.

In the present context, the memory units are considered to be single-ported, i.e., read and write operations are implemented during different cycles, in contrast to what are referred to as "dual-ported" memories (which are ostensibly more expensive and require larger dual control buses for reads and writes). As a variant, the proposed technical solutions can be implemented as what are referred to as "dual-ported" memories. In such embodiments, read and write operations can be implemented during one and the same computing cycle.

Figure 1 shows three PUs (7), PU 1, PU X, and PU N. To simplify Figure 1, only the structure of PU X is shown in detail. However, the structures of the PUs are similar to each other. In some variations, the number of PUs is different. The device (1) may include a single PU, two PUs, or more than three PUs.

In the example described herein, PU X includes four ALUs, ALU X.0, ALU X.1, ALU X.2, and ALU X.3. In some variations, the PUs may include different numbers of ALUs and/or different numbers of ALUs than four, including a single ALU. Each PU includes a set of registers (11), where at least one register (11) is assigned to each ALU. In the example described herein, PU X includes a single register (11) per ALU, i.e., four registers are referenced as REG X.0, REG X.1, REG X.2, and REG X.3, and are assigned to ALU X.0, ALU X.1, ALU X.2, and ALU X.3, respectively. In some variations, each ALU is assigned multiple registers (11).

Each register (11) can supply operand data to the inputs of the ALUs (9) and can receive data from the outputs of the ALUs (9). Each register (11) can also store data from the memory (13) obtained via the bus (15) through what is referred to as a "read" operation. Each register (11) can also transfer the stored data to the memory (13) via the bus (15) through what is referred to as a "write" operation. The read and write operations are managed by controlling memory access operations from the control unit (5).

The control unit (5) imposes on each ALU (9) the manner in which it performs basic computing operations, in particular imposing the order of the basic computing operations, and assigning the operations to be executed to each ALU (9). In the example described herein, the control unit (5) is configured to control the ALUs (9) according to a processing chain microarchitecture so that the ALUs (9) perform computing operations in parallel with each other. For example, the device (1) has a single instruction flow and multiple data flow architecture, referred to as SIMD for "Single Instructions Multiple Data", and/or a multiple instruction flow and multiple data flow architecture, referred to as MIMD for "Multiple Instructions Multiple Data". Meanwhile, the control unit (5) is also designed to control memory access operations via the memory interface (15), in particular, in the present case, to control read and write operations. The two types of control (computing and memory access) are shown by arrows in the dashed lines in Figure 1.

Reference is now made to Figure 2, which illustrates a single ALU Y. Data transfers are indicated by arrows in the solid lines. It should be understood that Figure 2 does not necessarily show a time t with simultaneous data transfers, since data is transferred stepwise. On the other hand, in order for an item of data to be transferred from a register (11) to an ALU (9), for example, said item of data needs to be transferred in advance from a memory (13), in this case via a memory interface (15) (or bus) to said register (11).

In the example of Fig. 2, an ALU referred to as ALU Y is assigned to three registers (11) referred to as REG Y.0, REG Y.1, and REG Y.2, respectively. Each ALU (9) has at least three ports, specifically two inputs and one output. For each operation, at least two operands are received by the first input and the second input, respectively. The result of the computing operation is transmitted via the output. In the example shown in Fig. 2, the operands received at the inputs come from register REG Y.0 and register REG Y.2, respectively. The result of the computing operation is written to register REG Y.1. Once written to register REG Y.1, the result (in the form of an item of data) is written to memory (13) via the memory interface (15). In some variations, at least one ALU may have more than two inputs and may receive more than two operands for the computing operation.

Each ALU(9) has,

- Integer arithmetic operations on data (addition, subtraction, multiplication, division, etc.);

- Floating-point arithmetic operations on data (addition, subtraction, multiplication, division, inversion, square root, logarithms, trigonometry, etc.);

- It can perform logic operations (2's complement, "logical AND", "logical OR", "exclusive OR", etc.).

The ALUs (9) do not exchange data directly with each other. For example, if the result of a first computing operation performed by a first ALU constitutes an operand for a second computing operation to be performed by a second ALU, the result of the first computing operation must be written to a register (11) at least before it can be used by the ALU (9).

In some embodiments, data written to a register (11) is also automatically written to memory (13) (via a memory interface (15)), even if said item of data is acquired to serve only as an operand and not as a result of a processing process in its entirety.

In some embodiments, data obtained to serve as an operand with short relevance (intermediate results that are not of interest at the end of the processing operation in their entirety) may not be automatically written to memory (13), but may only be temporarily stored on a register (11). For example, if the result of a first computing operation performed by a first ALU constitutes an operand for a second computing operation to be performed by a second ALU, the result of the first computing operation must be written to a register (11). Then, the said item of data is transferred directly from the register (11) to the second ALU as an operand. It should be understood that in this case, the assignment of the register (11) to the ALU (9) may evolve over time, in particular from one computing cycle to another. Such allocations may take the form of addressing data which always makes it possible to find the location of an item of data (whether it is on a register (11) or at a location within memory (15)).

In the following description, the operation of the device (1) is described with respect to processing operations applied to computing data, which processing operations are decomposed into a set of operations, which operations comprise computing operations performed in parallel by a plurality of ALUs (9) over a period of time consisting of a series of computing cycles. In this case, the ALUs (9) are said to operate according to a processing chain microarchitecture. However, the processing operations implemented by the device (1) and encompassed herein may themselves constitute a portion (or subset) of a broader computing process. This broader process may comprise computing operations that are performed in a non-parallel manner by the plurality of ALUs in other portions or subsets, for example, in a serial operating mode or in a cascade.

The (parallel or serial) operating architectures may be constant or dynamic, for example imposed (controlled) by a control unit (5). Architectural variations may vary, for example, depending on the data to be processed and on the current instructions received at the input of the device (1). Such dynamic adaptation of the architectures may be implemented as early as the compilation stage by adapting the machine instructions generated by the compiler based on the type of data to be processed and the instructions, when these can be derived from the source code. Such adaptation may also be implemented only in the device (1) or the processor, if the device (1) or the processor executes conventional machine code and is programmed to implement a set of configuration instructions depending on the data to be processed and the currently received instructions.

A memory interface (15) or "bus" transmits and routes data in both directions between the ALUs (9) and the memory (15). The memory interface (15) is controlled by the control unit (5). Thus, the control unit (5) controls access to the memory (13) of the device (1) via the memory interface (15).

A control unit (5) controls memory access operations and (computing) operations implemented by ALUs (9) in a coordinated manner. Control by the control unit (5) includes implementing a series of operations that are decomposed into computing cycles. Control includes generating a first cycle i and a second cycle ii. The first cycle i temporally precedes the second cycle ii. As described in more detail in the examples below, the second cycle ii may immediately follow the first cycle i, or alternatively, the first cycle i and the second cycle ii may be temporally separated from each other, for example, with intermediate cycles.

The first cycle i is,

- implementing a first computing operation through at least one ALU (9); and

- Includes downloading the first data set from memory (13) to at least one register (11).

The second cycle ii includes implementing a second computing operation via at least one ALU (9). The second computing operation may be implemented by the same ALU (9) as the first computing operation, or may be implemented by a separate ALU (9). At least a portion of the first dataset downloaded during the first cycle i forms an operand for the second computing operation.

Now, referring to Figure 3, some data or blocks of data are referenced as A0 to A15, respectively, and are stored in memory (13). In this example, data A0 to A15 are grouped together into four groups as follows:

- A dataset consisting of data A0, A1, A2 and A3 and referenced as AA0_3;

- A dataset consisting of data A4, A5, A6 and A7 and referenced as AA4_7;

- A dataset consisting of data A8, A9, A10 and A11 and referenced as AA8_11; and

- A dataset consisting of data A12, A13, A14, and A15, referenced as AA12_15.

As a variation, the data may be grouped together differently, particularly into more than two, three, or four groups (or "blocks" or "slots"). A dataset may be viewed as a group of data accessible on memory (13) via a single port of the memory interface (15) during a single read operation. Similarly, data in a dataset may be written to memory (13) via a single port of the memory interface (15) during a single write operation.

Thus, during a first cycle i, at least one dataset AA0_3, AA4_7, AA8_11 and/or AA12_15 is downloaded to at least one register (11). In the example in the figure, each of the datasets AA0_3, AA4_7, AA8_11 and/or AA12_15 is downloaded to a respective register (11), i.e., to four separate registers (11). Each of the registers (11) is at least temporarily assigned to a respective ALU (9), referred to herein as ALU 0, ALU 1, ALU 2 and ALU 3, respectively. During this one and the same cycle i, the ALUs (9) may have implemented computing operations.

During the second cycle ii, each ALU (9) implements a computing operation, during which at least one of the items of data stored on the corresponding register (11) forms an operand. For example, ALU 0 implements a computing operation, during which one of the operands is A0. A1, A2 and A3 may be unused during the second cycle ii.

Generally speaking, downloading data from memory (13) to registers (11) consumes less computing time than implementing computing operations via ALUs (9). Therefore, in general, a memory access operation (here, a read operation) may consume a single computing cycle, while implementing a computing operation via ALUs (9) may consume one computing cycle or a plurality of consecutive computing cycles (e.g., four computing cycles).

In the example of Fig. 3, there are a plurality of registers (11) assigned to each ALU (9), which are represented by groups of registers (11) referred to as REG A, REG B and REG C. Data downloaded from memory (13) to the registers (11) correspond to groups REG A and REG B. Group REG C is intended here to store data obtained through computing operations implemented by the ALUs (9) (during a write operation).

Accordingly, registers (11) of groups REG B and REG C may contain datasets referenced similarly to the registers of REG A as follows:

- Group REG B includes four registers (11), in which a dataset BB0_3 consisting of data B0 to B3, a dataset BB4_7 consisting of data B4 to B7, a dataset BB8_11 consisting of data B8 to B11, and a dataset BB12_15 consisting of data B12 to B15 are stored, respectively;

- Group REG C includes four registers (11), in which data set CC0_3 consisting of data C0 to C3, data set CC4_7 consisting of data C4 to C7, data set CC8_11 consisting of data C8 to C11, and data set CC12_15 consisting of data C12 to C15 are stored, respectively.

In the example of Figure 3, data AN and BN constitute operands for computing operations implemented by ALU (9), while items of data CN constitute results, where "N" is an integer between 0 and 15. For example, in the case of addition, CN = AN + BN. In this example, the data processing operations implemented by device (1) correspond to 16 operations. The 16 operations are independent of each other in that none of the results of the 16 operations is required to implement any of the other 15 operations.

Therefore, the implementation of a processing operation (16 operations) can be decomposed into, for example, 18 cycles as follows:

Example 1:

- Cycle #0: Read AA0_3;

- Cycle #1: Read BB0_3;

- Cycle #2: Compute C0 (from set CC0_3) and read AA4_7 (e.g. forming cycle i);

- Cycle #3: Compute C1 (from set CC0_3) and read BB4_7 (e.g. forming cycle i);

- Cycle #4: Compute C2 (from set CC0_3);

- Cycle #5: Compute C3 (from set CC0_3) and fill in CC0_3;

- Cycle #6: Compute C4 (from set CC4_7) and read AA8_11 (e.g. forming cycle ii);

- Cycle #7: Compute C5 (from set CC4_7) and read BB8_11 (e.g. forming cycle ii);

- Cycle #8: Compute C6 (from set CC4_7) (e.g., forming cycle ii);

- Cycle #9: Compute C7 (from set CC4_7) and write CC4_7 (e.g. forming cycle ii);

- Cycle #10: Compute C8 and read AA12_15 (from set CC8_11);

- Cycle #11: Compute C9 (from set CC8_11) and read BB12_15;

- Cycle #12: C10 Computing (from set CC8_11);

- Cycle #13: Compute C11 (from set CC8_11) and write CC8_11;

- Cycle #14: C12 Computing (from set CC12_15);

- Cycle #15: Compute C13 (from set CC12_15);

- Cycle #16: Compute C14 (from set CC12_15);

- Cycle #17: Compute C15 (from set CC12_15) and fill in CC12_15.

In this case, it should be understood that, except for initial cycle #0 and cycle #1, memory access operations (read and write operations) are implemented in parallel with the computing operations without consuming additional computing cycles. Reading datasets containing (multiple) pieces of data or blocks of data rather than reading a single item of data allows for data to be loaded from memory (13) into registers even before the data is needed as an operand for a computing operation.

In the example of Cycle #2 above, if only the item of data needed immediately (A0) was read, rather than reading the set AA0_3 = {A0; A1; A2; A3}, then three additional read operations would need to be implemented subsequently to obtain A1, A2, and A3.

For better understanding and comparison, an implementation of the processing operation is reproduced below, where a single data item is read each time, rather than a dataset containing (multiple) data items. It is observed that 48 cycles are required.

Example 0:

- Cycle #0: Read A0;

- Cycle #1: B0 ;

- Cycle #2: Compute C0 and write C0;

- Cycle #3: A1 Reading;

- Cycle #4: B1 Reading;

- Cycle #5: Compute C1 Write C1;

- ...

- Cycle #45: A15 reading;

- Cycle #46: B15 reading;

- Cycle #47: Compute C15 and write C15.

Note that in Case 1 (18 cycles), the first two cycles, Cycle #0 and Cycle #1, constitute initialization cycles. The number of initialization cycles (I) corresponds to the number of operands per computation. Next, a pattern of four consecutive cycles is repeated four times. For example, Cycles #2 to #5 together form a pattern. The number of cycles per pattern corresponds to the number of data per dataset (D), while the number of patterns corresponds to the number of datasets to be processed (E). Therefore, the total number of cycles can be expressed as I + D*E, as follows.

Achieving good performance means minimizing the total number of cycles. Therefore, under the conditions considered—that is, where each of the 16 independent basic operations can be implemented in a single cycle—the optimal number of cycles is equal to the number of basic operations (16) plus the initialization phase (two cycles), for a total of 18 cycles.

In one variation, the number of data accessible in a single cycle (either in read mode or in write mode) (the number of data per dataset (D)) is considered to be three (rather than four), for example, due to hardware limitations. In this case, the series of cycles can be decomposed, for example, as follows:

- Initialization phase of 2 cycles; then

- 5 patterns of 3 cycles for a total of 15 basic computing operations out of 16 to be performed; then

- The last cycle to compute and record the results of the last basic computing operation.

Example 2:

- Cycle #0: Read AA0_2={A0; A1; A2};

- Cycle #1: Read BB0_2={B0; B1; B2};

- Cycle #2: Compute C0 (from set CC0_2={C0; C1; C2}) and read AA3_5 (e.g. forming cycle i);

- Cycle #3: Compute C1 (from set CC0_2) and read BB3_5 (e.g. forming cycle i);

- Cycle #4: Compute C2 (from set CC0_2) and fill in CC0_2;

- Cycle #5: Compute C3 (from set CC3_5) and read AA6_8 (e.g. forming cycle ii);

- Cycle #6: Compute C4 (from set CC3_5) and read BB6_8 (e.g. forming cycle ii);

- Cycle #7: Compute C5 (from set CC3_5) and write CC3_5 (e.g. forming cycle ii);

- Cycle #8: Compute C6 (from set CC6_8) and read AA9_11;

- Cycle #9: Compute C7 (from set CC6_8) and read BB9_11;

- Cycle #10: Compute C8 (from set CC6_8) and fill in CC6_8;

- Cycle #11: Compute C9 and read AA12_14 (from set CC9_11);

- Cycle #12: Compute C10 (from set CC9_11) and read BB12_14;

- Cycle #13: Compute C11 (from set CC9_11) and write CC9_11;

- Cycle #14: Compute C12 (from set CC12_14) and read A15 (e.g., forming cycle i);

- Cycle #15: Compute C13 (from set CC12_14) and read B15 (e.g., forming cycle i);

- Cycle #16: Compute C14 (from set CC12_14) and write CC12_14;

- Cycle #17: Compute C15 (a separate item of data) and write C15 (e.g., forming cycle ii).

In Case 2, each cycle is observed to involve a memory access operation (either in read mode or in write mode). Therefore, if the number of data items (D) accessible within a single cycle is significantly less than three, it should be understood that additional cycles will be required to perform the memory access operations. Therefore, the optimal 18 cycles for 16 basic operations will no longer be achievable. However, even without optimization, the number of cycles remains significantly lower than the number of cycles required in Case 0. An embodiment in which the datasets include two data items represents an improvement over the existing implementation.

In Case 1, if Cycle #2 and/or Cycle #3 correspond to Cycle i, for example, as defined above, then Cycle #6, Cycle #7, Cycle #8, and Cycle #9 each correspond to Cycle ii. Naturally, this can change from pattern to pattern. In Case 2, if Cycle #2 and/or Cycle #3 correspond to Cycle i, for example, as defined above, then Cycle #5, Cycle #6, and Cycle #7 each correspond to Cycle ii. Naturally, this can change from pattern to pattern.

In the examples described so far, particularly in Cases 1 and 2, a particularly low overall number of cycles is achieved, since the maximum number of memory access operations is implemented per dataset containing (multiple) data, rather than in parallel with the computing operations and not in units. Thus, for some parts of the process (all parts in the optimized examples), read operations on all required operands can be achieved even before the preceding basic computing operation is finished. Preferably, computing power is saved by performing the computing operations in a common computing cycle (e.g., cycle #5 in Case 1) and writing the results of said computing operations (write operations).

In these examples, pre-reading of operand data is implemented throughout the process (repeatedly from one pattern to another). Operands required for computational operations performed during a pattern are automatically obtained (read) during the previous pattern. Note that in the degraded embodiments, pre-reading is only partially implemented (only for two consecutive patterns). Compared to the previous examples, this degraded mode also yields better results than existing methods.

In the examples described so far, it has been recognized that data is read before it can serve as operands. In some embodiments, the pre-read data is read randomly, or at least independently of future computing operations to be performed. Thus, at least some of the pre-read data from among the datasets effectively corresponds to operands for subsequent computing operations, while other read data is not operands for subsequent computing operations. For example, at least some of the read data may be subsequently erased from the registers (11) without being used by the ALUs (9), typically by other data that is subsequently written to the registers (11). Thus, some data is unnecessarily read (and unnecessarily written to the registers (11). However, to achieve savings in computing cycles, at least some of the data from the read datasets effectively becomes operands, thus improving the situation compared to what currently exists. Therefore, depending on the number of data to be processed and the number of cycles, there is a high probability (in the mathematical sense of the term) that at least some of the pre-fetched data can be effectively used as operands in computing operations performed by the ALU (9) in subsequent cycles.

In some embodiments, the pre-fetched data is pre-selected based on the computing operations to be performed. This allows for improved relevance of the pre-fetched data. Specifically, in the example with the 16 basic computing operations described above, each of the 16 basic computing operations requires a pair of operands at the input, A0 and B0; A1 and B1; ...; A15 and B15, respectively. If the data is read randomly, the first two cycles may correspond to the read operation on AA0_3 and BB4_7. In this case, the complete operand pair is not available in the registers (11) at the end of the first two cycles. Therefore, the ALUs (9) cannot implement any basic computing operation in the subsequent cycle. Therefore, one or more additional cycles are necessarily consumed on memory access operations before the basic computing operations can begin, thereby increasing the overall number of cycles and detrimentally affecting efficiency.

Calculating the chance and probability that data acquired in read mode is as relevant as possible is not entirely satisfactory, but it is sufficient to improve upon what currently exists. The situation can be further improved.

Implementing a prefetch algorithm ensures that all operands for the next computational operation are available as early as possible. In the previous example, reading AA0_3 and BB0_3 during the first two cycles ensures that all operands required to implement the first four basic computational operations are available in registers (11).

These algorithms receive, as input parameters, information data related to the computational operations to be subsequently performed by the ALUs (9), and in particular, related to the required operands. These algorithms enable selection of data to be read (per set) by predicting future computational operations to be performed at the output. These algorithms are implemented by the control unit (5), for example, when controlling memory access operations.

According to a first approach, the algorithm imposes organization on the data as soon as it is written to the memory (13). For example, data that is desirable to form a dataset is juxtaposed and/or ordered so that the entire dataset can be retrieved with a single request. For example, if the addresses of data A0, A1, A2, and A3 are referenced as @A0, @A1, @A2, and @A3, respectively, the memory interface (15) can be configured to automatically read data at the three subsequent addresses @A1, @A2, and @A3 in response to a read request for @A0.

According to a second approach, the prefetch algorithm provides, at the output, memory access requests that are adapted based on the computational operations to be subsequently performed by the ALUs (9), and in particular with respect to the operands required. In the preceding examples, the algorithm may identify that the data to be read first are data from AA0_3 and BB0_3, in order to enable, for example, the basic computational operations that provide the result CC0_3 (i.e., computing C0 with operands A0 and B0, computing C1 with operands A1 and B1, computing C2 with operands A2 and B2, and computing C3 with operands A3 and B3) as early as the subsequent cycle. Accordingly, the algorithm provides, at the output, memory access requests that are configured to trigger read operations with respect to AA0_3 and BB0_3.

The two approaches can optionally be combined, whereby the algorithm identifies the data to be read, and from this the control unit (5) derives memory access requests at the memory interface (15) to obtain said data, whereby the requests are adapted based on the characteristics (structure and protocol) of the memory interface (15).

In the above examples, particularly in Cases 1 and 2, the number of ALUs allocated to basic computing operations is undefined. A single ALU (9) may perform all basic computing operations in one cycle. The basic computing operations to be performed may also be distributed across multiple (e.g., four) ALUs (9) of the PU. In such cases, coordinating the distribution of computing operations across the ALUs by grouping together the data to be read in each read operation may enable further efficiency improvements. The two approaches are distinct.

In the first approach, the data read in one operation form operands within computing operations implemented by exactly one identical ALU (9). For example, groups AA0_3 and BB0_3 of data A0, A1, A2, A3, B0, B1, B2 and B3 are read first, and the first ALU is responsible for computing CC0_3 (C0, C1, C2 and C3). Next, groups AA4_7 (A4, A5, A6 and A7) and BB4_7 (B4, B5, B6 and B7) are read, and the second ALU is responsible for computing CC4_7 (C4, C5, C6 and C7). In this case, it should be understood that the first ALU can start implementing the computing operations before the second ALU can start implementing the computing operations, because the operands required for the computing operations of the first ALU will be available on the registers (11) before the operands required for the computing operations of the second ALU are present. In this case, the ALUs (9) of the PU operate in parallel and in an asynchronous manner.

In a second approach, the data read in one operation forms operands in computing operations that are each implemented by different (e.g., four) ALUs (9). For example, two groups of data are read first, each containing A0, A4, A8, and A12; and B0, B4, B8, and B12. The first ALU would be responsible for computing C0, the second ALU would be responsible for computing C4, the third ALU would be responsible for computing C8, and the fourth ALU would be responsible for computing C12. In this case, it should be understood that the four ALUs could begin implementing their respective computing operations substantially simultaneously, since the necessary operands would be available in the registers (11) as soon as they were downloaded in the common operation. The ALUs (9) of the PU operate in parallel and synchronously. Depending on the types of computations to be performed, the accessibility of data in memory, and available resources, one or the other of two approaches may be preferred. The two approaches can also be combined, such that the ALUs can be structured into subgroups (one subgroup of ALUs operating synchronously, and the other subgroups operating asynchronously with respect to each other).

To impose synchronous, asynchronous, or mixed operation of the ALUs, the grouping of data to be read per read operation must be chosen to correspond to the distribution of assignments of computing operations to the various ALUs.

In the preceding examples, the basic computational operations are independent of each other. Therefore, the order in which they are performed has no a priori significance. In some applications where at least some of the computational operations are dependent on each other, the order of the computational operations may be specific. This situation typically occurs in the context of recursive computing operations. In such cases, the algorithm can be configured to identify the data to be acquired (read) first. For example, if

- If the result C1 is obtained through a computing operation in which one of the operands is C0 and CO itself is obtained from the operands A0 and B0,

- If the result C5 is obtained through a computational operation in which one of the operands is C4 and C4 itself is obtained from the operands A4 and B4,

- If the result C9 is obtained through a computing operation in which one of the operands is C8 and C8 itself is obtained from the operands A8 and B8, and

- If the result C13 is obtained through a computational operation in which one of the operands is C12 and C12 itself is obtained from the operands A12 and B12,

During the first two initialization cycles #0 and #1, the algorithm computes the following datasets:

- {A0; A4; A8; A12}, and

- It can be configured to read {B0; B4; B8; B12}.

The dataset defined accordingly is shown in Fig. 4. Metaphorically, it can be said that the data is grouped together "in rows" in the embodiment shown in Fig. 3, and "in columns" in the embodiment shown in Fig. 4. Therefore, implementing the algorithm enables reading operands useful for the primary computing operations and making them available on the registers (11). In other words, implementing the algorithm enables increasing the short-term relevance of the read data compared to a random read operation.

The present invention is not limited to the examples of processing units and methods described above by way of example only, but rather includes all variations that a person skilled in the art would consider within the scope of the protection sought. The present invention also relates to a set of processor-implementable machine instructions for obtaining such a computing device, such as a processor or a set of processors, to implementing such a set of machine instructions on a processor, to a method for managing a processor architecture implemented by a processor, to a computer program comprising a corresponding set of machine instructions, and to a recording medium on which such a set of machine instructions is computably recorded.

Claims (10)

As a computing device (1),
The above computing device (1) is,
- a plurality of arithmetic logic units (9);
- A set of registers (11),
The above registers (11) can supply data of operand type to the inputs of the arithmetic logic units (9) and can receive data from the outputs of the arithmetic logic units (9);
- Memory (13) and;
- Memory interface (15),
Data (A0, A15) is transmitted and routed between the registers (11) and the memory (13) through the memory interface (15);
- Includes a control unit (5),
The control unit (5) is configured to control the arithmetic logic units (9) according to a processing chain microarchitecture so that the arithmetic logic units (9) perform computing operations in parallel with each other.
The above control unit (5) is also designed to control the memory access operations via the memory interface (15),
The control operations performed by the above control unit (5) are:
- at least one cycle i;
- generating at least one cycle ii subsequent to at least one cycle i,
wherein said at least one cycle i comprises, in parallel, implementing at least one first computing operation via the arithmetic logic unit (9) and downloading a first dataset (AA4_7; BB4_7) from the memory (13) to at least one register (11), wherein at least a part (A4; B4) of said first dataset (AA4_7; BB4_7) is not used by any computing operation of the arithmetic logic units (9) during said cycle i,
A computing device characterized in that said at least one cycle ii comprises implementing a second computing operation via an arithmetic logic unit (9), wherein during said second computing operation at least said part (A4; B4) of said first dataset (AA4_7; BB4_7) forms at least one operand. In the first paragraph,
A computing device characterized in that the control unit (5) is also configured to implement an identification algorithm for identifying the first dataset (AA4_7; BB4_7) to be downloaded during the at least one cycle i based on the second computing operation to be implemented during the at least one cycle ii before controlling the arithmetic logic units and the memory access operations. In the first paragraph,
The above control unit (5) is configured to implement two separate cycles i, so that two separate first data sets (AA4_7, BB4_7) are downloaded to at least one register (11),
A computing device characterized in that at least a portion (A4, B4) of each of said two first data sets (AA4_7, BB4_7) forms an operand for said second computing operation of said at least one cycle ii. In the first paragraph,
A computing device characterized in that the control unit (5) is configured to implement a plurality of cycles ii that are separated from each other, such that a part (A4; A5; A6; A7) of the first data set (AA4_7) forming at least one operand for the second computing operation of the cycle ii is configured to be different in one cycle ii and another cycle ii of the plurality of cycles ii. In the first paragraph,
The above control unit (5) is configured to perform at least two iterations of at least one cycle i and one cycle ii in a series,
A computing device characterized in that the two iterations are at least partially superimposed such that at least one cycle ii of the first iteration forms a cycle i of the subsequent iteration. In the first paragraph,
A computing device characterized in that the control unit (5) is configured to perform an initialization phase, which comprises downloading at least one data set (AA0_3; BB0_3) forming operands for the first computing operation of the first cycle i from the memory (13) to at least one register (11) prior to the first cycle i. In the first paragraph,
The above control unit (5) is also designed to control the memory access operations through the memory interface (15), so that the control operations are
- During cycle i, implementation of a plurality of first computing operations by a plurality of arithmetic logic units (9);
- designed to cause the implementation of a plurality of second computing operations by a plurality of arithmetic logic units (9) during cycle ii,
A computing device characterized in that the grouping of data for the dataset to be downloaded is selected to match the distribution of allocations of computing operations to each of the plurality of arithmetic logic units (9), such that the arithmetic logic units (9) are selected to have synchronized operation, asynchronous operation, or mixed operation. A data processing method implemented by a control unit (5) of a computing device (1),
The above device (1) is,
- Multiple arithmetic logic units (9);
- A set of registers (11),
The above registers (11) can supply data of operand type to the inputs of the arithmetic logic units (9) and can receive data from the outputs of the arithmetic logic units (9);
- Memory (13) and;
- Memory interface (15),
Data (A0, A15) is transmitted and routed between the registers (11) and the memory (13) through the memory interface (15);
- Including the above control unit (5),
The above control unit (5) is configured to control the arithmetic logic units (9) according to the processing chain microarchitecture so that the arithmetic logic units (9) perform computing operations in parallel with each other.
The above control unit (5) is also designed to control the memory access operations through the memory interface (15),
The above method comprises at least:
- generating cycle i;
- Including generating a cycle ii subsequent to the above cycle i,
The above cycle i comprises implementing at least one first computing operation via the arithmetic logic unit (9) and downloading a first data set (AA4_7; BB4_7) from the memory (13) to at least one register (11) in parallel, wherein at least a part (A4; B4) of the first data set (AA4_7; BB4_7) is not used by any computing operation of the arithmetic logic units (9) during the cycle i,
A data processing method, characterized in that the cycle ii comprises implementing a second computing operation via an arithmetic logic unit (9), during which at least a portion (A4; B4) of the first dataset (AA4_7; BB4_7) forms at least one operand. A computer program, characterized in that the computer program includes instructions for implementing a method as described in claim 8 when the computer program is executed by a processor. A non-transient computer-readable recording medium, wherein a program is recorded on the non-transient computer-readable recording medium, and the program is characterized in that the program is for implementing the method as described in claim 8 when the program is executed by a processor.