JPS6240554A - Buffer memory block prefetching system - Google Patents

Abstract

PURPOSE:To decrease a useless prefetch of a block by executing a prefetch processing of a block data, only when the next block of the block concerned is in the same page. CONSTITUTION:At the time of a buffer memory mishit processing, a registration to a buffer memory directory 17 is executed by the first request register 11, and thereafter, request information is sent to the second request register 12 and the third request register 13 again. In this case, when shifting a block from the register 12 to the register 13, a block address in a page is added by an addition counter 20 of the block address in the page. In this regard, when an overflow is generated at the time of this addition, a prefetch of a block data is terminated. That is to say, it is because as for the prefetch of the block data exceeding a page, its prefetch effect cannot be expected.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory control device that holds part of data in a main memory device and controls a buffer memory, and particularly relates to a block data preemption method thereof.

(Prior Art) Buffer memory, which holds part of the data in the main memory device and operates at a higher speed than the main memory device, is used in many devices because it can greatly improve the apparent memory performance. It is adopted in

In order to improve this apparent memory performance, K is
Probability that the required data exists in the buffer memory (
It is necessary to increase the buffer memory hit rate. For this purpose, the buffer memory capacity can be increased, but this has the problem of increasing the amount of hardware and reducing the speed of the buffer memory.

As a method of increasing the buffer memory hit rate without increasing the buffer capacity, pre-fetching of block data is conventionally known. Here, a block is a unit of data registered on the buffer memory. What is block pre-emption?
This is a processing method in which when a block is rarely accessed, the block at the next address is prefetched from the main memory device. This takes advantage of the fact that when a certain access occurs, there is a high probability that data near that address will be accessed in the near future, which is a characteristic of programs, and by preemptively storing data in the buffer memory before it is accessed. This is intended to improve the buffer memory hit rate.

(Problems to be Solved by the Invention) However, the above-described conventional block data preemption system has the following problems. When registering new block data from the main memory device to the buffer memory, it is necessary to register it in the buffer memory directory, determine the replacement location on the buffer memory, and write the block data to the buffer memory. However, this has the disadvantage that other buffer memory access processing is hindered and delayed. Further, the main memory device is also burdened with reading the block data, which hinders other accesses. If most of the prefetched block data is used by subsequent accesses, there will be no ambiguity loss, and the effect of improving the buffer memory hit rate will be large, but if the rate of block data used by subsequent accesses is low, there will be a loss in performance. The disadvantage is that it can lead to

An object of the present invention is to improve the usage rate of preempted data in subsequent accesses in order to increase the effectiveness of block data prefetching, and to create an environment in which block data prefetching 9 processing is less likely to interfere with subsequent buffer memory access processing. By performing the above-mentioned pre-fetching, the above-mentioned disadvantages are eliminated, and even under high frequency of read/write access to the buffer memory, the block data pre-fetching process is configured to avoid the influence on subsequent buffer memory access processing. The purpose of the present invention is to provide a buffer memory block preemption method.

(Means for Solving the Problems) The buffer memory block preemption method according to the present invention includes one or more arithmetic control devices, one or more input/output control devices,
An information processing system including one or more main memory devices and a memory control device for receiving memory requests from an arithmetic control device and an input/output control device and mediating memory access to the main memory device, , the memory control device comprises a buffer memory, address addition means, and index prefetch means.

Pack-a-memory is for holding a copy of a portion of the data in the main memory device.

The address addition means is used when processing a memory request, when the target data does not exist in the buffer memory, or even if it exists, the memory request is the first access to the prefetched buffer memory block, the buffer memory block to which the data belongs This is to add the request address for the next block address.

If the actual page number part of the request address does not change due to the addition and only the intra-page address changes, the index preemption means uses the address of the addition result to index whether or not the corresponding buffer memory block is registered in the buffer memory. , to prefetch the buffer memory block onto the buffer memory when the index result is null.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the buffer memory block preemption method according to the present invention, and FIG. 2 is an explanatory diagram showing an example of the information format inside the buffer memory directory of FIG. 1. .

In FIG. 1, 101 and 102 are respectively quest reception circuits, 11 is a first request register, 12 is a second request register, 13 is an eighth request register, 14 is a main memory access register, and 15 is a write Data register, 16 is read data register, 11
18 is a buffer memory directory, 191 to 195 are pre-emption instruction bits, 20 is an addition counter, and 22 is a directory register.

In FIG. 1, the memory control device 5 includes the arithmetic control device 1,
Alternatively, request information such as a memory request from the input/output control device 2, its request type, request address, and write data is sent to the signal 1601.
502 and performs memory access processing to the main memory device 4.

The portable memory control device 3 of the present invention is equipped with a buffer memory 18. The high speed ratio of large information processing systems has progressed with advances in semiconductor device technology, but
Although the processing speed of the arithmetic control unit 1 and the input/output control unit 2 has improved, the processing speed of the memory elements of the main memory device 4 has not been improved relatively. Therefore, not only the inside of the arithmetic and control device 1 but also the memory control device 3 has a buffer memory 1 which has a slower processing speed but a larger capacity than the arithmetic and control device 1.
8, the apparent memory access performance is improved.

Next, the internal operation of the memory control device 3 will be explained.

A signal line 501.
Request information sent via 502 is accepted by circuits 101 and 102. For request reception, the circuits 101 and 102 are not limited to the example shown in FIG. When multiple L1s and input/output control devices 2 are installed, requests are accepted by the circuit 10.
2 will further increase in number. Request reception is at circuit 10
One request is selected from the request group accepted by 1° 102, and the request information is entered into the first request register 11.

In the first request register 11, indexing of the buffer memory (IJIT) is performed.

Buffer memory directory 17 contains buffer memory 1.
The address information of the main memory device data held in 8 is registered, and by indexing this, it is possible to determine the presence or absence of the required data on the buffer memory 18 (referred to as buffer memory hits and buffer memory misses). ), as well as information on the location when the data exists on the buffer memory 18 are obtained in the directory register 22.

When a buffer memory miss occurs, a block data successive retrieval request is sent to the main memory device 4 from the main memory access register 14 via the second request register 12. The block data read from the main memory device 4 via the signal line 52 is written to the buffer memory IJ 18K via the write data register 15, and further required data is sent via the read data register 16 as a memory request. returned to the device.

On the other hand, if requests are processed in parallel and a buffer memory miss occurs, the request information is transferred to the first request register via the second request register 12 and the eighth request register 1S. 11, and the block address is registered in the buffer memory directory 17 so that subsequent memory requests to the same block will result in a buffer memory hit.

The W2B diagram shows one form of the contents of the buffer memory directory 17, where each entry in the buffer memory directory 17 includes v, p, and address information, and the buffer memory directory 11 is composed of a large number of entries. Each entry corresponds to each block of the buffer memory 1B, the ■ bit indicates the validity of the buffer memory block data, and the address indicates the main memory device address information of the block data. The P bit is a bit added for block data prefetching, and when the P bit is on, it indicates that the above block is a preempted block that has not yet been accessed by a memory request. There are 0 stores in (5 stores)
-in) method (in the rough memory directory 17, there is also a modified pick) M. When a buffer memory miss occurs due to a memory request from the arithmetic and control unit 1 and the buffer memory directory 1 is registered as described above, the P bit is registered as an OFF state.

In this embodiment in which block data is fetched in advance, the following operations are further performed during buffer memory miss processing.

After the first request register 11 registers the request information in the buffer memory directory 17, the request information is sent again to the second request register 12 and then to the eighth request register 13.

At this time, when the block is transferred from the second request register 12 to the third request register 15, the in-page block address addition counter 20 adds the in-page block address to the request address.

A logical address method is generally adopted in large-scale information processing systems, but in such systems, the arithmetic and control unit 1
Execution of instructions at a logical address or, depending on the system, input/output data transfer is also performed on a logical address. The logical address space is divided into a large number of pages, and the relationship between the logical page number at the logical address and the real page number at the real address, which is the memory address of the main memory device 4, is established inside the arithmetic control unit 1. A fast address translation buffer is provided. Here, the address within the logical page is the same as the address within the real page.

Generally, the page size is 2 bytes or 4 bytes.
The block size of the buffer memory 18 is often about 82 bytes to 128 bytes.

A nearby address on a program is a nearby address on a logical address, and does not mean a nearby address on a real address. In other words, an adjacent block on a real address is also an adjacent block on a logical address as long as it is within the same page, but if the page numbers are different, it is not necessarily an adjacent block on a logical address.

In the above sense, prefetching block data that exceeds a page has no effect. Therefore, if an overflow occurs when the addition counter 20 adds up the block address within the page to JL, the prefetching of the block data is stopped in this embodiment.

When no overflow occurs, the request address added to indicate the next block address is the 8th block address.
is sent from the request register 13 to the first request register 11, and the first request register 11 indexes the buffer memory directory 'J L 7 again. If there is a buffer memory hit, the process ends, but if there is a miss, a block data read request to the memory device 4 and registration to the buffer memory 18 are performed as described above. Here, the P bit to the buffer memory directory 17 is turned on and registered. This indicates that this block has been pre-empted and has not yet been accessed by an actual memory request.

The above is the process when a memory request from the arithmetic control unit 1 or the input/output control unit 2 results in a buffer memory miss. Next, the process when a buffer memory hit occurs will be explained.

The buffer memory directory 17 is first indexed in the first request register 11, but when the request is a read request, the address and directory register 22 are sent via the second request register 12.
Buff candy with information.

The required data is read from the memory 18 and returned via the read data register 16 to the device that sent the memory request. When the request is a write request, the second
The data in the write data register 15 is written into the buffer memory 18 specified by the address via the request register 12 and the information in the directory register 22.

The P bit of the hit entry is checked when the buffer memory directory 11 is accumulated from the first request register 11. If the P bit is off, preemption of block data can be suppressed, but if the P bit is on, the P bit is checked. Second
The request information is returned to the first request register 11 via the request register 12 and the eighth request register 13, and processing when the P bit of the corresponding entry in the buffer memory directory 17 is turned off is performed. Further, when the P bit is on, it is 1, and block data prefetch processing is performed in the same way as when there is a buffer memory miss. That is, the request address is added by the in-page block address addition kakunme 20, and when no overflow is detected, the added address is indexed in the buffer memory directory 17. As a result of the indexing, if there is a miss in the buffer memory 18, block data is prefetched, and the newly prefetched block turns on the P bit and is stored in the buffer memory directory 1.
7 and buffer memory 18.

(Effects of the Invention) As explained above, in the present invention, in processing the buffer memory installed between memory control devices, the block to which a memory request to the memory control device belongs and the block next to this block are within the same page. By performing preemptive ML processing on block data only when
This reduces unnecessary block prefetching, and since block data prefetching within the memory control unit does not interfere with buffer memory hit processing within the arithmetic control unit, it increases the effect of block data prefetching and improves the block data prefetching within the memory device. Performance can be improved by improving the buffer memory hit rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the buffer memory block prefetching method according to the present invention. FIG. 2 is an explanatory diagram showing an example of the information format inside the buffer memory directory of FIG. 1. 1... Arithmetic control device 2... Input/output control device 3... Memory control device 4φ... Main memory device 101.102... Request reception is performed by circuits 11 to 15
---Request register 14, main memory access register 15, e-write data register 16, continuation data register 17, φ, buffer memory directory 18, buffer memory 191 to 193, preemption υ instruction Bit 20...addition counter

Claims (1)

[Claims] one or more arithmetic control devices, one or more input/output control devices, one or more main memory devices, and receiving a memory request from the arithmetic control device and the input/output control device to the main memory device; a buffer memory block prefetching method in an information processing system, the buffer memory block prefetching method comprising: a memory control device for mediating memory access of the main memory device; , when processing a memory request, if the target data does not exist in the buffer memory, or even if it does exist, the memory request is the first access to the prefetched buffer memory block, the next buffer memory block to which the data belongs address adding means for adding a request address to obtain a block address; and when the actual page number part of the request address does not change due to the addition and only the intra-page address changes, the address of the addition result; index prefetching means for indexing whether or not a corresponding buffer memory block is registered in the buffer memory, and prefetching the buffer memory block onto the buffer memory when the result of the index is null. A buffer memory block prefetching method is characterized in that it is configured as follows.