CN107656880B - Processor with memory controller including dynamically programmable functional units - Google Patents

Abstract

A processor having a memory controller including a dynamically programmable functional unit, the processor including a memory controller, wherein the memory controller is to interface an external memory with a Programmable Functional Unit (PFU). The PFU is programmed with a PFU program to modify operation of the memory controller, wherein the PFU includes programmable logic elements and programmable interconnects. For example, the PFU is programmed with a PFU program to add functionality during operation of the processor or otherwise modify existing functionality of the memory controller to enhance the functionality of the memory controller. Thus, once the processor is manufactured, the functions and/or operations of the memory controller are not fixed, but instead the memory controller may be modified after manufacture to improve the efficiency of the processor and/or enhance the performance of the processor, such as when executing corresponding processes.

Description

Processor with memory controller including dynamically programmable functional units

technical field

The present invention relates generally to programmable resources of processors, and more particularly to processors having dynamically programmable functional units at the memory controller level.

Background technique

Processors continue to become more powerful, with these processors having higher performance at higher efficiency levels. The term "processor" as used herein refers to any type of processing unit including a microprocessor, a central processing unit (CPU), one or more processing cores, a microcontroller, and the like. The term "processor" as used herein also includes any type of processor configuration such as a processing unit integrated on a chip or integrated circuit (IC), including those contained within a system-on-chip (SOC) chips or integrated circuits. Semiconductor manufacturing techniques are continuing to improve, resulting in increased speed, reduced power consumption, and reduced size of circuits integrated on processing chips. The reduction in integration size allows additional functionality to be incorporated within the processing unit. However, once a conventional processor is manufactured, many of its internal functions and operations are essentially fixed.

The memory controller provides the interface between the processor and external system memory, typically configured as dynamic random access memory (DRAM). Although the memory controller may be provided separately, in many modern conventional processing configurations the memory controller may be integrated into the same chip or IC as the processor with input/output (I/O) interface to external system memory superior. In a conventional configuration, once the processor is manufactured, the function of the memory controller is essentially fixed.

SUMMARY OF THE INVENTION

A processor according to one embodiment includes a memory controller for interfacing an external memory and a programmable function unit (PFU). The PFU is programmed with a PFU program to modify the operation of the memory controller, where the PFU includes programmable logic elements and programmable interconnects. For example, the PFU is programmed with a PFU program to add functionality or otherwise modify the existing functionality of the memory controller during operation of the processor, thereby enhancing the functionality of the memory controller. As such, once the processor is manufactured, the function and/or operation of the memory controller is not fixed, but instead, the memory controller may be modified after manufacture to increase the efficiency of the processor and/or such as when executing corresponding processes Enhance the performance of the processor.

The processor includes local memory for storing PFU programs. The local memory may be random access memory (RAM) for storing PFU programs retrieved from external memory. The processor may respond to a write command that instructs the processor to write the PFU program from external memory to random access memory. The processor may also include a PFU programmer for programming the PFU using the PFU program stored in the PFU memory. The PFU memory may be or may include read only memory (ROM) for storing at least one predetermined PFU program for programming the PFU to operate according to a predetermined PFU definition. For example, the PFU program may be the default PFU program that is used by the PFU programmer to program the PFU at startup of the processor. Alternatively or additionally, the processor may respond to program commands for causing the PFU programmer to program the PFU with a specified PFU program of a plurality of PFU programs stored in the PFU memory. A configuration map may be included, wherein the configuration map is used to map each of the plurality of different processing modes with a corresponding PFU program of the plurality of PFU programs stored in the PFU memory.

Programmable logic elements and programmable interconnects may be subdivided into substantially the same multiple programmable segments. A PFU programmer may be included, wherein the PFU programmer is used to assign the plurality of programmable sections and use the PFU program to program the allocated plurality of programmable sections to program the PFU.

Programmable logic elements may include programmable look-up tables. Additionally or alternatively, programmable logic elements may include adders, multiplexers, and registers. The PFU may include programmable memory, where in the programmable memory, the PFU program may be a stream of bits scanned into the programmable memory of the PFU. The PFU may be programmed with multiple PFU programs, and may include a PFU programmer for enabling at least one of the PFU programs at a time during operation of the processor.

As a more specific, non-limiting example, a PFU program may program the PFU to perform encryption functions for encrypting data stored in external memory. The encryption function may include an encryption function and a reverse encryption function, wherein the reverse encryption function employs a predetermined key combined with an address to develop a padding value that is further combined with the data value.

A method for providing a programmable memory controller of a processor, the programmable memory controller interfacing the processor with an external memory, the method comprising the steps of: incorporating a programmable logic element and a programmable interconnect A programmable function unit (PFU) of the connector is incorporated into the memory controller; and the PFU is programmed with a PFU program to modify the operation of the memory controller.

The method may include storing the PFU program in a local memory of the processor. The method may also include executing a write command with the processor, wherein the write command is used to instruct the processor to write the PFU program from the external memory to random access memory of the local memory . The method may include providing a PFU programmer and a PFU engine within the PFU, wherein the PFU programmer uses the PFU program stored in the local memory to program the PFU engine. The method may include executing, with the processor, program commands for instructing a PFU programmer to program a PFU engine with a PFU program stored in a PFU memory. The method may include setting a configuration map in the PFU, wherein the configuration map is used to map each processing mode in a plurality of different processing modes with a corresponding PFU program in a plurality of PFU programs stored in the PFU memory. .

The method may include: subdividing the programmable logic element and the programmable interconnect into substantially the same plurality of programmable sections; allocating a plurality of the programmable sections to be used according to the PFU program to configure the PFU; and to program the assigned plurality of the programmable sections with at least one PFU program. The method may include: setting the PFU as a programmable memory; and scanning the at least one PFU program as a bitstream into a programmable memory of a PFU engine. The method may include: programming the PFU with a plurality of PFU programs; and enabling at least one of the plurality of PFU programs at a time during operation of the processor.

Description of drawings

The benefits, features and advantages of the present invention will be better understood with reference to the following description and accompanying drawings, wherein:

1 is a simplified block diagram of a processor including a programmable function unit (PFU) coupled to external memory and memory devices implemented in accordance with one embodiment of the present invention;

Figure 2 is a more detailed block diagram of the PFU of Figure 1 implemented in accordance with one embodiment of the present invention;

3 is a simplified block diagram of the PFU programmer and controller of FIG. 2 engaged with the PFU engine, implemented using programmable logic, in accordance with one embodiment of the present invention;

4 is a block diagram illustrating a method for initially programming the PFU of FIG. 1 according to one embodiment of the present invention;

5 is a simplified block diagram depicting an executable binary application that may be used to program or otherwise reprogram the PFU of FIG. 1 according to one embodiment of the present invention;

6 is a more detailed block diagram of the programmable logic of FIG. 3 implemented in accordance with one embodiment of the present invention;

FIG. 7 is a schematic block diagram of the programmable logic element of FIG. 6 implemented according to an embodiment of the present invention;

8 is a schematic diagram of the LUT of FIG. 7 implemented according to an embodiment of the present invention;

Figure 9 is a simplified block diagram of the format of the PFU program for programming the PFU engine of Figure 2 according to one embodiment of the invention;

10 is a simplified block diagram illustrating an exemplary method for generating the PFU program of FIG. 1 for programming the PFU engine of FIG. 2 according to one embodiment of the present invention;

11 is a simplified block diagram illustrating an exemplary encryption process that may be programmed into the PFU and performed by the MC when storing data to the system memory of FIG. 1; and

12 is a simplified block diagram illustrating the reverse encryption process that may be programmed into the PFU and performed by the MC when data is loaded from the system memory of FIG. 1 .

Detailed ways

The inventors have recognized possible limitations associated with predetermined memory controllers present in conventional processors. Accordingly, the present inventors have developed a processor with a memory controller that includes a programmable functional unit (PFU), wherein the programmable functional unit (PFU) is configurable or otherwise programmable to modify or otherwise way to enhance the operation of the memory controller. A basic input/output system (BIOS) or operating system (OS) may include configuration information for programming the PFU. The BIOS may copy this configuration information into memory and send commands to the PFU to access the configuration on power-up, reset, or reboot, etc. (here called POR), or the OS (in the case where the BIOS is loaded during boot after the BIOS) information. Additionally or alternatively, the programmer or developer of a particular software program, process or application may incorporate the PFU program into the application used to program the PFU to modify or enhance the operation of the memory controller used by that particular application. As an example, the PFU may be configured to perform programmed encryption functions when written to or read from external system memory used by the processor.

1 is a simplified block diagram of a processor 100 including a programmable function unit (PFU) 114 coupled to external memory and memory devices, implemented in accordance with one embodiment of the present invention. The standard instruction set architecture (ISA) of the processor 100 may be the x86 architecture, where most applications designed to execute on an x86 processor can be properly executed. If the expected results are obtained, the application is executed correctly. In particular, processor 100 executes instructions of the x86 instruction set and includes the x86 user-visible register set. However, the present invention is not limited to the x86 architecture, such that the processor 100 may be implemented according to any alternative ISA as known to those of ordinary skill in the art.

Processor 100 includes 4 slices individually labeled S0, S1, S2, and S3 (S0-S3), where it should be understood that the number of slices is arbitrary and includes only one (1) and up to any positive value. integer number. Each slice S0-S3 includes a corresponding core in the four cores C0, C1, C2 and C3 (C0-C3), four cache memories or "last level caches" LLC0, LLC1, LLC2 and LLC3 (LLC0-LLC3 ), and the corresponding ring stations in the four ring stations R0, R1, R2, and R3 (R0 to R3). Each core C0-C3 includes one or more internal cache memories (eg, one or more L1 caches and L2 caches not shown, etc.) coupled to respective ones of the ring stations R0-R3 , wherein the corresponding ring station is further coupled to a corresponding one of the last level caches LLC0 ˜ LLC3 . It should be understood that the processor 100 may be configured as a single-core processor, a central processing unit (CPU), or a microprocessor, rather than multiple slices with multiple cores.

The processor 100 also includes an "uncore" 102 with a corresponding ring station RSU and a memory controller (MC) 104 with a corresponding ring station RSM. Ring stations R0 - R3 , RSU and RSM are coupled together in a ring configuration to enable communication between partitions S0 - S3 , uncore 102 and memory controller 104 . As shown, for example, RS0 communicates bidirectionally with RS1, RS1 communicates bidirectionally with RSM, RSM communicates bidirectionally with RS2, RS2 communicates bidirectionally with RS3, RS3 communicates bidirectionally with RSU, and RSU communicates bidirectionally with RS0. The particular ordering of ring stations in a ring configuration is arbitrary in view of ring and bidirectional communication, with the configuration shown being only one of many possible alternative configurations.

uncore 102 contains or otherwise interfaces functions of processor 100 that are not located in any of the partitions S0-S3 or corresponding cores C0-C3, but should be tightly coupled to these cores to achieve the desired level of performance . In the configuration shown, for example, uncore 102 is provided to interface with an external read only memory (ROM) 106 , which typically includes a basic input/output system (BIOS) 108 . BIOS 108 is firmware executed at POR of processor 100 for hardware initialization during POR to provide runtime services to operating system (OS) 120 and programs or applications. The uncore 102 is also arranged to interface with external memory 110 , which may include any number of data storage devices such as one or more hard drives, optical drives, flash drives, etc., and typically stores the OS 120 .

MC 104 interfaces processor 100 to external system memory 112 . The partitions S0-S3 share the resources of the system memory 112, and can also share information with each other via the ring stations RS0-RS3, RSU, RSM. System memory 112 may be implemented using suitable memory devices or chips, such as one or more dynamic random access memory (DRAM) chips.

The MC 104 also includes a PFU 114, where the PFU 114 can be programmed to modify or otherwise enhance the functionality of the MC 104. PFU 114 may be programmed in any of a number of ways depending on the details of the configuration. In one case, BIOS 108, after initializing memory 110 and system memory 112, accesses a PFU program (PGM) 116 stored in memory 110 and copies the PFU program 116 to memory on processor 100 or copies to system memory 112. For example, after copying, a copy of PFU program 116 is shown as PFU program 118 stored in system memory 112 . In one embodiment, the PFU program 116 may be stored in an encrypted and/or compressed format, wherein when the PFU program 116 is stored in memory on the processor 100 or in the system memory 112, the The PFU program 116 performs decryption and/or decompression. However, as described further herein, the PFU program 116 may be in the form of a bitstream that includes a series of logical ones (1) and zeros (0) without decryption or compression. The BIOS 108 then sends commands or instructions or the like to the PFU 114 to locate and program the PFU 114 itself with the copied PFU program 118 . Once programmed, the PFU 114 can modify or enhance the operation of the MC 104 during operation of the processor 100 .

In another case, after the BIOS 108 is executed, the OS 120 is loaded into the processor 100 and installed on the processor 100, and during the OS installation, the OS 120 copies the PFU program 116 and then instructs the PFU 114 to utilize, for example, the PFU program 116. PFU programs such as program 118 locate and program themselves to perform substantially the same process. In yet another case, a program or application or the like performs a similar process, wherein in this process the application contains the PFU program 116 and the application instructs the PFU 114 to use the copied PGM information, such as the PFU program 118, etc. to locate itself and to program. In another embodiment, PFU 114 includes local memory (eg, local memory 206 of FIG. 2 ) for storing PFU programs 118 . In this case, the BIOS 108, OS 120, or application performs a similar programming process, except that the PFU program 118 is stored in the local memory 206 of the PFU 114, and the PFU 114 accesses the PFU program 118 from its local memory for programming.

FIG. 2 is a more detailed block diagram of PFU 114 implemented in accordance with one embodiment of the present invention. The PFU engine 202 is provided, wherein the PFU engine 202 is programmed with the PFU program 118 to modify and/or enhance the operation of the MC 104 . A PFU programmer and controller 204 may be included in the PFU 114 for managing and/or controlling the operation of the PFU engine 202 , including programming the PFU engine 202 . The PFU programmer and controller 204 accesses the identified one or more PFU programs for programming the PFU engine 202 and enables programming of at least one of the one or more PFU programs into the PFU engine 202 . The PFU programmer and controller 204 are shown as separate units, and may be contained within the PFU engine 202 itself. In one embodiment, PFU 114 does not include local memory 206, in which case system memory 112 may be used to store PFU program 118. Without local memory 206, BIOS 108, OS 120, or an application sends a programming command identifying the location of PFU program 118 in system memory 112, and PFU programmer and controller 204 accesses PFU program 118 from system memory 112 and The PFU engine 202 is programmed.

In one embodiment, the PFU engine 202 may be configured with sufficient resources to be programmed with multiple PFU programs, with the PFU programmer and controller 204 programming each PFU program into the PFU engine 202 and only activating or enabling and The appropriate PFU program associated with the particular process in execution or the particular mode of operation of the processor 100 . As an example, the PFU engine 202 may initially be programmed at POR and enabled for most operations of the processor 100 . A process (eg, program or application, etc.) may program the PFU engine 202 with another PFU program for use while the process is active and executing. The PFU programmer and controller 204 manages the operation of the PFU engine 202 by activating only one of the PFU programs programmed into the PFU engine 202 at a time. In configurations without local memory, the PFU engine 202 may be programmed with a limited number of PFU programs.

It should be appreciated that the PFU engine 202 may be a limited resource that can load a limited number of PFU programs at any given time. The PFU engine 202 may not have sufficient capacity to be programmed with the total number of PFU programs that can be activated at any given time during operation of the processor 100 . In such a configuration, particularly where location information for one or more of the PFU programs within system memory 112 may no longer be valid or may not be available, it may be difficult to target different Modes are switched by programming of the PFU engine 202 with different PFU programs. Furthermore, the PFU engine 202 may include sufficient resources to be programmed with only one large PFU program or two smaller PFU programs depending on its implementation.

In another embodiment, the PFU 114 includes a local memory 206 for storing at least one PFU program used to program the PFU engine 202 . Local memory 206 may include random access memory (RAM) 208 , where in this case PFU program 116 may be copied to RAM 208 and accessed by PFU programmer and controller 204 to program PFU engine 202 . In one embodiment, RAM 208 may be of sufficient size to store multiple PFU programs shown as PGMA, PGMB, PGMC, and the like. In response to program commands, the PFU programmer and controller 204 access the identified ones of the PFU programs to program the PFU engine 202 . In this way, if the PFU engine 202 does not have sufficient resources to hold all PFU programs that can be activated at any time, the PFU programmer and controller 204 can reprogram the PFU engine 202 from local memory 206 on the fly in response to a command or in response to a mode change .

Local memory 206 may also include read only memory (ROM) 210 for storing one or more standard or predetermined PFU programs, shown as PGM1, PGM2, PGM3, and so on. In one embodiment, one of these predetermined PFU programs is designated as the default PFU program (eg, PGM1). During initial startup of processor 100, instead of copying PFU program 116 from memory 110 (or in addition to copying PFU program 116 from memory 110), BIOS 108 or OS 120 instructs PFU programmer and controller 204 to utilize the default PFU program (including case) to program the PFU engine 202, and then activate the default PFU program of the PFU engine 202. Alternatively or additionally, BIOS 108 , OS 120 , or any application or process may recognize any of the predetermined PFU programs stored in ROM 210 to program PFU engine 202 .

To facilitate multiple PFU procedures, a PFU configuration map 212 may be provided, wherein the PFU configuration map 212 maps a particular mode of operation of the processor 100 with the corresponding PFU procedure set for that mode. The operating mode may include process identification information if the particular process employs the corresponding PFU program. As shown, for example, multiple modes are identified as M1, M2, M3, M4, etc., respectively associated with corresponding PFU programs PGMA, PGM1, PGM2, PGMB, etc., respectively. The PFU programmer and controller 204 updates the PFU configuration map 212 each time a PFU program is programmed into the PFU engine 202 . According to the mapping set in the PFU configuration map 212, the PFU programmer and controller 204 identifies an active mode (or process) at any given time and activates the corresponding PFU program programmed into the PFU engine 202, or otherwise The PFU engine 202 is programmed. Once the correct PFU program is loaded and/or activated, the PFU engine 202 is utilized to modify or enhance the operation of the MC 104 accordingly.

In this way, the PFU programmer and controller 204 can map each mode (or process) with a corresponding PFU program unless or until replaced by another mode. In response to each subsequent programming command or mode change, PFU programmer and controller 204 utilizes the identified predetermined PFU program from ROM 210 or RAM 208 to activate or otherwise program PFU engine 202, and then accordingly. to update the PFU configuration map 212. In particular, the PFU programmer and controller 204 consults the PFU configuration map 212 and determines whether the PFU program associated with the corresponding mode has been loaded into the PFU engine 202. If the PFU program associated with the corresponding mode has been loaded into the PFU engine 202, the PFU programmer and controller 204 deactivates the current PFU program (if present) and activates the PFU engine 202 for the active mode within the next PFU program. If the PFU engine 202 is not loaded with a PFU program suitable for the new mode, the PFU programmer and controller 204 accesses the RAM 208 or ROM 210 storing the identified PFU program and programs the PFU engine 202 accordingly.

In one embodiment, the PFU programmer and controller 204 identifies whether the PFU engine 202 has enough free space to program the next PFU program without overwriting any PFU programs currently loaded within the PFU engine 202. If the PFU engine 202 has the free space, the next PFU program is loaded into the free space. However, if the PFU engine 202 does not have enough free space to load the next PFU program, the PFU programmer and controller 204 uses a replacement strategy to overwrite one or more PFU programs currently residing within the PFU engine 202. The replacement strategy may be a least recently used (LRU) algorithm or the like, but may also take into account the amount of programmable space required by the PFU program being loaded. For example, if a smaller least recently used PFU program does not provide enough space for the next PFU program to be loaded, the larger PFU program may be selected and overwritten despite being used more recently PFU program. In one embodiment, if a copy of any PFU program being overwritten within PFU engine 202 is not stored in ROM 210 or RAM 208, and if RAM 208 has sufficient storage space available, the PFU program is overwritten in PFU engine 202 Previously, the PFU programmer and controller 204 could unload or copy the PFU program from the PFU engine 202 into the RAM 208 .

Although RAM 208 can store a considerable number of PFU programs, in cases where RAM 208 is not large enough to store all of the PFU programs attempted to be downloaded at any given time, PFU programmer and controller 204 can take appropriate action. For example, if a process attempts to configure an undiscovered or unavailable PFU program, the PFU programmer and controller 204 may disable operation of the PFU engine 202 for that process only. Alternatively, the PFU programmer and controller 204 may load or otherwise activate standard PFU programs, such as the default PFU program PGM1, as long as any other PFU programs are not permanently overwritten.

3 is a simplified block diagram of a PFU programmer and controller 204 interfacing with a PFU engine 202, implemented using programmable logic 301, in accordance with one embodiment of the present invention. In the illustrated embodiment, programmable logic 301 is subdivided into a set of "P" substantially identical programmable sections 303, shown as programmable sections P1, P2, . . . , PP, where "P" is a positive integer. PFU programmer and controller 204 programs one or more PFU programs into programmable logic 301 . In particular, the PFU programmer and controller 204 allocates one or more programmable sections 303 of the programmable sections 303 sufficient to program the PFU program, and then loads the PFU program into the allocated section 303 to Corresponding PFU functions are implemented in the PFU engine 202 . The PFU programmer and controller 204 maintains pointers, etc. to identify and locate the various PFU programs loaded into the PFU engine 202, and activate or deactivate the loaded PFU programs based on the operating mode or active process.

Programmable logic 301 may be a relatively large resource, such as implemented by a field programmable gate array (FPGA) or the like, to program multiple PFU programs at once for each of multiple application processes. However, programmable logic 301 is a limited resource as the remaining unallocated sections 303 may not be sufficient to program the new PFU program to be programmed. In this case, the PFU programmer and controller 204 has no copy in RAM 208, and if sufficient space is available in RAM 208, copy the existing PFU program from programmable logic 301 to RAM In 208, the allocated section 303 can then be programmed with the new PFU program. In the event that a process has completed operations, causing the process to terminate, or in the event of a mode switch, within the PFU engine 202 and/or RAM 208, any PFU programs that have been programmed for that process may be invalidated and eventually cover.

Each programmable section 303 may include programmable logic sufficient to perform a simple PFU program. As shown, for example, the first PFU program PGMA (relatively simple) is loaded into the first programmable section P1 to implement the first program PFUA, and the second PFU program PGMB (more complex) is loaded into the two programmable sections P1 Sections P2 and P3 are programmed to implement the second program PFUB. Additionally, even more complex PFU programs can be loaded into more than two sections 303 . Depending on the relative size and complexity of the PFU programs and the total number of programmable sections 303, any number of PFU programs may be programmed into programmable logic 301.

In one embodiment, the PFU programmer and controller 204 performs dynamic allocation, wherein the PFU programmer and controller 204 identifies the next section 303 available for allocation, and when a new PFU program is scanned, programming begins. If the PFU program proceeds after the first allocation section 303 has been fully programmed such that additional sections 303 are required to complete the programming, the additional sections are dynamically allocated on the fly until the PFU program is fully programmed into the PFU engine 202 . In an alternate embodiment, the PFU programmer and controller 204 first evaluates the size of the new PFU program and allocates the appropriate number of programmable segments 303 accordingly prior to programming. In another alternative embodiment, a PFU program may be configured to include a resource declaration (RSRC) 903 or the like (Fig. 9). In this case, the PFU programmer and controller 204 retrieves the resource declaration 903, pre-allocates the indicated number of sections 303, and then uses the PFU program to program the allocated sections.

Once a PFU program is programmed into the programmable logic 301 for a given process, and the PFU configuration map 212 is updated accordingly, the PFU programmer and controller 204 monitors or is otherwise provided with mode information and enables the corresponding PFU program in work during this mode.

FIG. 4 is a block diagram illustrating a method for initially programming the PFU 114 according to one embodiment of the present invention. At POR, in block 302, BIOS 108 performs initialization processes and routines for performing hardware initialization to provide runtime services to OS 120 and programs or applications. Initialization includes, for example, initialization of memory 110 and system memory 112 for use by processor 100 .

The next set of blocks 304, 306 and 308 may be performed by BIOS 108 or OS 120 depending on the implementation. In the next block 304, it is determined whether the PFU program 116 is located on the ROM 210 in the case where the ROM 210 of the PFU 114 is provided. For example, the PFU program may be stored on ROM 210 (if provided) as PGM1 (eg, the default PFU program, etc.). If the PFU program 116 is not located on the ROM 210 , or the ROM 210 is not set, then operation proceeds to block 306 where the PFU program 116 is accessed on the memory 110 and copied to the RAM of the local memory 206 208 (if set up), or copied to system memory 112.

Following block 304 or 306 , operation proceeds to block 308 where a program command PGM<ADDR> is sent to the PFU 114 of the MC 104 to program the PFU engine 202 . The PGM command may be received by the PFU programmer and controller 204, which locates the PFU program 118 using the included address ADDR. In embodiments where PFU program 118 is pre-stored on ROM 210 within processor 100, ADDR identifies a location within ROM 210, such as the location of PGM1 (or any other pre-stored PFU program within ROM 210), or the like. In embodiments where the PFU program 118 is not pre-stored and the RAM 208 of the local memory 206 is provided on the processor 100, the PFU program 116 may be copied to the ADDR within the RAM 208 to identify the location of the copied PFU program Location. For example, the ADDR may identify the location on RAM 208 of the replicated PFU program 118 stored as a PGMA or the like. In the case where no local memory 206 is provided, the PFU program 116 is copied as the PFU program 118 stored in the system memory 112 , and the ADDR identifies the location of the PFU program 118 in the system memory 112 .

Operation then proceeds to block 310 where the PFU programmer and controller 204 uses the set ADDR to access the PFU program (eg, PFU program 118 and/or PGM1 and/or PGMA) and correspondingly The PFU engine 202 is programmed and the PFU engine 202 is enabled. Then, the method of initial programming is completed. Once the PFU engine 202 is thus programmed and enabled, the programmed PFU engine 202 modifies and/or enhances the operation of the MC 104 according to the PFU program.

5 is a simplified block diagram depicting an executable binary application (APP) 502 that may be used to program or otherwise reprogram the PFU 114 in accordance with one embodiment of the present invention. The binary APP 502 includes a header 504 and a body 506 . The binary APP 502 is shown in a general-purpose form and may be implemented as a binary executable (.EXE) file, a word, a binary executable (.EXE) file that can be successfully executed by any one or more of the processing cores C0-C3 of the processor 100 Section code files (.NET, Java, etc.) or any other type of executable code. In the configuration shown, header 504 includes at least one PFU write instruction, wherein each write instruction is provided to specify or locate a corresponding PFU program that may be used to encode PFU 114 . As shown, for example, the header 504 includes a PFU write instruction WRITE_PFU containing an operand (or parameter) PGMA for identifying the corresponding PFU program PGMA_PFU contained within the header 504 . Alternatively, the PFU program PGMA_PFU may be provided in a different section of the binary APP 502 . In any case, operand PGMA may be an address or offset used to locate the PFU program PGMA_PFU within binary APP 502 and/or system memory 112 . Although binary APP 502 includes only one PFU write instruction for identifying a corresponding PFU program, the executable binary application may include any number of PFU programs for loading any number of PFU programs that may be loaded into processor 100 at any given time the PFU write command.

During operation, a processing core (eg, C0) makes accesses and/or loads binary APP 502 from memory 110 to system memory 112, and executes a WRITE_PFU instruction. Assuming the RAM 208 of the local memory 206 exists, the PFU program PGMA_PFU within the binary APP 502 is located using the operand PGMA of the WRITE_PFU instruction, and the PFU program PGMA_PFU is written into the RAM 208 . Alternatively, the PFU program PGMA_PFU may be written into any other memory accessible by the PFU 114 of the processor 100 . The header 121 also includes a PFU programming instruction PGM_PFU with a location (or address) operand LOC, where the PFU programming instruction PGM_PFU is forwarded to the PFU programmer and controller 204 of the PFU 114 . The LOC identifies the location within the RAM 208 of the PFU program PGMA_PFU copied from the binary APP 502 . The PFU programmer and controller 204 then uses the PFU program PGMA_PFU from the RAM 208 to program the PFU engine 202 .

In configurations where local memory 206 (or any other suitable memory) is not provided within processor 100 , the WRITE_PFU instruction may simply identify the location of the PFU program PGMA_PFU within binary APP 502 without actually copying the PFU program PGMA_PFU to processor 100 in any local storage. In this case, the LOC is updated with the address within system memory 112 of the PFU program PGMA_PFU. The PFU programming instruction PGM_PFU is forwarded to the PFU programmer and controller 204 of the PFU 114 , which uses the operand LOC to locate the PFU program PGMA_PFU in the system memory 112 to program the PFU engine 202 .

In an alternative configuration, a single instruction or command may be used in the binary APP 502, where the single instruction or command, if executed, is forwarded to the PFU programmer and controller 204. The PFU programmer and controller 204 uses the included operands in the form of addresses or offsets, etc. to locate the PFU program PGMA_PFU with which the PFU engine 202 is directly programmed. In any programming configuration, the PFU programmer and controller 204 enables the PFU program PGMA_PFU newly programmed into the PFU engine 202 .

System memory 112 (and/or other external memory) may include a number of applications loaded for execution by processor 100 over time. Multiple applications or processes may be loaded into any one or more of the processing cores C1-C3, but in the illustrated embodiment each processing core typically executes only one process at a time. Embodiments in which each processing core executes multiple processes at once are also contemplated. Multiple applications can be assigned to one of the processing cores for execution. OS 120 includes a scheduler or the like for scheduling execution of applications for processor 100 including swapping in and out each of a plurality of processes for execution one at a time for a given processing core . Multiple applications may be executed by a given processing core, where each application may include one or more PFU programs for programming PFU 114 . Different processes corresponding to different processing modes of processor 100 may be managed using PFU programmer and controller 204 and local memory 206 and PFU configuration map 212 to control programming of PFU engine 202 over time.

FIG. 6 is a more detailed block diagram of the programmable logic 301 of FIG. 3 implemented in accordance with one embodiment of the present invention. The illustrated programmable logic 301 includes an array of programmable elements including programmable logic elements (LEs) 601 shown arranged in an XY matrix of logic elements 601, each of which is shown as LExy, where x and y represent the row and column indices of the array, respectively. Each row also includes at least one of an array of miscellaneous logic blocks 603 , where the miscellaneous logic blocks 603 each include support logic to complement the matrix of logic elements 601 . Each miscellaneous logic block 603 may, for example, include one or more storage elements, one or more registers, one or more latches, one or more multiplexers, one or more adders (to add or add subtracting a digital value), a set of Boolean logic elements, or gates (eg, logic gates such as an OR (OR) gate, an AND (AND) gate, an inverter, an exclusive OR (XOR) gate, etc.), and the like. Various miscellaneous logic blocks 603 may include one or more registers that may be configured as shift registers or data swizzlers, or the like, for flexible data manipulation. Logic elements 601 and miscellaneous logic blocks 603 are coupled together with a routing grid that includes a matrix of programmable crossbar switches or interconnectors 605 . Each programmable interconnect 605 includes a plurality of switches to selectively connect programmable devices together. The routing mesh includes sufficient connectivity to connect multiple devices in logic elements 601 and miscellaneous logic blocks 603 together for simple processing operations and more complex processing operations.

As further described herein, each programmable section 303 includes one or more programmable elements (logic element 601 , logic block 603 ) as well as modifications for selectively connecting devices and elements together to implement PFU 114 The corresponding routing mesh (interconnector 605 ) of the corresponding function of the operation of the MC 104 . A routing grid is a switching matrix that includes a number of switches, etc. to redirect input and output between logic elements 601 and miscellaneous logic blocks 603 .

Programmable logic 301 includes programmable memory 607 that is used to receive a PFU program (eg, one of PFU program 116, PFU program 118, PGMA, PGMB, PGMC, . . . , PGM1, PGM2, PGM3, etc. or multiple) to program selected ones of logic elements 601, corresponding miscellaneous logic blocks 603, and programmable interconnects 605 to create corresponding logic for modifying the operation of MC 104 when activated or otherwise enabled PFU function. Programmable memory 607 may also include storage locations or registers or the like to receive input operands or values and store output results of the PFU program. Programmable memory 607 is dispersed among programmable sections 303 of programmable logic 301, and may be used individually or collectively by each of the programmable sections 303 in selected allocated sections 303 for particular PFU operations. Programmable memory 607 may be configured as a dedicated memory space within programmable logic 301 or even within MC 104 and cannot be accessed externally. Memory 607 may be implemented in any suitable manner, such as static random access memory (SRAM).

FIG. 7 is a schematic block diagram of a programmable logic element 601 implemented in accordance with one embodiment of the present invention. The logic element 601 includes a look-up table (LUT) 701 , three 2-input multiplexers (MUXs) 705 , 706 and 707 , a 2-input adder 709 , and a clock register (or latch) 711 . A portion of programmable memory 607 is shown for programming a portion of logic element 601 , any included miscellaneous logic blocks 603 and one or more interconnects 605 . As explained above, programmable memory 607 may be used to provide input values, store output results, and/or store intermediate values updated for each of multiple iterations of a processing operation.

As shown, memory 607 is programmed using the PFU program shown as PGM_PFU. LUT 701 is shown as a 4×1 LUT programmed with corresponding LUT value (LV) bits in memory 607 . MUXs 705, 706, and 707 each have select inputs controlled by corresponding memory bits stored by memory 607 (shown as memory bits Ml, M2, and M3, respectively). The output of LUT 701 , shown as LO, is provided to one input of MUX 705 and to the input of register 711 , where the output of register 711 is provided to the other input of MUX 705 . The output of MUX 705 is provided to one input of MUX 706 and one input of adder 709. The output of adder 709 is provided to another input of MUX 706 , where the output of MUX 706 is provided to the input of programmable interconnector 605 . Memory 607 includes a programmable bit V, wherein the programmable bit V is provided to one input of MUX 707, the other input of MUX 707 is coupled to the output of programmable interconnect 605, and the output of MUX 707 is provided to Another input to adder 709. The output of adder 709 is provided to the other input of MUX 706 . Memory 607 may also be used to program corresponding portions of interconnect 605 and any miscellaneous logic blocks 603 .

The illustrated logic element 601 is exemplary only, and alternative versions may be considered depending on the particular configuration. Logic elements 601 may be configured at a bit slice granularity level to address a single bit of a data value. For data values that include multiple bits, multiple bit slice logic elements are used. For example, for 64-bit data values, 64 bit slice logic elements are used in parallel.

In operation, memory 607 is programmed with the LUT data value (LV) of LUT 701 , the select inputs M1 - M3 of MUX 705 - 707 , and the programmable data value V provided to the input of MUX 707 . The four input values S0-S3 are provided from the operands of the instruction, from memory 607, or from another programming block to select the one of the 16 values to be programmed into the LUT 701, where all of the values are provided at the output of the LUT 701. The selected value is used as LO. Program the MUX 705 to provide the LO output of the LUT701 directly or to provide a registered version. The registered version can be used to insert delays for the purpose of timing of PFU operations. MUX 706 is programmed to provide the output of MUX 705 directly, or to provide interconnect 605 the output of adder 709 to be provided as an output or to be provided to another programming block. Adder 709 adds the selected value, which is the programming value V or the output from interconnector 605 (provided from another input or from another programming block), to the output of MUX 705 .

Figure 8 is a schematic diagram of a LUT 701 implemented in accordance with one embodiment of the present invention. A set of 2-input MUXs organized as a binary MUX tree is provided to select between 16 input values LV0-LV15 based on selection inputs S3:S0 (where S0 is the least significant bit). LV0-LV15 are programmed into memory 607 as previously described. Each adjacent pair of 16 input values LV0-LV15 (LV0 and LV1, LV2 and LV3, . S0 is received at the input. Each adjacent pair of the 8 outputs of MUX 801 is provided to a corresponding input pair of four 2-input MUXs 803, each of which receives S1 at its select input. Each adjacent pair of the four outputs of MUX 803 is provided to a corresponding input pair of two 2-input MUXs 805, each of which receives S2 at its select input. The output pair of MUX 805 is provided to the input pair of output MUX 807, which receives S3 at its select input and provides the LUT output LO at its output. It should be understood that the configuration shown in Figure 8 is only one of many suitable LUT implementations that can be understood by those of ordinary skill in the art.

9 is a simplified block diagram of the format of a PFU program 901 for programming the PFU engine 202, where the PFU program 901 may represent the PFU programs 116, 118, PGMA, PGMB, PGMC, . . . , PGM1, according to one embodiment of the present invention , PGM2, PGM3, etc. any form. In this case, the PFU program 901 may include a resource declaration (RSRC) 903, where the RSRC 903 is used to indicate the amount of resources required within the programmable logic 301 to implement the PFU program. As an example, resource declaration 903 may represent the number P of programmable sections required to complete programming. PFU programmer and controller 204 may read resource declaration 903 during programming of PFU engine 202 to allocate a corresponding number of programmable segments 303 . Although greater granularity may be used, such as by tracking the amount of individual logic elements 601, miscellaneous logic blocks 603, programmable interconnects 605, and/or programmable memory 607, this may require the PFU programmer and controller 204 to change over time The individual elements of the programmable logic 301 are traced over the course of the .

The PFU program 901 may also include a series of logical ones (1) and zeros (0) known as a bitstream. In one embodiment, for example, in response to programming instructions received by the processing cores, the PFU programmer and controller 204 assigns programmable memory (including programmable memory 607 and interconnects to the allocated sections of programmable section 303 ). 605) into a large serialized shift register, which is then shifted in the bitstream until fully loaded in each allocated section, then the programmable memory is de-arranged and provided with the pointer to locate and identify the programmed PFU. Alternative programming methods and formats including parallel programming may be used. Furthermore, the resource declaration may be placed at any suitable location, such as start or end, to be read by the PFU programmer and controller 204 to ensure proper programming.

10 is a simplified block diagram illustrating an example method for generating a PFU program 116 for programming the PFU engine 202 of the PFU 114, according to one embodiment of the present invention. An application generator, such as a programmer, writes the PFU functional description 1002 in a selected format to describe or otherwise define the memory controller operation for modifying or enhancing the MC 104 . PFU functional description 1002 may otherwise be referred to as a PFU definition. The PFU functional description 1002 may be written in any suitable hardware programming language such as LegUp, Catapult (from Catapulttechnology, Inc.), Verilog, HDL (Hardware Description Language), Register Control Logic (RCL), Register Transfer Logic (RTL), and the like. The PFU functional description 1002 is provided to a corresponding PFU programming tool 1004 , wherein the PFU programming tool 1004 is configured to convert the PFU functional description 1002 into a PFU program 116 suitable for programming the PFU engine 202 to operate according to the PFU functional description 1002 . As an example, the PFU programming tool 1004 can convert the PFU functional description 1002 into a corresponding bitstream that can be used to program one or more of the programmable sections 303 of the programmable logic 301 of the PFU engine 202 .

Once the PFU program 116 is generated, the PFU program 116 may be stored in a suitable location on the memory 110 for access by the BIOS 108 or the OS 120 to program the PFU 114 according to any of the methods previously described. Alternatively, the PFU program 116 may be incorporated into an application, such as the binary APP 502, to be programmed by the application when executed.

FIG. 11 is a simplified block diagram illustrating an exemplary encryption process that may be programmed into PFU 114 and performed by MC 104 when storing data to system memory 112 . The move (MOV) instruction 1102 represents any type of store instruction executed by any core of the processor 100 to store the data value DATA (data) stored in the register (REG) 1103 to the specified address ADDR in the system memory 112 . The PFU engine 202 of the PFU 114 is programmed with a KEY 1104 and an encryption algorithm 1106 . KEY 1104 is any binary or hexadecimal value that can be predetermined and stored within PFU program 116 . The encryption algorithm 1106 is based on any standard or custom encryption algorithm, such as Data Encryption Standard (DES), RSA Public Key System, MD5 algorithm, Advanced Encryption Standard (AES), various hashing algorithms, and the like.

In operation, the MC 104 , as modified by the PFU 114 , extracts the address ADDR from the MOV instruction 1102 and applies the address ADDR to an input to the encryption algorithm 1106 . The KEY 1104 is applied to the other input, and the encryption algorithm 1106 provides the corresponding PAD (padding) value 1108 at its output. In other words, encryption algorithm 1106 essentially converts KEY 1104 and ADDR to PAD value 1108. The DATA value from the REG 1103 is applied to one input of a Boolean logic function such as an exclusive OR (XOR) operation 1110, the PAD value 1108 is applied to the other input, and the XOR operation 1110 performs the indicated Boolean operation (e.g., XOR ) and provides the corresponding encrypted data value XDATA1112 at its output. The MC 104 stores the encrypted XDATA value 1112 at address ADDR of the system memory 112 instead of the original DATA value.

FIG. 12 is a simplified block diagram illustrating the reverse encryption process that may be programmed into PFU 114 and performed by MC 104 when data is loaded from system memory 112 . The reverse encryption process of FIG. 12 is complementary to the encryption process of FIG. 11 , where the two processes are stored together in the PFU program 116 to implement a complete encryption process for storing and loading information relative to the system memory 112 . Another MOV instruction 1202 represents any type of load instruction executed by any core of the processor 100 to load or read a data value from an addressed location of the system memory 112 into a designated register of the processor 100, such as REG 1103.

Extract the address ADDR from the load instruction 1202 and apply the address ADDR to one input of the reverse encryption algorithm 1206 (or decryption algorithm), and apply the KEY 1104 to the other input of the reverse encryption algorithm 1206, where the reverse encryption algorithm 1206 A corresponding PAD 1208 is provided at its output. A MOV instruction 1202 is also applied to system memory 112 to retrieve encrypted XDATA values 1112. The encrypted XDATA values 1112 and PAD 1208 are applied to the respective inputs of the XOR operation 1110, which outputs the corresponding decrypted data value DATA. The MC 104 stores the DATA value instead of the retrieved XDATA value 1112 into the REG 1103 as specified with the MOV instruction 1202.

Assuming that encryption algorithm 1106 and reverse encryption algorithm 1206 are complementary, the decrypted DATA value retrieved upon execution of MOV instruction 1202 is the same as the original DATA value originally stored in REG 1103 prior to execution of MOV instruction 1202. In this way, PFU 114 modifies the operation of MC 104 to encrypt data stored in system memory 112 and decrypt data retrieved from system memory 112 . Note that for symmetric key encryption such as AES, the encryption algorithm 1106 and the reverse encryption algorithm 1206 are the same (ie, are the same algorithm), so that only one encryption/decryption algorithm is required.

The foregoing description has been presented to enable one of ordinary skill in the art to make and use the present invention as provided in the context of a particular application and its requirements. Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the generic principles set forth herein may be applied to other embodiments. For example, the circuits described herein may be implemented in any suitable manner including logic devices or circuits, or the like. Those skilled in the art should appreciate that the conception and specific embodiment disclosed may be readily utilized as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of the following US patent application, the entire contents of which are hereby incorporated by reference for all purposes and uses.

This application is related to the following US patent application, which is hereby incorporated by reference in its entirety for all purposes and uses.

Claims (16)

1. A processor, comprising:

a memory controller for interfacing an external memory;

a Programmable Functional Unit (PFU) programmed by a PFU program to modify operation of the memory controller, wherein the PFU comprises a plurality of programmable logic elements and a plurality of programmable interconnects; and

a programmable memory to receive the PFU program to program the selected programmable logic element;

wherein the programmable logic element comprises:

a lookup table programmed by respective lookup table value bits in the programmable memory and providing a plurality of input values by an operand of an instruction to select the respective lookup table value bits as output;

a register comprising an output and an input coupled to the output of the lookup table;

a first multiplexer including an output, a select input controlled by a corresponding memory bit stored in the programmable memory, a first input coupled to the output of the lookup table, and a second input coupled to the output of the register;

a second multiplexer including an output, a select input controlled by a corresponding memory bit stored in the programmable memory, a first input coupled to a programmable bit stored in the programmable memory, and a second input coupled to the programmable interconnect;

an adder including an output, a first input coupled to the output of the first multiplexer, and a second input coupled to the output of the second multiplexer; and

a third multiplexer including a select input controlled by a respective memory bit stored in the programmable memory, a first input coupled to an output of the first multiplexer, a second input coupled to an output of the adder, and an output coupled to the programmable interconnect.

2. The processor of claim 1, further comprising a PFU programmer to program the PFU using a PFU program stored in local memory.

3. The processor of claim 2, wherein the processor is responsive to a program command, wherein the program command is to cause the PFU programmer to program the PFU with a specified PFU program of a plurality of PFU programs stored in the local memory.

4. The processor of claim 1, further comprising a configuration map for mapping each of a plurality of different processing modes with a respective one of a plurality of PFU programs stored in local memory.

5. The processor of claim 1, wherein said plurality of programmable logic elements and said plurality of programmable interconnects are subdivided into a plurality of substantially identical programmable sections, wherein said processor further comprises a PFU programmer for allocating a plurality of said programmable sections and programming said allocated plurality of said programmable sections with said PFU program to program said PFU.

6. The processor of claim 1, wherein the PFU comprises the programmable memory and the PFU program comprises a bit stream scanned into the programmable memory of the PFU.

7. The processor of claim 1, wherein the PFU is programmed with a plurality of PFU programs, wherein the processor further comprises a PFU programmer to enable at least one of the plurality of PFU programs at a time during operation of the processor.

8. The processor of claim 1, wherein the PFU program programs the PFU to perform an encryption function for encrypting data stored in the external memory.

9. The processor of claim 8, wherein the cryptographic function includes an encryption process and a reverse encryption process that employs a predetermined key combined with an address to develop a pad value that is further combined with a data value.

10. A method for providing a programmable memory controller of a processor interfacing the processor with an external memory, the method comprising the steps of:

a PFU comprising a programmable functional unit, the PFU including a plurality of programmable logic elements and a plurality of programmable interconnects;

programming the PFU with a PFU program to modify operation of the programmable memory controller; and

setting a programmable memory to receive the PFU program to program the selected programmable logic element, comprising:

setting a lookup table, a register, a first multiplexer, a second multiplexer, an adder and a third multiplexer;

the lookup table is programmed by corresponding lookup table value bits in the programmable memory and a plurality of input values are provided by an operand of the instruction to select the corresponding lookup table value bits as output;

the register receives the output of the lookup table;

the first multiplexer receiving a select input controlled by a respective memory bit stored in the programmable memory and receiving an output of the lookup table as a first input and an output of the register as a second input;

the second multiplexer receiving a select input controlled by a respective memory bit stored in the programmable memory and receiving a programmable bit stored in the programmable memory as a first input and an output of the programmable interconnect as a second input;

the adder receives the output of the first multiplexer as a first input and the output of the second multiplexer as a second input; and

the third multiplexer receives a select input controlled by a respective memory bit stored in the programmable memory and receives the output of the first multiplexer as a first input, the output of the adder as a second input, and the output of the third multiplexer is provided to the programmable interconnect.

11. The method of claim 10, further comprising the steps of: providing a PFU programmer and a PFU engine within the PFU, wherein in the PFU programmer programs the PFU engine with the PFU program stored in local memory.

12. The method of claim 11, further comprising the steps of: executing a program command with the processor, wherein the program command is to instruct the PFU programmer to program the PFU engine with a PFU program stored in the local memory.

13. The method of claim 10, further comprising the steps of: setting a configuration map in the PFU, wherein the configuration map is used to map each processing mode of a plurality of different processing modes with a corresponding PFU program of a plurality of PFU programs stored in a local memory.

14. The method of claim 10, further comprising the steps of:

subdividing the plurality of programmable logic elements and the plurality of programmable interconnectors into a plurality of substantially identical programmable sections;

allocating a plurality of the programmable sections to configure the PFU according to the PFU program; and

programming the allocated plurality of the programmable segments with at least one PFU program.

15. The method of claim 11, further comprising the steps of:

setting the PFU to the programmable memory; and

programming the PFU includes: scanning at least one of the PFU programs as a bitstream into the programmable memory of the PFU engine.

16. The method of claim 10, further comprising the steps of: programming the PFU with a plurality of PFU programs; and enabling at least one of the plurality of PFU programs at a time during operation of the processor.

Images