WO2002033569A3 - Data path arrangement - Google Patents

Data path arrangement Download PDF

Info

Publication number
WO2002033569A3
WO2002033569A3 PCT/DE2001/003915 DE0103915W WO0233569A3 WO 2002033569 A3 WO2002033569 A3 WO 2002033569A3 DE 0103915 W DE0103915 W DE 0103915W WO 0233569 A3 WO0233569 A3 WO 0233569A3
Authority
WO
WIPO (PCT)
Prior art keywords
functional units
data path
aim
cpu
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2001/003915
Other languages
German (de)
French (fr)
Other versions
WO2002033569A2 (en
Inventor
Wolfram Drescher
Gerhard Fettweis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP Semiconductors Germany GmbH
Original Assignee
Systemonic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Systemonic AG filed Critical Systemonic AG
Priority to US10/399,243 priority Critical patent/US20040044818A1/en
Priority to EP01987921A priority patent/EP1330726A2/en
Priority to JP2002536887A priority patent/JP2004512598A/en
Priority to AU2002218136A priority patent/AU2002218136A1/en
Publication of WO2002033569A2 publication Critical patent/WO2002033569A2/en
Publication of WO2002033569A3 publication Critical patent/WO2002033569A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)

Abstract

The invention relates to an arrangement for the configuration of data paths, in which different functional units are connected to a linker unit and arranged within a CPU architecture. The aim of the invention is to permit functional extensions within the CPU architecture without essentially extending the networking complexity between the functional units and the controlling register of the CPU. Said aim is achieved, whereby the linking unit essentially comprises a processor bus arrangement and functional units with dedicated input registers and output registers.
PCT/DE2001/003915 2000-10-16 2001-10-15 Data path arrangement Ceased WO2002033569A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US10/399,243 US20040044818A1 (en) 2000-10-16 2001-10-15 Data path arrangement
EP01987921A EP1330726A2 (en) 2000-10-16 2001-10-15 Data path arrangement
JP2002536887A JP2004512598A (en) 2000-10-16 2001-10-15 Data path placement
AU2002218136A AU2002218136A1 (en) 2000-10-16 2001-10-15 Data path arrangement

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10051284.4 2000-10-16
DE10051284A DE10051284A1 (en) 2000-10-16 2000-10-16 Data path arrangement e.g. for CPU, has processor bus joined to input of input register and to output of output register

Publications (2)

Publication Number Publication Date
WO2002033569A2 WO2002033569A2 (en) 2002-04-25
WO2002033569A3 true WO2002033569A3 (en) 2003-01-03

Family

ID=7659995

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/003915 Ceased WO2002033569A2 (en) 2000-10-16 2001-10-15 Data path arrangement

Country Status (6)

Country Link
US (1) US20040044818A1 (en)
EP (1) EP1330726A2 (en)
JP (1) JP2004512598A (en)
AU (1) AU2002218136A1 (en)
DE (1) DE10051284A1 (en)
WO (1) WO2002033569A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4641276A (en) * 1984-10-22 1987-02-03 General Electric Company Serial-parallel data transfer system for VLSI data paths
US5301340A (en) * 1990-10-31 1994-04-05 International Business Machines Corporation IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle
US5692139A (en) * 1988-01-11 1997-11-25 North American Philips Corporation, Signetics Div. VLIW processing device including improved memory for avoiding collisions without an excessive number of ports
WO2000033178A1 (en) * 1998-12-03 2000-06-08 Sun Microsystems, Inc. Local and global register partitioning in a vliw processor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4203157A (en) * 1978-09-05 1980-05-13 Motorola, Inc. Carry anticipator circuit and method
US4272828A (en) * 1979-01-03 1981-06-09 Honeywell Information Systems Inc. Arithmetic logic apparatus for a data processing system
JPS5757345A (en) * 1980-09-24 1982-04-06 Toshiba Corp Data controller
JPS60258671A (en) * 1984-06-05 1985-12-20 Nec Corp Processor
KR860007588A (en) * 1985-03-25 1986-10-15 미쓰다 가쓰시게 Data processing device
JPH0758460B2 (en) * 1988-05-25 1995-06-21 日本電気株式会社 Floating-point arithmetic normalization control method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4641276A (en) * 1984-10-22 1987-02-03 General Electric Company Serial-parallel data transfer system for VLSI data paths
US5692139A (en) * 1988-01-11 1997-11-25 North American Philips Corporation, Signetics Div. VLIW processing device including improved memory for avoiding collisions without an excessive number of ports
US5301340A (en) * 1990-10-31 1994-04-05 International Business Machines Corporation IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle
WO2000033178A1 (en) * 1998-12-03 2000-06-08 Sun Microsystems, Inc. Local and global register partitioning in a vliw processor

Also Published As

Publication number Publication date
DE10051284A1 (en) 2002-04-25
US20040044818A1 (en) 2004-03-04
EP1330726A2 (en) 2003-07-30
AU2002218136A1 (en) 2002-04-29
JP2004512598A (en) 2004-04-22
WO2002033569A2 (en) 2002-04-25

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