RU2006124538A - DATA PROCESSING DEVICE AND METHOD FOR MOVING DATA BETWEEN REGISTERS AND MEMORY - Google Patents

DATA PROCESSING DEVICE AND METHOD FOR MOVING DATA BETWEEN REGISTERS AND MEMORY Download PDF

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RU2006124538A
RU2006124538A RU2006124538/09A RU2006124538A RU2006124538A RU 2006124538 A RU2006124538 A RU 2006124538A RU 2006124538/09 A RU2006124538/09 A RU 2006124538/09A RU 2006124538 A RU2006124538 A RU 2006124538A RU 2006124538 A RU2006124538 A RU 2006124538A
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data
registers
data elements
processing device
single access
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RU2006124538/09A
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Саймон Эндрю ФОРД (GB)
Саймон Эндрю ФОРД
Доминик Хьюго САЙМЗ (GB)
Доминик Хьюго САЙМЗ
Эндрю Кристофер РОУЗ (GB)
Эндрю Кристофер РОУЗ
Дэвид Реймонд ЛУТЦ (US)
Дэвид Реймонд ЛУТЦ
Кристофер Нил ХИНДЗ (US)
Кристофер Нил ХИНДЗ
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Арм Лимитед (Gb)
Арм Лимитед
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Publication of RU2006124538A publication Critical patent/RU2006124538A/en

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Claims (33)

1. Устройство обработки данных, содержащее устройство хранения данных регистров, имеющее множество регистров, способных хранить элементы данных, количество элементов данных, хранимых в каждом регистре, зависит от типа данных элементов данных; процессор, способный выполнять параллельно операцию обработки данных над множеством элементов данных, занимающих различные линии параллельной обработки в, по меньшей мере, одном из упомянутых регистров; логическую схему доступа, способную в ответ на единичную инструкцию доступа переместить множество элементов данных между выбранной одной из упомянутых линий обработки в заданных регистрах и структурой в памяти, имеющей формат структуры, формат структуры имеет множество компонент; единичную инструкцию доступа, включающую в себя информацию о типе данных, идентифицирующую тип данных, связанный с перемещаемым элементом данных, и идентифицирующую количество компонент в формате структуры; и логическую схему доступа, способную выполнить упорядочивание множества элементов данных при их перемещении так, чтобы элементы данных различных компонент сохранялись в разных заданных регистрах в выбранной линии обработки, причем в памяти элементы данных хранятся в виде структуры, упорядочивание выполняется логической схемой доступа в зависимости от типа данных.1. A data processing device comprising a register data storage device having a plurality of registers capable of storing data elements, the number of data elements stored in each register depends on the data type of the data elements; a processor capable of performing in parallel a data processing operation on a plurality of data elements occupying different parallel processing lines in at least one of said registers; an access logic capable of responding to a single access instruction to move a plurality of data elements between a selected one of said processing lines in predetermined registers and a structure in memory having a structure format, the structure format has many components; a single access instruction including data type information identifying a data type associated with a data item being moved and identifying the number of components in a structure format; and an access logic capable of arranging a plurality of data elements when moving them so that data elements of various components are stored in different predetermined registers in a selected processing line, wherein data elements are stored in memory as a structure, ordering is performed by an access logic depending on the type data. 2. Устройство обработки данных по п.1, в котором единичная инструкция доступа задает выбранную линию обработки.2. The data processing device according to claim 1, in which a single access instruction sets the selected processing line. 3. Устройство обработки данных по п.1 или 2, в котором логическая схема доступа в ответ на последовательность упомянутых единичных инструкций доступа перемещает элементы данных между множеством выбранных линий обработки в заданных регистрах и соответствующим множеством структур в памяти.3. The data processing device according to claim 1 or 2, in which the access logic in response to a sequence of said single access instructions moves data elements between a plurality of selected processing lines in predetermined registers and a corresponding plurality of structures in memory. 4. Устройство обработки данных по п.1, в котором структура содержит одну компоненту, а заданные регистры содержат один регистр.4. The data processing device according to claim 1, in which the structure contains one component, and the specified registers contain one register. 5. Устройство обработки данных по п.1, в котором единичная инструкция доступа идентифицирует заданные регистры, количество заданных регистров кратно количеству компонент.5. The data processing device according to claim 1, in which a single access instruction identifies the given registers, the number of specified registers is a multiple of the number of components. 6. Устройство обработки данных по п.1, в котором каждый перемещаемый элемент данных принадлежит к одному и тому же типу данных.6. The data processing device according to claim 1, in which each roaming data item belongs to the same data type. 7. Устройство обработки данных по п.1, в котором заданные регистры имеют фиксированную связь между собой.7. The data processing device according to claim 1, in which the given registers have a fixed connection with each other. 8. Устройство обработки данных по п.7, в котором в соответствии с фиксированной связью заданные регистры разделены посредством n вспомогательных регистров, где n=2m-1, где m является целым числом, большим либо равным нулю.8. The data processing device according to claim 7, in which, in accordance with a fixed connection, the given registers are divided by n auxiliary registers, where n = 2 m -1, where m is an integer greater than or equal to zero. 9. Устройство обработки данных по п.7 или 8, в котором заданные регистры являются группами соседних регистров в упомянутом устройстве хранения данных регистров.9. The data processing device according to claim 7 or 8, wherein the predetermined registers are groups of neighboring registers in said register data storage device. 10. Устройство обработки данных по п.1, в котором упомянутая единичная инструкция доступа является единичной инструкцией загрузки, упомянутая логическая схема доступа способна в ответ на упомянутую единичную инструкцию доступа загрузить множество элементов данных из упомянутой структуры в памяти в выбранную линию обработки упомянутых заданных регистров, и перед сохранением элементов данных в выбранную линию обработки упомянутых заданных регистров, упорядочить упомянутые элементы данных так, что элементы данных различных компонент сохраняются в различные регистры упомянутых заданных регистров.10. The data processing device according to claim 1, wherein said single access instruction is a single download instruction, said access logic is capable, in response to said single access instruction, from loading a plurality of data elements from said structure in memory into a selected processing line of said predetermined registers, and before storing the data elements in the selected processing line of said predetermined registers, arrange said data elements so that the data elements of the various components stored in various registers of said specified registers. 11. Устройство обработки данных по п.1, в котором упомянутая единичная инструкция доступа является единичной инструкцией сохранения, упомянутая логическая схема доступа способна в ответ на упомянутую единичную инструкцию сохранения сохранить множество элементов данных из выбранной линии обработки упомянутых заданных регистров в упомянутую структуру в памяти, и перед сохранением элементов данных в упомянутую структуру в памяти, упорядочить упомянутые элементы данных так, чтобы элементы данных сохранялись в упомянутом формате структуры.11. The data processing device according to claim 1, wherein said unit access instruction is a unit save instruction, said access logic is capable of in response to said unit save instruction, to store a plurality of data elements from a selected processing line of said predetermined registers into said structure in memory, and before storing the data elements in said structure in memory, arrange said data elements so that the data elements are stored in said structure format s. 12. Устройство обработки данных по п.10, в котором логическая схема доступа способна вызывать заполнение незаполненных частей заданных регистров одним или более предопределенными значениями.12. The data processing device of claim 10, wherein the access logic is capable of causing the unfilled parts of the given registers to be filled with one or more predetermined values. 13. Устройство обработки данных по п.1, в котором единичная инструкция доступа идентифицирует режим адресации, используемый для идентификации перемещаемых элементов данных.13. The data processing device according to claim 1, in which a single access instruction identifies the addressing mode used to identify roaming data elements. 14. Устройство обработки данных по п.13, в котором режим адресации идентифицирует начальный адрес для структуры в памяти.14. The data processing device according to item 13, in which the addressing mode identifies the starting address for the structure in memory. 15. Устройство обработки данных по п.1, в котором заданные регистры имеют одинаковый размер.15. The data processing device according to claim 1, in which the specified registers are of the same size. 16. Устройство обработки данных по п.1, в котором единичная инструкция доступа идентифицирует преобразование, которое будет применено к элементам данных, и логическая схема доступа способна применить упомянутое преобразование к элементам данных при их перемещении.16. The data processing device according to claim 1, in which a single access instruction identifies the transformation that will be applied to the data elements, and the access logic is able to apply the transformation to the data elements when moving them. 17. Способ управления устройством обработки данных, содержащим устройство хранения данных регистров, имеющее множество регистров, способных хранить элементы данных, количество элементов данных, хранимых в каждом регистре зависит от типа данных элементов данных, и процессор, способный выполнять параллельно операцию обработки данных над множеством элементов данных, занимающих различные линии параллельной обработки в, по меньшей мере, одном из упомянутых регистров, причем способ включает в себя этапы, на которых17. A method of controlling a data processing device comprising a register data storage device having a plurality of registers capable of storing data elements, the number of data elements stored in each register depends on the data element data type, and a processor capable of performing a data processing operation on a plurality of elements in parallel data occupying various parallel processing lines in at least one of said registers, the method including the steps of (a) в ответ на единичную инструкцию доступа перемещают множество элементов данных между выбранной одной из упомянутых линий обработки в заданных регистрах и структурой в памяти, имеющей формат структуры, формат структуры имеет множество компонент;(a) in response to a single access instruction, a plurality of data elements are moved between a selected one of said processing lines in predetermined registers and a structure in memory having a structure format, the structure format has many components; единичная инструкция доступа включает в себя информацию о типе данных, идентифицирующую тип данных, связанный с перемещаемыми элементами данных, и идентифицирующую количество компонент в формате структуры, и способ включает в себя дополнительный этап, на которомa single access instruction includes data type information identifying a data type associated with movable data items and identifying the number of components in a structure format, and the method includes an additional step in which (b) упорядочивают множество элементов данных при их перемещении так, чтобы элементы данных различных компонент сохранялись в разных заданных регистрах в выбранной линии обработки, причем в памяти элементы данных хранятся в виде структуры, выполняемое упорядочивание зависит от типа данных.(b) arrange a plurality of data elements when moving them so that the data elements of various components are stored in different predetermined registers in the selected processing line, the data elements being stored in memory as a structure, the ordering performed depends on the data type. 18. Способ по п.17, в котором единичная инструкция доступа задает выбранную линию обработки.18. The method according to 17, in which a single access instruction sets the selected processing line. 19. Способ по п.17 или 18, в котором упомянутые этапы (a) и (b) повторяются для последовательности упомянутых единичных инструкций доступа, для того чтобы переместить элементы данных между множеством выбранных линий обработки в заданных регистрах и соответствующим множеством структур в памяти.19. The method according to 17 or 18, wherein said steps (a) and (b) are repeated for a sequence of said single access instructions in order to move data elements between a plurality of selected processing lines in predetermined registers and a corresponding plurality of structures in memory. 20. Способ по п.17, в котором упомянутая структура содержит одну компоненту, и заданные регистры содержат один регистр.20. The method according to 17, in which said structure contains one component, and the specified registers contain one register. 21. Способ по п.17, в котором единичная инструкция доступа идентифицирует заданные регистры, количество заданных регистров кратно количеству компонент.21. The method according to 17, in which a single access instruction identifies the given registers, the number of specified registers is a multiple of the number of components. 22. Способ по п.17, в котором каждый перемещаемый элемент данных принадлежит к одному и тому же типу данных.22. The method according to 17, in which each roaming data item belongs to the same data type. 23. Способ по п.17, в котором заданные регистры имеют фиксированную связь между собой.23. The method according to 17, in which the given registers have a fixed connection with each other. 24. Способ по п.23, в котором в соответствии с фиксированной связью заданные регистры разделены посредством n вспомогательных регистров, где n=2m-1, где m является целым числом, большим либо равным нулю.24. The method according to item 23, in which in accordance with a fixed connection specified registers are separated by n auxiliary registers, where n = 2 m -1, where m is an integer greater than or equal to zero. 25. Способ по п.23 или 24, в котором заданные регистры являются группами соседних регистров в упомянутом устройстве хранения данных регистров.25. The method according to item 23 or 24, in which the specified registers are groups of neighboring registers in said register data storage device. 26. Способ по п.17, в котором упомянутая единичная инструкция доступа является единичной инструкцией загрузки, и где упомянутый этап (а) содержит этап загрузки множества элементов данных из упомянутой структуры в памяти в выбранную линию обработки упомянутых заданных регистров; и упомянутый этап (b) содержит этап перед сохранением элементов данных в выбранную линию обработки упомянутых заданных регистров, упорядочивания упомянутых элементов данных так, что элементы данных различных компонент сохраняются в различные регистры упомянутых заданных регистров.26. The method according to 17, in which said single access instruction is a single download instruction, and where said step (a) comprises the step of loading a plurality of data elements from said structure in memory into a selected processing line of said predetermined registers; and said step (b) comprises a step before storing the data elements into the selected processing line of said predetermined registers, arranging said data elements so that the data elements of various components are stored in different registers of said predetermined registers. 27. Способ по п.17, в котором упомянутая единичная инструкция доступа является единичной инструкцией сохранения, и где упомянутый этап (а) содержит этап сохранения множества элементов данных из выбранной линии обработки упомянутых заданных регистров в упомянутую структуру в памяти; и упомянутый этап (b) содержит этап перед сохранением элементов данных в упомянутую структуру, упорядочивания упомянутых элементов данных так, чтобы элементы данных сохранялись в упомянутом формате структуры.27. The method according to 17, in which said single access instruction is a single save instruction, and where said step (a) comprises a step of storing a plurality of data elements from a selected processing line of said predetermined registers into said structure in memory; and said step (b) comprises a step before storing the data elements into said structure, arranging said data elements so that the data elements are stored in said structure format. 28. Способ по п.26, включающий в себя дополнительный этап, на котором заполняют незаполненные части заданных регистров одним или более предопределенными значениями.28. The method according to p. 26, including the additional step of filling in the unfilled parts of the given registers with one or more predetermined values. 29. Способ по п.17, в котором единичная инструкция доступа идентифицирует режим адресации, используемый для идентификации перемещаемых элементов данных.29. The method of claim 17, wherein the single access instruction identifies an addressing mode used to identify roaming data items. 30. Способ по п.29, в котором режим адресации идентифицирует начальный адрес для структуры в памяти.30. The method according to clause 29, in which the addressing mode identifies the starting address for the structure in memory. 31. Способ по п.17, в котором заданные регистры имеют одинаковый размер.31. The method according to 17, in which the specified registers have the same size. 32. Способ по п.17, в котором единичная инструкция доступа идентифицирует преобразование, которое будет применено к элементам данных, и способ включает в себя дополнительный этап, на котором применяют упомянутое преобразование к элементам данных при их перемещении.32. The method according to 17, in which a single access instruction identifies the transformation that will be applied to the data elements, and the method includes an additional step in which the said transformation is applied to the data elements when moving them. 33. Компьютерный программный продукт, содержащий компьютерную программу, включающую в себя, по меньшей мере, одну единичную инструкцию доступа, которая при выполнении обуславливает функционирование устройства обработки данных в соответствии со способом по любому из пп.17-32.33. A computer program product containing a computer program including at least one single access instruction, which, when executed, determines the operation of the data processing device in accordance with the method according to any one of claims 17-32.
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CN1894659B (en) 2010-05-26
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TWI315034B (en) 2009-09-21
GB2409066B (en) 2006-09-27
IL175588A (en) 2010-12-30
GB2409066A (en) 2005-06-15
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WO2005057405A1 (en) 2005-06-23
EP1692612A1 (en) 2006-08-23
JP4689621B2 (en) 2011-05-25
US20050125640A1 (en) 2005-06-09
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MY137354A (en) 2009-01-30
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