EP0177336A3 - Gate array integrated device - Google Patents

Gate array integrated device Download PDF

Info

Publication number
EP0177336A3
EP0177336A3 EP85307023A EP85307023A EP0177336A3 EP 0177336 A3 EP0177336 A3 EP 0177336A3 EP 85307023 A EP85307023 A EP 85307023A EP 85307023 A EP85307023 A EP 85307023A EP 0177336 A3 EP0177336 A3 EP 0177336A3
Authority
EP
European Patent Office
Prior art keywords
gate array
integrated device
array integrated
gate
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP85307023A
Other versions
EP0177336A2 (en
EP0177336B1 (en
Inventor
Yoshihisa Takayama
Kazuyuki Kawauchi
Shigeru Fujii
Toshihiko Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59206144A external-priority patent/JPH0828481B2/en
Priority claimed from JP59220447A external-priority patent/JPH0828482B2/en
Priority claimed from JP59220450A external-priority patent/JPH07105479B2/en
Priority claimed from JP59274504A external-priority patent/JPS61156751A/en
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0177336A2 publication Critical patent/EP0177336A2/en
Publication of EP0177336A3 publication Critical patent/EP0177336A3/en
Application granted granted Critical
Publication of EP0177336B1 publication Critical patent/EP0177336B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • H10D89/213—Design considerations for internal polarisation in field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
EP85307023A 1984-10-03 1985-10-01 Gate array integrated device Expired - Lifetime EP0177336B1 (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP206144/84 1984-10-03
JP59206144A JPH0828481B2 (en) 1984-10-03 1984-10-03 Gate array master slice integrated circuit device
JP59220447A JPH0828482B2 (en) 1984-10-22 1984-10-22 Clip method in gate array master slice integrated circuit device
JP59220450A JPH07105479B2 (en) 1984-10-22 1984-10-22 Clip method in gate array master slice integrated circuit device
JP220447/84 1984-10-22
JP220450/84 1984-10-22
JP274504/84 1984-12-28
JP59274504A JPS61156751A (en) 1984-12-28 1984-12-28 Semiconductor integrated circuit

Publications (3)

Publication Number Publication Date
EP0177336A2 EP0177336A2 (en) 1986-04-09
EP0177336A3 true EP0177336A3 (en) 1987-04-15
EP0177336B1 EP0177336B1 (en) 1992-07-22

Family

ID=27476294

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85307023A Expired - Lifetime EP0177336B1 (en) 1984-10-03 1985-10-01 Gate array integrated device

Country Status (4)

Country Link
US (1) US4661815A (en)
EP (1) EP0177336B1 (en)
KR (1) KR900005150B1 (en)
DE (1) DE3586385T2 (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62119936A (en) * 1985-11-19 1987-06-01 Fujitsu Ltd Complementary lsi chip
US4884118A (en) * 1986-05-19 1989-11-28 Lsi Logic Corporation Double metal HCMOS compacted array
JPS62276852A (en) * 1986-05-23 1987-12-01 Mitsubishi Electric Corp Semiconductor integrated circuit device
EP0248266A3 (en) * 1986-06-06 1990-04-25 Siemens Aktiengesellschaft Logic circuit with a plurality of complementary field effect transistors
JPH0789568B2 (en) * 1986-06-19 1995-09-27 日本電気株式会社 Integrated circuit device
JPH0738414B2 (en) * 1987-01-09 1995-04-26 株式会社東芝 Semiconductor integrated circuit
US4819047A (en) * 1987-05-15 1989-04-04 Advanced Micro Devices, Inc. Protection system for CMOS integrated circuits
JP2606845B2 (en) * 1987-06-19 1997-05-07 富士通株式会社 Semiconductor integrated circuit
JPH0254576A (en) * 1988-08-18 1990-02-23 Mitsubishi Electric Corp Gate array
JPH0727968B2 (en) * 1988-12-20 1995-03-29 株式会社東芝 Semiconductor integrated circuit device
US4928160A (en) * 1989-01-17 1990-05-22 Ncr Corporation Gate isolated base cell structure with off-grid gate polysilicon pattern
US5298774A (en) * 1990-01-11 1994-03-29 Mitsubishi Denki Kabushiki Kaisha Gate array system semiconductor integrated circuit device
JPH04103161A (en) * 1990-08-22 1992-04-06 Toshiba Corp Semiconductor device with bipolar transistor and insulated gate transistor mixedly mounted thereon
US5063429A (en) * 1990-09-17 1991-11-05 Ncr Corporation High density input/output cell arrangement for integrated circuits
JP3084740B2 (en) * 1990-10-30 2000-09-04 日本電気株式会社 Semiconductor integrated circuit
US5155390A (en) * 1991-07-25 1992-10-13 Motorola, Inc. Programmable block architected heterogeneous integrated circuit
US5343058A (en) * 1991-11-18 1994-08-30 Vlsi Technology, Inc. Gate array bases with flexible routing
US5308798A (en) * 1992-11-12 1994-05-03 Vlsi Technology, Inc. Preplacement method for weighted net placement integrated circuit design layout tools
US5757208A (en) * 1996-05-01 1998-05-26 Motorola, Inc. Programmable array and method for routing power busses therein
JP3553334B2 (en) * 1997-10-06 2004-08-11 株式会社ルネサステクノロジ Semiconductor device
JP3526450B2 (en) * 2001-10-29 2004-05-17 株式会社東芝 Semiconductor integrated circuit and standard cell layout design method
JP5594294B2 (en) 2009-12-25 2014-09-24 パナソニック株式会社 Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0119059A2 (en) * 1983-03-09 1984-09-19 Kabushiki Kaisha Toshiba Semiconductor integrated circuit with gate-array arrangement

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4161662A (en) * 1976-01-22 1979-07-17 Motorola, Inc. Standardized digital logic chip
JPH077825B2 (en) * 1981-08-13 1995-01-30 富士通株式会社 Gate array manufacturing method
JPS6017932A (en) * 1983-07-09 1985-01-29 Fujitsu Ltd Gate array
US4602270A (en) * 1985-05-17 1986-07-22 United Technologies Corporation Gate array with reduced isolation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0119059A2 (en) * 1983-03-09 1984-09-19 Kabushiki Kaisha Toshiba Semiconductor integrated circuit with gate-array arrangement

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 26, no. 5, October 1983, pages 2404-2407, New York, US; J.P. BANSAL: "CMOS (N-well) master image chip" *
IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-18, no. 5, October 1983, pages 578-584, New York, US; T. SAIGO et al.: "A 20K-Gate CMOS Gate Array" *
PATENTS ABSTRACTS OF JAPAN, vol. 9, no. 15 (E-291)[1738], 22nd January 1985; & JP-A-59 163 837 (TOSHIBA K.K.) 14-09-1984 *

Also Published As

Publication number Publication date
DE3586385T2 (en) 1993-01-07
DE3586385D1 (en) 1992-08-27
KR900005150B1 (en) 1990-07-20
KR860003662A (en) 1986-05-28
EP0177336A2 (en) 1986-04-09
EP0177336B1 (en) 1992-07-22
US4661815A (en) 1987-04-28

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