CN106951374A - Method and device for checking block page address - Google Patents

Abstract

The invention discloses a method for accessing NVM, which comprises the following steps: processing a first user command instructing to read NVM, checking whether a block address and a page address corresponding to the first user command are the same as a block address and a page address corresponding to a second user command instructing to read NVM, wherein the second user command occurs before the first user command, and the second command accesses the same first parallel unit as the first user command; and if the block address and the page address corresponding to the first user command are the same as those corresponding to the second user command, reading data from the first cache corresponding to the first parallel unit for responding to the first user command. By the technical scheme of the invention, whether the data exists in the cache of the storage controller or not can be flexibly judged, and a user of the storage equipment can participate in flexible control of cache utilization without depending on the storage controller to judge whether the data is cached or not.

Description

Method and device for checking block page address

technical field

The present invention relates to a solid storage device (Solid Storage Device, SSD), and more particularly, the present invention relates to the execution of block/page address checking microinstructions in a memory controller.

Background technique

Similar to mechanical hard drives, solid-state storage devices (SSDs) are high-capacity, non-volatile storage devices used in computer systems. A solid-state storage device generally uses a non-volatile memory (NVM, Non Volatile Memory) such as a flash memory (Flash) as a storage medium. As shown in FIG. 1 , it is a block diagram of a storage system in the prior art. It mainly includes a host system 110 and a solid-state storage device 120 . Wherein, the solid state storage device 120 includes an interface module 130 , a storage controller 140 , and a Flash array 160 composed of a plurality of flash memory particles 150 . Wherein, the interface module 130 is mainly used to realize the interface protocol of communication with the host system, such as SATA (Serial Advanced Technology Attachment, serial advanced technology attachment), USB (Universal Serial Bus, universal serial bus), PCIE (Peripheral Component Interconnect Express, Fast Peripheral Component Interconnect), NVMe (NVM Express), SCSI (Small Computer System Interface, Small Computer System Interface), iSCSI (internet Small Computer System Interface, Internet Small Computer System Interface), IDE (Integrated Drive Electronics, integrated drive electronics )Wait. Through the interface module 130, the solid-state storage device presents to the host system as a standard storage device with a certain logical address space or physical address space. The storage controller 140 is the control core of the entire storage device, and is mainly responsible for the transmission of control signals and data between the interface module 130 and the flash memory array 160, flash memory management, conversion or mapping from the logical address of the host computer to the physical address of the flash memory, wear leveling, and /or bad block management etc. The storage controller 140 can be realized in various ways of software, hardware, firmware or combinations thereof.

The storage controller 140 accesses the flash memory particles 150 by sending commands to the flash memory particles 150 in the flash memory array 160 . Commands for accessing the flash memory particles 150 include, for example, reading, programming and/or erasing. Data is written or read from the flash memory particles 150 by page. The flash memory particle 150 provides a predetermined page size, and the size of each page is, for example, 2KB, 4KB, 8KB or 16KB.

The file system or device driver of the host 110 also accesses the storage device according to data blocks of a predetermined size. A data block of a predetermined size may be called a block, page, or sector. Here the size of the data block is the same as or different from the page size of the flash memory particle 150 .

In the Chinese patent application with publication number CN1414468A, a solution for processing CPU (Central Processing Unit, central processing unit) instructions by executing microinstruction sequences is provided. When the CPU wants to process a specific instruction, the conversion logic circuit converts the specific instruction into a corresponding microinstruction sequence, and realizes the function of the specific instruction by executing the microinstruction sequence. The microinstruction sequence or the template of the microinstruction sequence is stored in a ROM (Read Only Memory, read-only memory). In the process of converting a specific instruction into a microinstruction sequence, the microinstruction sequence template can be filled to correspond to the specific instruction.

The memory target (Target) is one or more logic units (Logic Unit) sharing a chip enable (CE, Chip Enable) signal in the package of the flash memory particle 150 . Each logical unit has a logical unit number (LUN, Logic Unit Number). A NAND flash memory package may include one or more dies. Typically, a logic unit corresponds to a single die. A logical unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, while multiple logic units within a NAND flash chip can execute commands and report status independently of each other. available from

In the "Open NAND Flash Interface Specification (Revision 3.0)" obtained from http://www.micron.com/～/media/Documents/Products/Other%20Documents/ONFI3_0Gold.ashx, it provides information about the target (target), logic unit , LUN, plane (Plane) meaning.

Chinese patent application publication number CN102177556A discloses a flash translation layer (FTL), which shows an example of a look-up table for a parallel unit of the FTL. Since logic units in a flash memory chip can be accessed in parallel, the parallel units can be logic units. A logic unit may include multiple planes, and a parallel unit may also be a plane.

Contents of the invention

In some application scenarios, the page size of the NVM is different from the page size requested by the application. For example, the data unit size of the IO access request of the operating system is 512 bytes, while the page size of the NVM is 4KB, 8KB or 16KB. After reading data from NVM in response to an IO access request, a large amount of read data is not used by the current IO request. However, due to the locality of data access or other reasons, the data read from the NVM may be used in subsequent IO access requests. Therefore, when it is necessary to read data from the flash memory particles, it is desirable to have a flexible way to determine whether the data already exists in the cache memory of the storage controller. There are many reasons why data is cached, and it is hoped that the method of judging whether data already exists in the cache of the storage controller can adapt to different reasons. And it is expected that users of storage devices can participate in flexible control of cache utilization, rather than relying on the storage controller to determine whether data is cached.

To achieve the above object, the present invention responds to commands from the host or the user through the execution of microinstruction sequences. The microinstruction execution unit executes the sequence of microinstructions to issue operation commands to the flash memory particles and/or receive data or other information read from the flash memory particles. Users of the memory device are able to participate in flexible control of the memory controller's cache utilization through programming, updating and/or modifying the sequence of microinstructions.

According to a first aspect of the present invention, a method for accessing NVM is provided, including: processing a first user command indicating to read NVM, and checking that the block address and page address corresponding to the first user command correspond to the second user command Whether the block address and the page address are the same, wherein the second user command indicates to read NVM, the second user command appears before the first user command, and the second command is the same as the first user command Accessing the same first parallel unit; if the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, from the first cache corresponding to the first parallel unit Data is read out for responding to the first user command.

According to an implementation manner of the first aspect of the present invention, it further includes: if the block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command, sending an NVM read command to the NVM.

According to an embodiment of the first aspect of the present invention, the first cache is provided for the first user command accessing the first parallel unit, and the second cache is provided for the first user command accessing the second parallel unit.

According to an implementation manner of the first aspect of the present invention, wherein, in response to the second user command, data corresponding to the block address and page address read from the NVM and corresponding to the second user command are written into the First cache.

According to an embodiment of the first aspect of the present invention, wherein, if the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, a flag register is set; and if the The block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command, and the flag register is cleared.

According to an embodiment of the first aspect of the present invention, wherein, if the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, jump to execute the first microinstruction sequence , to read data from the first cache corresponding to the first parallel unit; and if the block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command, jump Turn to execute the second microinstruction sequence to send the NVM read command to the NVM.

According to an implementation manner of the first aspect of the present invention, wherein, in response to the first user command, if the block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command , further reading data corresponding to the block address and page address corresponding to the first user command from the NVM, and writing it into the first cache.

According to an implementation manner of the first aspect of the present invention, the first user command corresponds to a first segment address, and the second user command corresponds to a second segment address.

According to an implementation manner of the first aspect of the present invention, the first user command indicates to acquire data in a first address range, and the second user command indicates to acquire data in a second address range.

According to an implementation manner of the first aspect of the present invention, wherein, in response to the second user command, the page data corresponding to the block address and the page address corresponding to the second user command are read from the NVM and written into the In the first cache, the page data includes first segment data and second segment data.

According to an embodiment of the first aspect of the present invention, it further includes: processing a third user command indicating to read NVM, accessing the second parallel unit according to the third user command, and reading from NVM with the third user command The block address corresponding to the command and the data corresponding to the page address are written into the second cache.

According to an implementation manner of the first aspect of the present invention, wherein, if the flag register is set, jump to execute the first microinstruction sequence to read data from the first cache corresponding to the first parallel unit; And if the flag register is cleared, jump to execute the second microinstruction sequence to send the NVM read command to the NVM.

According to the second aspect of the present invention, there is also provided a method for accessing NVM, including: processing a first user command indicating to read NVM, and checking that the block address and page address corresponding to the first user command correspond to the second user command Whether the block address and the page address are the same, wherein the second user command indicates writing to NVM, the second user command appears before the first user command, and the second command is identical to the first user command Access to the same parallel unit; if the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, read data from the cache corresponding to the parallel unit for Responding to the first user command.

According to an implementation manner of the second aspect of the present invention, it further includes: if the block address and page address corresponding to the user command are different from the block address and page address corresponding to the second user command, sending an NVM read command to the NVM.

According to a third aspect of the present invention, there is also provided a NVM controller, including: a microinstruction memory, used to store microinstruction sequences; a microinstruction execution unit, used to decode the microinstructions and execute the microinstructions corresponding operation; a program counter for indicating a storage location of a microinstruction in a microinstruction memory; a general-purpose register set, wherein a register in the general-purpose register set can be accessed by a microinstruction in the microinstruction sequence; a user command memory for Store user commands; context storage, used to store context information corresponding to microinstruction sequences.

According to an embodiment of the third aspect of the present invention, wherein, according to the program counter, the microinstruction execution unit obtains the first microinstruction from the microinstruction memory; the microinstruction execution unit decodes the first microinstruction, when When the first microinstruction is a read address check microinstruction, the microinstruction execution unit accesses the user command memory according to the offset value of the read address check microinstruction, and obtains the first block address and the first page address; the microinstruction executes The unit accesses the context memory to obtain the second block address and the second page address stored in the context information of the current microinstruction sequence; the microinstruction execution unit compares the first block address with the second block address, and the first page address with the second page address Two page addresses, if the first block address is identical to the second block address, and the first page address is identical to the second page address, the microinstruction execution unit then checks the register index of the microinstruction according to the read address and sets the general The general-purpose register in the register file indicated by the register index.

According to an embodiment of the third aspect of the present invention, wherein, if the first block address is different from the second block address, or the first page address is different from the second page address, the microinstruction execution unit will A register index of a read address checking microinstruction clears a general purpose register in a general purpose register set indicated by the register index; and the microinstruction execution unit increments the program counter.

According to an implementation manner of the third aspect of the present invention, wherein the microinstruction execution unit accesses the user command memory, and further obtains the address of the first parallel unit; the microinstruction execution unit accesses the user command memory, according to the first parallel unit address The unit address obtains the second block address and the second page address stored in the context information of the current microinstruction sequence.

According to an embodiment of the third aspect of the present invention, wherein the execution of the microinstruction sequence is initiated in response to a user command in the user command memory, and the first execution of the microinstruction sequence is performed according to the parallel unit accessed by the user command. A context memory, the microinstruction execution unit accesses the first context memory to obtain the second block address and the second page address stored in the context information of the current microinstruction sequence.

According to the fourth aspect of the present invention, there is also provided an NVM controller, including: a microinstruction memory, used to store microinstruction sequences; a microinstruction execution unit, used to decode the microinstructions and execute the microinstructions corresponding operation; a program counter, used to indicate the storage location of the microinstructions in the microinstruction memory; a user command memory, used to store user commands; a context memory, used to store context information corresponding to the microinstruction sequence.

According to an implementation manner of the fourth aspect of the present invention, wherein, according to the program counter, the microinstruction execution unit obtains the first microinstruction from the microinstruction memory, and the microinstruction execution unit decodes the first microinstruction, when When the first microinstruction is a read address check microinstruction, the microinstruction execution unit accesses the user command memory according to the offset value of the read address check microinstruction, and obtains the first block address and the first page address; the microinstruction executes The unit accesses the context memory to obtain the second block address and the second page address stored in the context information of the current microinstruction sequence; the microinstruction execution unit compares the first block address with the second block address, and the first page address with the second page address Two page addresses, wherein, if the first block address is the same as the second block address, and the first page address is the same as the second page address, the microinstruction execution unit checks the first address of the microinstruction according to the read address The address sets the program counter; if the first block address is different from the second block address, or the first page address is different from the second page address, the microinstruction execution unit increments the program counter to the second address.

According to an implementation manner of the fourth aspect of the present invention, wherein, according to the program counter, the microinstruction execution unit obtains the first microinstruction from the microinstruction memory, and the microinstruction execution unit decodes the first microinstruction, when When the first microinstruction is a read address check microinstruction, the microinstruction execution unit accesses the user command memory according to the offset value of the read address check microinstruction, and obtains the first block address and the first page address; the microinstruction executes The unit accesses the context memory to obtain the second block address and the second page address stored in the context information of the current microinstruction sequence; the microinstruction execution unit compares the first block address with the second block address, and the first page address with the second page address Two page addresses, wherein, if the first block address is different from the second block address, or the first page address is different from the second page address, the microinstruction execution unit checks the first address of the microinstruction according to the read address. The address sets the program counter; if the first block address is the same as the second block address, and the first page address is the same as the second page address, the microinstruction execution unit increments the program counter to the second address.

According to an implementation manner of the fourth aspect of the present invention, the context memory further stores data read from the second block address and the second page address of the NVM before processing the user command.

According to an implementation manner of the fourth aspect of the present invention, wherein the context memory further stores data written to the second block address and the second page address of the NVM before processing the user command.

According to an implementation manner of the fourth aspect of the present invention, wherein the microinstruction memory stores a sequence of microinstructions for obtaining data from the cache starting from the first address.

According to an implementation manner of the fourth aspect of the present invention, wherein the microinstruction memory stores a sequence of microinstructions for issuing an NVM read command to the NVM starting from the second address.

According to an implementation manner of the fourth aspect of the present invention, wherein the microinstruction memory stores a microinstruction sequence for issuing an NVM read command to the NVM starting from the first address.

According to an implementation manner of the fourth aspect of the present invention, wherein the microinstruction memory stores a sequence of microinstructions for obtaining data from the cache starting from the second address.

According to the fifth aspect of the present invention, there is also provided a method for executing a read address checking microinstruction in an NVM interface controller, including: fetching a first microinstruction; decoding the first microinstruction, and determining the first microinstruction A microinstruction is a read address check microinstruction, wherein the read address check microinstruction includes a register index and an offset value, and the register index is used to indicate a flag register storing the execution result of the read address check instruction, and the offset The value is used to indicate the storage location of the user command; the first block address and the first page address corresponding to the user command are obtained according to the offset value; the second block address and the first page address are obtained according to the context information of the read address check microinstruction. The second page address, if the first block address is the same as the second block address, and the first page address is the same as the second page address, then set the flag register according to the register index; the first block address and the second block address different, or the address of the first page is different from the address of the second page, the flag register is cleared according to the register index.

According to a sixth aspect of the present invention, there is also provided a method for executing a read address check microinstruction in an NVM interface controller, including: fetching the read address check microinstruction, wherein the read address check microinstruction includes a register index With an offset value, the register index is used to indicate the flag register storing the execution result of the read address check instruction, and the offset value is used to indicate the storage location of the user command; the read address check microinstruction is decoded; Obtain the first block address and the first page address corresponding to the user command according to the offset value; obtain the second block address and the second page address according to the context information of the read address check microinstruction, if the first The block address is the same as the second block address, and the first page address is the same as the second page address, then the flag register is set according to the register index; if the first block address is different from the second block address, or the first page address is the same as the second page address If the addresses of the two pages are different, the flag register is cleared according to the register index.

According to an implementation manner of the sixth aspect of the present invention, the second block address and the second page address are a block address and a page address for accessing NVM corresponding to a user command occurring before the user command.

According to an implementation manner of the sixth aspect of the present invention, the user command indicates to read the data of the storage location corresponding to the first block address and the first page address of the NVM.

According to an implementation manner of the sixth aspect of the present invention, the remaining user commands are commands indicating to read data from the NVM or to write data to the NVM.

According to the seventh aspect of the present invention, there is also provided a method for executing a read address check microinstruction in an NVM interface controller, including: fetching the read address check microinstruction, wherein the read address check microinstruction includes a register index With an offset value, the register index is used to indicate the flag register storing the execution result of the read address check instruction, and the offset value is used to indicate the storage location of the user command; the read address check microinstruction is decoded; Obtaining the first parallel unit address, the first block address and the first page address corresponding to the user command according to the offset value; obtaining the second block address and the second page address according to the first parallel unit address, wherein, If the first block address is the same as the second block address, and the first page address is the same as the second page address, then set the flag register according to the register index; if the first block address is different from the second block address, or the first page address is the same as the second page address; If the address of the first page is different from the address of the second page, the flag register is cleared according to the register index.

According to an implementation manner of the seventh aspect of the present invention, the second block address and the second page address are block addresses and page addresses corresponding to other user commands that occur before the user command for accessing the NVM.

According to an implementation manner of the seventh aspect of the present invention, the user command indicates to read the data of the storage location corresponding to the first block address and the first page address of the NVM.

According to an implementation manner of the seventh aspect of the present invention, the remaining user commands are commands indicating to read data from the NVM or to write data to the NVM.

According to an eighth aspect of the present invention, there is also provided a method for executing a read address check microinstruction in an NVM interface controller, comprising: fetching the read address check microinstruction, wherein the read address check microinstruction includes a register index and an offset value, the register index is used to indicate the flag register storing the execution result of the read address check instruction, the offset value is used to indicate the storage location of the user command, and the read address check instruction also includes a first address ; Decode the read address check microinstruction; obtain the first block address and the first page address corresponding to the user command according to the offset value; obtain the second block according to the context information of the read address check microinstruction address and the second page address, wherein, if the first block address is the same as the second block address, and the first page address is the same as the second page address, then the program counter of the NVM interface controller is set to the A first address; where the microinstruction sequence for obtaining data from the cache is stored starting from the first address.

According to an embodiment of the eighth aspect of the present invention, wherein, if the address of the first block is different from the address of the second block, or the address of the first page is different from the address of the second page, the program of the NVM interface controller The counter is set to a second address; wherein the second address starts storing a sequence of microinstructions that issue an NVM read command to the NVM.

According to an implementation manner of the eighth aspect of the present invention, wherein, if the first block address is the same as the second block address, and the first page address is the same as the second page address, the method further includes: setting according to the register index flags register.

According to an embodiment of the eighth aspect of the present invention, wherein, if the first block address is different from the second block address, or the first page address is different from the second page address, the method further includes: clearing the flags register.

According to a ninth aspect of the present invention, there is also provided a method for executing a read address check microinstruction in an NVM interface controller, including: fetching the read address check microinstruction, wherein the read address check microinstruction includes a register index and an offset value, the register index is used to indicate the flag register storing the execution result of the read address check instruction, the offset value is used to indicate the storage location of the user command, and the read address check instruction also includes a first address ; Decode the read address check microinstruction; obtain the first block address and the first page address corresponding to the user command according to the offset value; obtain the second block according to the context information of the read address check microinstruction address and the second page address, if the first block address is the same as the second block address, and the first page address is different from the second page address, then the program counter of the NVM interface controller is set to the first address; where the first address starts to store a sequence of microinstructions that issue an NVM read command to the NVM.

According to an implementation manner of the ninth aspect of the present invention, wherein, if the first block address is different from the second block address, or the first page address is different from the second page address, the program of the NVM interface controller The counter is set to a second address; wherein the second address begins to store a sequence of microinstructions for obtaining data from the cache.

According to an implementation manner of the ninth aspect of the present invention, wherein, if the first block address is the same as the second block address, and the first page address is the same as the second page address, the method further includes: setting according to the register index flags register.

According to an implementation manner of the ninth aspect of the present invention, wherein, if the first block address is different from the second block address, or the first page address is different from the second page address, the method further includes: clearing the flags register.

According to a tenth aspect of the present invention, there is provided a computer program comprising computer program code which, when loaded into and executed on a computer system, causes the computer system to perform the method described above.

According to an eleventh aspect of the present invention, there is provided a program including program code, and when loaded into and executed on a storage device, the program code causes the storage device to execute the method described above.

Through the technical solution of the present invention, it is possible to flexibly determine whether data exists in the cache of the storage controller, and the user of the storage device can participate in the flexible control of cache utilization without relying on the storage controller to determine whether the data is cached.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. Also throughout the drawings, the same reference numerals are used to designate the same parts. Wherein in the drawings, letter marks after reference numerals indicate a plurality of identical components, and when referring to these components generally, the last letter marks thereof will be omitted. In the attached picture:

FIG. 1 shows a block diagram of a storage system in the prior art;

Fig. 2 shows the structural block diagram of the parts of processing microinstructions of the memory controller according to one embodiment of the present invention;

FIG. 3 shows a schematic diagram of the format of a block/page read address check microinstruction according to an embodiment of the present invention;

Fig. 4-1 shows the flowchart of the method for accessing NVM according to an embodiment of the present invention;

Fig. 4-2 shows the flowchart of the method for accessing NVM according to an embodiment of the present invention;

Fig. 4-3 shows the flowchart of the method for accessing NVM according to an embodiment of the present invention;

FIG. 5 shows a flowchart of a method for accessing NVM according to another embodiment of the present invention;

FIG. 6A shows a flow chart of a method for executing a read address check microinstruction in an NVM interface controller according to an embodiment of another aspect of the present invention;

6B shows a flow chart of a method for executing a read address check microinstruction in an NVM interface controller and its subsequent operations according to another embodiment of another aspect of the present invention;

FIG. 7A shows a flow chart of a method for executing a read address check microinstruction in an NVM interface controller according to an embodiment of another aspect of the present invention; and

FIG. 7B shows a flowchart of a method for executing a read address checking microinstruction in an NVM interface controller and its subsequent operations according to an embodiment of another aspect of the present invention.

In the drawings, the same or similar reference numerals are used to refer to the same or similar elements.

detailed description

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

FIG. 2 shows a structural block diagram of components for processing microinstructions of a memory controller according to an embodiment of the present invention. To implement processing of microinstructions, the memory controller of the storage device may include a microinstruction execution unit 210 , a command queue 220 , an interface controller 230 , a microinstruction memory 240 , a context memory 260 and/or a general register 250 .

The microinstruction memory 240 is used to store microinstructions. The microinstruction execution unit 210 reads and executes microinstructions from the microinstruction memory 240 . The microinstructions make the microinstruction execution unit 210 send commands to the flash memory particles through the interface controller 230 to access the flash memory particles, including, for example, reading, programming, erasing, suspending, reading the characteristics of the flash memory particles and/or reading the characteristics of the flash memory particles Wait for the order. The microinstructions also enable the microinstruction execution unit 210 to obtain the data read from the flash memory particles through the interface controller 230 . One microinstruction or multiple microinstructions may correspond to one of commands for accessing flash memory particles such as read, program, erase and/or suspend. The microinstructions also include branch and jump microinstructions, which cause the microinstruction execution unit to change the order in which microinstructions are executed. Microinstructions also include block/page read address checking microinstructions. The block/page read address checking microinstruction will be introduced in detail later in conjunction with FIG. 3 .

One or more microinstruction sequences can be stored in the microinstruction memory 240 . As an example, in the microinstruction memory 240 in FIG. 2 , n segments of microinstruction sequences are stored, including microinstruction sequence 1 , microinstruction sequence 2 . . . and microinstruction sequence n. Each segment of microinstruction sequence 1 , microinstruction sequence 2 . . . and microinstruction sequence n includes a plurality of microinstructions.

Multiple microinstructions in the microinstruction sequence can be executed by the microinstruction execution unit 210 . Each microinstruction sequence has its own execution state, so that the execution of each microinstruction can be suspended and resumed. The microinstruction executing unit 210 can suspend the executing microinstruction sequence and choose to execute other microinstruction sequences. A yielding microinstruction may also be provided in the microinstruction sequence. When the yielding microinstruction is executed, the microinstruction execution unit 210 may schedule and execute other microinstruction sequences. When the microinstruction execution unit 210 suspends the microinstruction sequence being executed, or executes the concession microfinger, the execution state of the microinstruction sequence being executed is preserved; when the microinstruction execution unit resumes the execution of the microinstruction sequence, the saved Execution state, thereby continuing execution of the resumed sequence of microinstructions.

The interface controller 230 is coupled with the flash memory particle, and is used to issue commands to the flash memory particle to access the flash memory particle, including, for example, reading, programming, erasing, suspending and/or resuming, etc.; The data.

The command queue 220 is used for buffering commands from users or upper systems. Commands from the user or the upper system can include commands such as read, write, delete, and mark as invalid, and can also include commands such as reading storage device status, reading/setting flash memory particle characteristics, and user-defined commands . The command queue 220 can be realized by a memory, a first-in-first-out memory register file, and the like. The microinstruction execution unit 210 can access the command queue 220 . For example, when executing a microinstruction, the microinstruction execution unit 210 accesses the command queue 220 according to the microinstruction.

When processing a command in the command queue 220 , the microinstruction sequence corresponding to the command is obtained, and the microinstruction execution unit 210 executes the microinstruction sequence to complete the processing of the command in the command queue 220 . Conversion from processing commands in command queue 220 to sequences of microinstructions may be accomplished by conversion circuitry (not shown). The conversion from processing commands in the command queue 220 to microinstruction sequences can also be implemented by the microinstruction execution unit 210 . During the process of obtaining the microinstruction sequence, the microinstruction sequence may be filled or adapted based on the commands in the command queue 220 , so that the microinstruction sequence is compatible with the commands in the command queue 220 . The microinstruction sequence also controls the microinstruction execution unit 210 to access and process commands in the command queue 220 . And according to the commands in the command queue 220, the corresponding microinstruction sequence is selected and executed.

The general purpose register 250 is coupled to the microinstruction execution unit 210 and is used for saving and providing the execution state of the microinstruction sequence. The execution state of the microinstruction sequence includes a program counter (PC), a general register (GR), a physical address register and/or a timer, and the like. The program counter is used to indicate the address of the currently executing microinstruction in the sequence of microinstructions. The physical address register is used to indicate the address of the flash memory particle accessed by the microinstruction sequence.

The context memory 260 is used to store the execution state of the microinstruction sequence. The execution state of the sequence of microinstructions stored in the context memory 260 may include the contents of the general purpose registers 250 . In the context memory 260, the execution state of one or more microinstruction sequences may be saved. Microinstruction sequences that store state information in the context memory 260 can be scheduled to resume execution. By restoring the state information corresponding to a microinstruction sequence stored in the context memory 260 to the general register 250, the microinstruction execution unit 210 can resume the execution of the microinstruction sequence. The sequence of microinstructions executed is called a thread. Each execution of the same sequence of microinstructions has its own execution state, allowing multiple threads to be created based on the same sequence of microinstructions. In context memory 260, execution state is stored for each thread.

In an embodiment in accordance with the invention, threads are created or used based on the parallel units to be accessed. For example, the first thread is used to access the first parallel unit, and/or the second thread is used to access the second parallel unit. In one example, the number of threads that the context memory 260 can hold is the same as the number of parallel units of the flash memory particles coupled to the parts that process the microinstructions of FIG. 2; for each parallel unit, threads are allocated or reserved; When a request is made, schedule the thread corresponding to this unit of parallelism. In one example, the number of threads that the context memory 260 can accommodate is less than the number of parallel units coupled to the microinstruction-processing components of FIG. 2 . When processing a request for a parallel unit, use the thread already allocated to process the parallel unit or allocate a new thread to handle the request.

A parallel unit cache is provided to store data read from or written to the parallel unit. Provides a parallel unit cache for each thread. The size of the parallel cell cache corresponds to the page size of the flash particle 150 (see FIG. 1 ). It is beneficial to provide a larger size parallel cell cache to improve performance. In one example, a parallel unit cache is provided in context memory 260 . In another example, the parallel unit cache is provided by DRAM or other memory external to the microinstruction-processing components of FIG. 2 .

FIG. 3 shows the format of a block/page read address check microinstruction according to an embodiment of the present invention. The block/page read address checking microinstruction includes an operation code (OpCode) field, a register (Reg) field and an offset value (Offset) field. The opcode field indicates by a specific identifier or value that the uop is a block/page read address checking uop. The register field indicates the name or number of the general register (see FIG. 2, general register 250) modified by the block/page read address check microinstruction. The offset value field indicates the position of the command corresponding to the block/page read address checking microinstruction in the command queue 220 (see FIG. 2 ). In one example, the offset value field indicates where the command to be checked is stored in the command queue 220 . For example, the command to be checked is a read command or a program command that was processed before the command currently being processed.

In one example, the value indicated by the offset value field is accumulated on the base address to obtain the storage location of the command in the command queue 220 . Note that the base address field is not included in the block/page read address check microinstruction, but provides a global base address register or base address index for the thread or each microinstruction, so that when the block/page read address check microinstruction is executed The base address can be obtained at instruction time. In another example, the storage position of the command in the command queue 220 is obtained by using the offset value field alone. In yet another example, the offset value field indicates the offset of the checked command from the command currently being processed. In yet another example, the offset value field is a register address or number, so that the offset value information can be modified at runtime by modifying the content of the register through the execution of the microinstruction sequence.

In the command in the command queue 220, the parallel unit address, block address and page address accessed by the command are provided, so that based on the parallel unit address, block address and page address, the specific location of the specific flash memory particle 150 (see FIG. 1 ) can be determined. blocks and pages. For example, a combination of a block address and a page address provided by the command indexed by the offset value field in the command queue 220 (refer to FIG. 2 ) is represented by user_cmd[base+offset].block_page_address.

In the embodiment according to the present invention, each thread is provided with a block address register and a page address register, which can be used as thread context, for storing the block address and the page address respectively. The block address and the page address can be stored in various ways, for example, the combination of the block address and the page address is stored in the same register. For example, block_page_address represents a combination of a block address and a page address as a thread context. Microinstructions belonging to the same thread can access the block address and page address as the thread context.

When executing the block/page read address check microinstruction according to the present invention, the microinstruction execution unit 210 (referring to FIG. 2 ) compares the block address and page address as the thread context with the block of the command in the command queue 220 processed by the thread Whether the address is the same as the page address, and if they are the same, the general register indicated by the register (Reg) field of the microinstruction is checked to be set at the block/page read address. If the block address and the page address as the thread context are different from the block address and the page address of the command in the command queue 220 processed by this thread, the general purpose indicated by the register (Reg) field of the block/page read address check microinstruction Registers are cleared. A register set operation may correspond to writing a logic "1" or a logic "0" in a specific location of the register, and a register clear operation writes a value in the specific location of the register inversely to the register set operation. As an example, the semantic representation of the block/page read address checking microinstruction is as follows: GR[Reg]=(block_page_address==user_cmd[base+offset].block_page_address)? 1:0. When block_page_address is the same as user_cmd[base+offset].block_page_address, set the general register GR[Reg] to 1, otherwise to 0.

In an embodiment according to the present invention, a conditional branch microinstruction is also provided. When the conditional branch microinstruction is executed, the specified general register is checked. The conditional branch microinstruction sets the program counter (PC) to one of two different values according to the specified general-purpose register being set or cleared, to instruct the microinstruction execution unit 210 to fetch the next request from a different location in the microinstruction memory 240. microinstructions executed.

In yet another embodiment of the present invention, the operations of the block/page read address check microinstruction and the conditional branch microinstruction are combined to provide a fused microinstruction. The fused microinstruction includes a branch target field in addition to an operation code (OpCode) field, a register (Reg) field, and an offset value (Offset) field.

When executing the fused microinstruction, the microinstruction execution unit 210 (see FIG. 2 ) compares whether the block address and page address as the thread context are the same as the block address and page address of the commands in the command queue 220 processed by the thread. According to the comparison result, the program counter (PC) is set to different values to instruct the microinstruction execution unit 210 to obtain the next microinstruction to be executed from different locations in the microinstruction memory. For example, when the comparison result is true, instruct the microinstruction execution unit 210 to obtain the microinstruction to be executed from the next microinstruction address of the current microinstruction; The microinstruction to be executed is fetched at the address indicated by the field. In this way, it is no longer necessary to use separate block/page read address check microinstructions and conditional branch microinstructions, but the conditional branch semantics is integrated into the execution block/page read address check microinstructions, thereby reducing the length of the microinstruction sequence, and The storage space occupied by the microinstruction sequence in the microinstruction memory 240 is reduced.

In another embodiment according to the present invention, when executing yet another fused microinstruction, the microinstruction execution unit 210 (referring to FIG. 2 ) compares the block address and the page address as the thread context with the command queue 220 processed by the thread. Whether the block address of the command is the same as the page address. According to the comparison result, the program counter (PC) is set to different values to indicate that the microinstruction execution unit 210 obtains the next microinstruction to be executed from different positions of the microinstruction memory; and, the block/page read address check microinstruction The general register indicated by the register (Reg) field of the instruction is set or cleared.

Fig. 4-1 shows a flowchart of a method for accessing NVM according to an embodiment of the present invention.

As shown in Figure 4-1, the method for accessing NVM includes: step 410: process the first user command; step 420: check whether the block address and page address of the first user command correspond to the block address and page address of the second user command Same; Step 430: If the block address and page address of the first user command are the same as the block address and page address corresponding to the second user command, get data from the first cache.

In step 410, as an example, the first user command is a first read command, and processing of the first read command starts. Referring back to FIG. 2 , the next command to be processed is obtained from the command queue 220 and determined to be the first read command. The microinstruction execution unit 210 executes a corresponding microinstruction sequence to process the first read command. In step 420, the microinstruction executing unit 210 executes the block/page read address checking microinstruction (also referring to FIG. 3 ) provided according to the present invention to judge the block address and/or page address of the first read command and the second user command's Whether the block address and/or page address are the same. The second user command is a command obtained and processed by the microinstruction execution unit 210 from the command queue 210 before processing the first read command. If they are the same, proceed to step 430 to obtain the data required by the first read instruction from the cache. In an embodiment according to the present invention, the second user command may be a read command or a write command, and when the second user command is processed, the data corresponding to the block address and/or page address of the second user command is moved to the cache . Thus when the first read command has the same block address and/or page address as the second user command, the data required by the first read command already exists in the cache, and the data to be read by the first read command can be obtained from the cache. data, and there is no need to issue an NVM read command, thereby speeding up the processing speed of the first read command.

Fig. 4-2 shows a flowchart of a method for accessing NVM according to an embodiment of the present invention.

As shown in Figure 4-2, the method for accessing NVM includes: step 410: process the first user command; step 420: check whether the block address and page address of the first user command correspond to the block address and page address of the second user command Same; Step 430: If the block address and page address of the first user command are the same as the block address and page address corresponding to the second user command, get data from the first cache. The method for accessing NVM shown in Figure 4-2 further includes step 440: if the block address and page address corresponding to the second user command are different from the block address and page address of the first user command, send an NVM read command to NVM .

4-3 show a flowchart of a method for accessing NVM according to an embodiment of the present invention.

As shown in Figure 4-3, the method for accessing NVM includes: step 410: process the first user command; step 420: check whether the block address and page address of the first user command correspond to the block address and page address of the second user command Same; step 430: if the block address and page address of the first user command are identical to the block address and page address corresponding to the second user command, obtain data from the first cache; step 440: if the block address of the first user command and The page address is different from the block address and page address corresponding to the second user command, and an NVM read command is sent to the NVM. In the method for accessing NVM shown in FIG. 4-3 , after sending an NVM read command to the NVM at step 440, it further includes step 450: reading data from the NVM, and writing the data into the first cache.

In step 450, in response to the second user command, write data corresponding to the block address and the page address read from the NVM and corresponding to the second user command into the first cache.

In a further embodiment, a dedicated cache is allocated for each parallel unit (LUN) of the NVM, so that when accessing the cache (such as moving data to the cache or moving data out of the cache), the address of the cache can be easily obtained, and Reduced cache management overhead.

Example 1

In Embodiment 1 of the present invention, a page of NVM includes multiple sectors, the first read command and the second user command access the same parallel unit, and carry the same block address and page address, but the accessed sector Different, where the first command accesses the first sector and the second user command accesses the second sector. The second user command is a read command and is put into the command queue (see FIG. 2, command queue 220) before the first read command. Although the second user command reads the data of the second sector, the NVM interface can transfer data by page size. When accessing NVM according to the second user command, the entire page data including the second sector is transferred to the cache . The first read command is then placed into the command queue 220 . The first read command is processed by executing microinstructions (see FIG. 4-1, step 410). Execute the block/page read address check microinstruction, compare the block address and page address of the first read command and the second user command (see Figure 4-1, step 420), and find the block address of the first read command and the second user command the same block address, and the page address of the first read command is the same as the page address of the second user command. This means that due to the execution of the second user command, the data required by the first read command has already been moved into the cache. As an example, a block/page read address check microinstruction is executed, and a flag is set in a general register (see FIG. 2, general register 250) according to the comparison result. The next microinstruction decides to execute the microinstruction corresponding to step 430 according to the set flag. Therefore, continue to execute microinstructions to fetch data from the cache (see FIG. 4-1, step 430). In this way, the data to be accessed can be obtained without sending a data read command to the NVM, which saves the execution time of the first read command and improves efficiency.

Example 2

In Embodiment 2 of the present invention, a page is a basic unit for reading NVM, and the first read command and the second user command access the same parallel unit and carry the same block address and page address. The second user command is a read command and is put into the command queue (see FIG. 2, command queue 220) before the first read command. Therefore, the first read command and the second user command are consecutive read commands for the same address. When accessing the NVM according to the previous second user command, the entire page of data is transferred into the cache. The first read command is then placed into the command queue 220 . The first read command is processed by executing microinstructions (see FIG. 4-1, step 410). Execute the block/page read address check microinstruction, compare the block address and the page address (step 420) of the first read command and the second user command, find that the block address of the first read command is identical with the block address of the second user command, and The page address of the first read command is the same as the page address of the second user command. This means that due to the execution of the second user command, the data required by the first read command has already been moved into the cache. Therefore, continue to execute microinstructions to fetch data from the cache (step 430). In this way, the data to be accessed can be obtained without sending a data read command to the NVM, which saves the execution time of the first read command and improves efficiency.

Example 3

In Embodiment 3 of the present invention, a page is a basic unit for reading NVM, and the first read command and the second user command access the same parallel unit. However, the block address and/or page address carried by the first read command and the second user command are different. The second user command is a read command and is put into the command queue (see FIG. 2, command queue 220) before the first read command. When accessing the NVM according to the previous second user command, the entire page of data is transferred into the cache. The first read command is then placed into the command queue 220 . The first read command is processed by executing microinstructions (see FIG. 4-3, step 410). Execute the block/page read address check microinstruction, compare the block address and the page address (step 420) of the first read command and the second user command, find that the block address of the first read command is different from the block address of the second user command, or The page address of the first read command is different from the page address of the second user command. Therefore, the data required by the first read command is not in the cache with high probability. As an example, a block/page read address check microinstruction is executed, and a flag is set in a general register (see FIG. 2, general register 250) according to the comparison result. The next microinstruction decides to execute the microinstruction corresponding to step 440 according to the set flag. Thus, the microinstructions continue to be executed to issue the NVM read command to the NVM (step 440). The microinstructions issue NVM read commands by operating the interface controller (see FIG. 2, interface controller 230). And receiving the data read from the NVM and writing the data into the cache by executing microinstructions (step 450 ). When the block address and the page address of the third user command appearing in the command queue (referring to FIG. 2, command queue 220) after the first read command are respectively identical with the block address and the page address of the first read command, it means that the third The data to be accessed by the user command already exists in the buffer. Data required by the third user command can be obtained from the cache without sending a data read command to the NVM.

Fig. 5 shows a flowchart of a method for accessing NVM according to another embodiment of the present invention. By executing the microinstruction sequence, the microinstruction execution unit 210 (see FIG. 2 ) executes the method for accessing NVM shown in FIG. 5 .

As shown in Figure 5, the method for accessing NVM includes: step 510: processing the first read command; step 520: reading the first data from NVM, and writing the first data into the first cache; step 530: processing the second read command : Step 540: check whether the block address and the page address of the first read command are identical to the block address and the page address of the second read command; Step 550: if the block address and the page address of the first read command are the same as the block address of the second read command Address is identical with page address, obtains the first data from the first cache; Step 560: if the block address of the first read command and the page address are not identical with the block address of the second read command and the page address, send the NVM read command; Step 570: Obtain second data read from the NVM, and write the second data into the cache.

In step 510, when an unprocessed first read command appears in the command queue 220 (shown in FIG. 2 ), the first read command is processed by executing a sequence of microinstructions. In step 520, read data from the NVM according to the first read command by executing the microinstruction sequence, and write the read data into the cache. In one example, when reading data from NVM according to the first read command, the block/page read address check microinstruction according to the present invention is also executed, and it is determined that the block address and page address of the first read command are different from the previous read /write the block address and page address of the command, so as to send the NVM read command to the NVM according to the first read command. In another example, according to the fact that the first read command is the only read command or write command in the command queue 220 (see FIG. 2 ), it is determined that the data required by the first read command does not exist in the cache. In step 530, in response to the occurrence of the second read command in the command queue, the second read command is processed by executing a sequence of microinstructions. In step 540, execute the block/page read address checking microinstruction according to the present invention, and determine the block address and page address of the second read command and the previous read/write command (in this example, the first read command) Whether the block address and page address are the same.

If the block address and page address of the second read command are the same as the block address and page address of the first read command, it means that the data required by the second read command has been moved to the cache by the execution of the first read command , in step 550, obtain the data required by the second read command from the cache by executing corresponding microinstructions. In a further example, the processing of the first read command has not been completed, the processing of the second read command is temporarily suspended, and after the data is retrieved by the first read command, the processing of the second read command is resumed, and Obtain data required by the second read command from the cache.

If the block address and page address of the second read command are different from the block address and page address of the first read command, it means that the possibility that the data required by the second read command is in the cache is extremely low. In step 560, by executing micro The instruction issues an NVM read command to the NVM. In step 570, the data read from the NVM is obtained by executing the microinstruction, and the data is written into the cache.

Describe in detail by the following specific examples:

Example 4

In Embodiment 4 of the present invention, the preceding first user command in the command queue 220 (see FIG. 2 ) is a write command, and the subsequent second user command is a read command. The first user command and the second user command access the same parallel unit and carry the same block address and page address. In response to an unprocessed first user command occurring in the command queue 220, the data to be written by the first user command is moved to the cache by executing the microinstruction sequence, and the NVM is sent to the NVM by the interface controller 230 (see FIG. 2 ). programming commands. In response to an unprocessed second user command occurring in the command queue 220, the block/page read address check microinstruction according to the present invention is executed by the microinstruction execution unit 210 (referring to FIG. 2 ) to determine that the first user command and the second user command access The block address is the same as the page address respectively. Based on this, it is judged that the data required by the second user command exists in the cache, and the data is obtained from the cache by executing the microinstruction.

Example 5

In Embodiment 5 of the present invention, the first user command preceding in the command queue 220 (see FIG. 2 ) is a write command, and the second user command following is a read command. The first user command and the second user command access the same parallel unit and carry the same block address and page address. The first user command is to write a full page of data, while the second user command reads out a portion of the page data. The part of the page data to be read is indicated by the address range carried in the second user command. In response to an unprocessed first user command occurring in the command queue 220, the entire page of data to be written by the first user command is transferred to the cache by executing the microinstruction sequence, and sent to the NVM by the interface controller 230 (see FIG. 2 ). Issue the NVM programming command. In response to an unprocessed second user command occurring in the command queue 220, the block/page read address check microinstruction according to the present invention is executed by the microinstruction execution unit 210 (referring to FIG. 2 ) to determine that the first user command and the second user command access The block address is the same as the page address respectively. Based on this, it is judged that the data required by the second user command exists in the cache, and the required partial page data is obtained from the cache by executing the microinstruction.

Example 6

In Embodiment 6 according to the present invention, the first user command in front of the command queue 220 (see FIG. 2) is a read command, and the second user command after the first user command is a read ID command. The third user command after the command is a read command. The first user command and the third user command access the same parallel unit and carry the same block address and page address. In response to an unprocessed first user command occurring in the command queue 220, the data to be written by the first user command is moved to the cache by executing the microinstruction sequence, and the NVM is sent to the NVM by the interface controller 230 (see FIG. 2 ). programming commands. In response to an unprocessed second user command appearing in the command queue 220, an NVM read ID command is issued to the NVM by executing a sequence of microinstructions. In response to the unprocessed third user command occurring in the command queue 220, the block/page read address check microinstruction according to the present invention is executed by the microinstruction execution unit 210 (referring to FIG. 2 ) to determine that the first user command and the second user command access The block address is different from the page address, and the block/page read address check microinstruction according to the present invention is executed again to determine that the block address accessed by the first user command and the third user command are the same as the page address respectively. Based on this, it is judged that the data required by the third user command exists in the cache, and the data is obtained from the cache by executing the microinstruction.

Example 7

In Embodiment 7 according to the present invention, the first user command in front of the command queue 220 (see FIG. 2 ) is a read command, and the second user command after the first user command is a Set Feature command. The third user command after the command is a read command. The first user command and the third user command access the same parallel unit and carry the same block address and page address. In response to an unprocessed first user command occurring in the command queue 220, the data to be written by the first user command is moved to the cache by executing the microinstruction sequence, and the NVM is sent to the NVM by the interface controller 230 (see FIG. 2 ). programming commands. In response to an unprocessed second user command appearing in the command queue 220, an NVM Set Feature command is issued to the NVM by executing the microinstruction sequence. In response to an unprocessed third user command occurring in the command queue 220, determining that the second user command in the command queue by executing the microinstruction will cause the data expected by the third user command to be different from the data read by the first user command, Therefore, the block/page read address check microinstruction according to the present invention is no longer executed or the checking result of the block/page read address check microinstruction is ignored, and the NVM read command is sent to the NVM according to the third user command.

FIG. 6A shows a flow chart of a method for executing a read address checking microinstruction in an NVM interface controller according to an embodiment of another aspect of the present invention.

As shown in Figure 6A, the method for executing the read address checking microinstruction in the NVM interface controller includes: step 610: obtaining the first microinstruction; step 620: decoding the first microinstruction, and determining that the first microinstruction is a read address checking microinstruction instruction; step 630: obtain the first block address and the first page address corresponding to the user command; step 640: check whether the first block address and the first page address are the same as the stored block address and page address, and if they are the same, enter Step 650: Set the flag register; if not, go to step 660: Clear the flag register.

In step 610 , the microinstruction execution unit 210 fetches the block/page read address checking microinstruction from the specified location of the microinstruction memory 240 (see FIG. 2 ) according to the program counter (PC) in the general register 250 . As an example, the block/page read address checking microinstruction is a microinstruction in the sequence of microinstructions for processing a read command. In step 620, the microinstruction execution unit 210 decodes the microinstruction read from the microinstruction memory 240, and determines that the microinstruction is a block/page read address checking microinstruction. In step 630, the microinstruction execution unit 210 checks the offset value field (see FIG. 3 ) of the microinstruction according to the block/page read address to access the command queue 220, and obtains therefrom the block address and the page address of the first command before the current read command . The microinstruction execution unit 210 also acquires the block address and page address of the current read command from the context memory 260 . In step 640, the microinstruction execution unit 210 compares whether the block address and page address of the first command are the same as the block address and page address of the current read command. If identical, in step 650, microinstruction execution unit 210 checks the flag register in the general purpose register 250 provided by the general register index provided by the Reg field (referring to Fig. 3) of block/page read address inspection microinstruction; If not identical, in step 660 , the microinstruction execution unit 210 clears the flag register in the general register 250 according to the general register index provided by the Reg field (see FIG. 3 ) of the microinstruction checked by the block/page read address.

In the above example, the microinstruction execution unit 210 acquires the block address and page address of the current read command from the context memory 260 .

Optionally, in another embodiment according to the present invention, a second offset value field is provided in the block/page read address check microinstruction to indicate the storage of the current read command in the command queue 220 (see FIG. 2 ). Location. And the microinstruction execution unit 210 obtains the block address and the page address of the current read command from the command queue 220 according to the second offset value field, and compares it with the block address and the page address of the first command indicated by the first offset value field Compare.

Still optionally, in another embodiment according to the present invention, the microinstruction execution unit 210 (see FIG. 2 ) maintains a context identifier to identify the context of the microinstruction sequence, especially the context of the microinstruction sequence in the context memory 260 (see Figure 2). This eliminates the need to indicate a context identifier in every microinstruction. The microinstruction execution unit 210 obtains the block address and page address of the current read instruction from the context memory 260 according to the context identifier.

Still optionally, in another embodiment according to the present invention, unprocessed commands in the command queue 220 (see FIG. 2 ) cause the microinstruction execution unit 210 (see FIG. 2 ) to execute the microinstruction sequence, provided in the command The context identifier is used to identify the context of the microinstruction sequence, especially the storage location of the context of the microinstruction sequence in the context memory 260 (see FIG. 2 ). And store the block address and page address carried in the command in the context storage 260 . When executing the block/page address checking microinstruction, the microinstruction execution unit 210 (see FIG. 2 ) obtains the block address and page address of the current read instruction from the context memory 260 according to the context identifier.

Still optionally, in another embodiment according to the present invention, unprocessed commands in the command queue 220 (see FIG. 2 ) cause the microinstruction execution unit 210 (see FIG. 2 ) to execute the microinstruction sequence, provided in the command parallel unit identifier, and use the parallel unit identifier to identify the context of the microinstruction sequence, especially the storage location of the context of the microinstruction sequence in the context memory 260 (see FIG. 2 ). Commands that access the same parallel unit are thus assigned the same context. And store the block address and page address carried in the command in the context storage 260 . When executing the block/page address checking microinstruction, the microinstruction execution unit 210 obtains the block address and page address of the current read instruction from the context memory 260 according to the parallel unit identifier.

Still optionally, in another embodiment according to the present invention, the microinstruction execution unit 210 (see FIG. 2 ) maintains a thread identifier for identifying the thread to which the microinstruction sequence belongs. And the context information of the thread is stored in the context memory 260 (see FIG. 2 ). And the storage location of the thread context in the context memory 260 is determined according to the thread identifier. The microinstruction execution unit 210 obtains the block address and page address of the current read instruction from the context memory 260 according to the thread identifier.

FIG. 6B shows a flowchart of a method for executing a read address checking microinstruction in an NVM interface controller and its subsequent operations according to another embodiment of another aspect of the present invention.

As shown in Figure 6B, after executing the read address check microinstruction in the NVM interface controller, also check the execution result of the microinstruction according to the read address, execute step 680 to read data from the first cache; or execute step 670: read from the NVM output the second data, and write the second data into the first cache.

In step 680, the follow-up microinstruction (for example, branch microinstruction) of the block/page read address check microinstruction checks the flag register, and is set according to the flag register, correspondingly revises the value of the program counter (PC), so that the microinstruction execution unit The next microinstruction is obtained according to the value of the updated program counter (PC), and the data required by the current read command is read from the cache by executing the next microinstruction and subsequent microinstruction sequence. In step 670, the block/page read address checks the follow-up microinstruction (for example, branch microinstruction) of the microinstruction to check the flag register, according to the flag register is cleared, correspondingly revises the value of the program counter PC, makes the microinstruction execution unit according to the updated The value of the program counter PC obtains the next microinstruction, and by executing the next microinstruction and the subsequent microinstruction sequence, an NVM read command is issued to the NVM, and the data read from the NVM is obtained and written into the cache.

FIG. 7A shows a flow chart of a method for executing a read address checking microinstruction in an NVM interface controller according to an embodiment of another aspect of the present invention.

As shown in Figure 7A, the method for performing read address checking microinstruction in NVM interface controller comprises: Step 710: obtain the first microinstruction; Step 720: decode the first microinstruction, determine that the first microinstruction is a read address inspection microinstruction Instruction; step 730: obtain the first block address and the first page address corresponding to the user command; step 740: check whether the first block address and the first page address are the same as the stored second block address and the second page address, if they are the same If yes, go to step 750: set the program counter to the first address; if not, go to step 760: set the program counter to the second address.

In step 710 , the microinstruction execution unit 210 fetches the first microinstruction from the specified location of the microinstruction memory 240 (see FIG. 2 ) according to the program counter (PC) in the general purpose register 250 . In step 720, the microinstruction execution unit 210 decodes the first microinstruction read from the microinstruction memory 240, and determines that the first microinstruction is a block/page read address checking microinstruction. In step 730, the microinstruction execution unit 210 checks the offset value field (see FIG. 3 ) of the microinstruction according to the block/page read address to access the command queue 220, and obtains therefrom the block address and the page address of the first command before the current read command . The microinstruction execution unit 210 also acquires the block address and page address of the current read command from the context memory 260 . In step 740, the microinstruction execution unit 210 compares whether the block address and page address of the first command are the same as the block address and page address of the current read command. If the same, in step 750, the program counter (PC) in the general-purpose register 250 is set to the first value by the microinstruction execution unit 210; (PC) is set as the second value. So far, the execution of the block/page read address checking microinstruction is completed.

FIG. 7B shows a flowchart of a method for executing a read address checking microinstruction in an NVM interface controller and its subsequent operations according to an embodiment of another aspect of the present invention.

As shown in FIG. 7B , after the read address check microinstruction is executed in the NVM interface controller, the execution result of the read address check microinstruction is also checked, and step 770 is performed: obtaining the second microinstruction from the address indicated by the program counter.

In step 770, the microinstruction execution unit 210 (referring to FIG. 2 ) obtains the next microinstruction according to the value of the updated program counter PC, and by executing the next microinstruction and subsequent microinstruction sequence, when the program counter is set in step 750 When the value of PC was set to the first value, the microinstruction execution unit read out the required data of the current read command from the buffer memory by executing the next microinstruction and the subsequent microinstruction sequence; when the value of the program counter PC in step 760 When it is set to the second value, the microinstruction execution unit executes the next microinstruction and the subsequent microinstruction sequence, sends an NVM read command to the NVM, obtains the data read from the NVM, and writes it into the cache.

In an optional embodiment, the microinstruction is checked by executing the block/page read address, and when the program counter (PC) is set to the first value by the microinstruction execution unit 210 (see FIG. Check the flag register in the general register index set general register 250 that the Reg field (referring to Fig. 3) of microinstruction that provides; The general register index provided by the Reg field (see FIG. 3 ) of the read address check microinstruction clears the flag register in the general register 250 .

An example of NVM in the present invention is flash memory. Those skilled in the art will appreciate that embodiments of the present invention are also applicable to other types of storage media, such as phase change memory, resistive memory, ferroelectric memory, and the like.

According to one aspect of the present invention, the present invention also provides a computer program comprising computer program code, which when loaded into a computer system and executed on the computer system, causes the computer system to perform the above-mentioned method.

According to another aspect of the present invention, there is also provided a program including program code. When loaded into a storage device and executed on the storage device, the program code causes the storage device to execute the method described above.

Through the technical solution of the present invention, it is possible to flexibly determine whether data exists in the cache of the storage controller, and the user of the storage device can participate in the flexible control of cache utilization without relying on the storage controller to determine whether the data is cached.

It will be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by various means including computer program instructions. These computer program instructions can be loaded into a general purpose computer, special purpose computer, or other programmable data controlled device to produce a machine, whereby the instructions executed on the computer or other programmable data controlled device create a process for implementing one or more flow chart blocks device for the functions specified in .

These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data-controlled device to act in a specific manner, so that the instructions stored in the computer-readable memory can be used to manufacture, including for implementing a or an article of manufacture of computer readable instructions for the functions specified in the flowchart blocks. Computer program instructions can also be loaded onto a computer or other programmable data-controlled device to cause a series of operational steps to be performed on the computer or other programmable data-controlled device, thereby producing a computer-implemented process, which in turn can be performed on the computer or other programmable data-controlled device. The instructions executed on the control device provide steps for implementing the functions specified in one or more of the flowchart blocks.

Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of steps for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or combinations of special purpose hardware and computer instructions.

At least some of the various blocks, operations, and techniques described above can be performed using hardware, controlling a device executing firmware instructions, controlling a device executing software instructions, or any combination thereof. When executed by a control device that executes firmware and software instructions, the software or firmware instructions can be stored in any computer-readable storage medium, such as a magnetic disk, optical disk or other storage medium, in RAM or ROM or flash memory, control device, hard disk , discs, disks and more. Likewise, software and firmware instructions may be transmitted to the user or system by any known or desired transmission means including, for example, on a computer readable disk or other portable computer storage mechanism or via a communication medium. Communication media typically embodies computer readable instructions, data structures, sequence modules or other data in a modulated data signal such as a carrier wave or other transport mechanism. By way of example, and not limitation, communication media includes wired media such as a wired network or a single-wire connection, and wireless media such as acoustic, radio frequency, infrared and other wireless media. Thus, software and firmware instructions may be transmitted to a user or system over a communication channel, such as a telephone line, DSL line, cable television line, fiber optic cable, wireless channel, the Internet, etc. (providing such software via a portable storage medium, are considered the same or interchangeable). The software or firmware instructions may include machine readable instructions which, when executed by the control device, cause the control device to perform various actions. When implemented in hardware, the hardware may include one or more discrete components, integrated circuits, application integrated circuits (ASICs), and the like.

It should be understood that the present invention can be realized by pure software, pure hardware, firmware and various combinations of the above. Hardware can be, for example, control devices, application-specific integrated circuits, large-scale integrated circuits, and the like.

Although the present invention has been described with reference to examples, it is for the purpose of explanation only and not to limit the present invention, changes, additions and/or deletions to the embodiments may be made without departing from the scope of the present invention.

Many modifications and other embodiments of the inventions described herein will come to mind to those skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the particular embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims (10)

1. A method of accessing NVM comprising: Processing a first user command indicating to read NVM, checking whether the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, wherein the second user command indicates to read NVM , the second user command appears before the first user command, and the second command accesses the same first parallel unit as the first user command; If the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, read data from the first cache corresponding to the first parallel unit to respond to the Describe the first user command. 2. The method of claim 1, further comprising: If the block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command, send an NVM read command to the NVM. 3. The method of claim 1, wherein a first buffer is provided for a first user command accessing a first parallel unit, and a second buffer is provided for a first user command accessing a second parallel unit. 4. The method according to claim 2, wherein, in response to the second user command, the data corresponding to the block address and the page address read from the NVM and corresponding to the second user command are written into the first a cache. 5. The method according to any one of claims 1-4, wherein, If the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, setting a flag register; and If the block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command, the flag register is cleared. 6. The method of claim 5, wherein, If the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command, jump to execute the first microinstruction sequence to start from the first microinstruction corresponding to the first parallel unit read data from the cache; and If the block address and page address corresponding to the first user command are different from the block address and page address corresponding to the second user command, jump to execute the second microinstruction sequence to send an NVM read command to the NVM. 7. The method according to claim 3 or 4, wherein, in response to the first user command, if the block address and page address corresponding to the first user command are the same as the block address and page address corresponding to the second user command Differently, the data corresponding to the block address and the page address corresponding to the first user command are further read from the NVM, and written into the first cache. 8. The method according to any one of claims 1-7, wherein the first user command corresponds to a first segment address, and the second user command corresponds to a second segment address. 9. A NVM controller comprising: A microinstruction memory for storing microinstruction sequences; The microinstruction execution unit is used to decode the microinstruction and execute the operation corresponding to the microinstruction; a program counter for indicating the storage location of the microinstruction in the microinstruction memory; a general-purpose register set, wherein registers in the general-purpose register set can be accessed by microinstructions in the microinstruction sequence; a user command memory for storing user commands; and The context memory is used to store context information corresponding to the microinstruction sequence. 10. The NVM controller according to claim 9, wherein according to the program counter, the microinstruction execution unit obtains the first microinstruction from the microinstruction memory, The microinstruction execution unit decodes the first microinstruction, and when the first microinstruction is a read address inspection microinstruction, the microinstruction execution unit accesses the user command memory according to the offset value of the read address inspection microinstruction, and obtains The first block address and the first page address; the microinstruction execution unit accesses the context memory to obtain the second block address and the second page address stored in the context information of the current microinstruction sequence; the microinstruction execution unit compares the second page address One block address and the second block address, the first page address and the second page address; if the first block address is the same as the second block address, and the first page address is the same as the second page address, the microinstruction is executed The unit then sets the general register indicated by the register index in the general register set according to the register index of the read address checking microinstruction.