KR100996421B1 - Apparatus and method for synchronization in channel card of mobile communication system - Google Patents

Abstract

The present invention relates to an apparatus and a method for synchronization in a channel card of a mobile communication system. In the channel card apparatus for synchronizing a digital signal processing (DSP) modem and a system clock in a mobile communication system, a reference signal indicating a transmission start is provided. The DSP modem transmitted to the field-programmable gate array (FPGA) modem and the time point at which the reference signal is received are compared with the GPS timer to record the GPS timer value at that time, and are recorded at a predefined GPS timer reference time point. Including the FPGA modem for transmitting the GPS timer value to the DSP modem, it is possible to provide synchronization between the DSP modem and the system clock and the channel card in the channel card consisting of a DSP modem and the FPGA modem.

Channel card, frame sync, system clock, digital signal processing (DSP), field-programmable gate array (FPGA).

Description

Apparatus and method for synchronization in channel card of mobile communication system {APPARATUS AND METHOD FOR SYNCHRONIZING CHANNEL CARD IN WIRELESS COMMUNICATION SYSTEM}

1 is a block diagram of a first channel card in a mobile communication system according to the prior art;

2 is a block diagram of a second channel card in a mobile communication system according to the prior art;

3 is an FPGA modem apparatus in a channel card according to an embodiment of the present invention;

4 is an exemplary GPS timer counter in a channel card according to the present invention;

5 is a detailed block diagram of an input / output matching unit in an FPGA modem in a channel card according to an embodiment of the present invention;

6 is a flowchart for synchronizing a system clock with a DSP modem in a channel card according to an embodiment of the present invention;

7 illustrates a downlink (DL) data format according to an embodiment of the present invention;

8 illustrates an uplink (UL) data format according to an embodiment of the present invention;

9 is an exemplary diagram for explaining synchronization between channel cards according to an embodiment of the present invention.

The present invention relates to an apparatus and method for channel card synchronization in a mobile communication system, and more particularly, to an apparatus and method for synchronization between a digital signal processing (DSP) modem and a system clock and channel card in the channel card.

In a current mobile communication system, a base station generates a signal to be transmitted to a terminal through a channel card or restores a signal received from the terminal. For example, in an orthogonal frequency division multiplexing (OFDM) wireless communication system, a channel card generates an OFDM signal or restores an OFDM signal. In addition, in the CDMA wireless communication system, the channel card performs spreading signal generation and spreading signal recovery functions.

1 shows a block diagram of a first channel card device according to the prior art.

Referring to FIG. 1, a channel card includes a digital signal processor (DSP) modem 100, a field-programmable gate array (FPGA) formatter 102, and an electrically programmable logic device (EPLD) 104. .

The DSP modem 100 performs signal processing such as modulation and demodulation functions (eg, OFDM modulation and CDMA modulation and demodulation) through algebraic operations on digital data obtained by A / D (analog / digital) conversion of analog signals. The DSP modem 100 is operated by receiving a DSP processing clock from an oscillator (OSC) 106. The EPLD 104 generates a signal capable of controlling the FPGA formatter 102 to provide system clocks such as 80 ms / 5 ms / 50 ms required for the operation of the FPGA formatter 102. The FPGA formatter 102 matches the signal of the DSP modem 100 to transmit to the IF board 110 for transmission to the IF (InterFace) board 110.

However, when data processing is performed in the DSP modem 100 consisting purely of DSP as shown in FIG. 1, the system clock (for example, 80 ms and 5 ms) may be accepted through an interrupt or an event during synchronization. The absence of an interface requires a specific protocol for system synchronization.

Figure 2 shows a block diagram of a second channel card device according to the prior art.

Referring to FIG. 2, since the modems in the channel card structure of DSP and field-programmable gate array (FPGA) modems 200 and 202 actually perform data processing and generation in the FPGA, a separate protocol is required for synchronization. none.

However, in FIG. 2, when the second channel card outputs data synchronized with the 100 MHz clock due to the structure of the DSP modem 200 operating by receiving a clock from the local clock (40 MHz), each time the power is turned on / off. There is a problem that a change in the data output point may occur, which may cause a problem when combining data of each channel card output terminal in the IF board. That is, when the data from the DSP modem (SW Modem) 200 is designed to be accommodated in the FPGA formatter 204 as it is in the prior art, the channel processing may be performed between the channel card and other channel cards due to the DSP processing clock at every power on / off. Synchronization can be lost, and the current DSP modem can't handle the system clock because it can't directly receive the system clock and process it in hardware.

Therefore, there is a need for an apparatus and method for processing synchronization between a DSP modem and an FPGA modem and channel card synchronization in a channel card using a DSP modem and an FPGA modem.

Accordingly, an object of the present invention is to provide an apparatus and method for synchronizing a DSP modem with a system clock in a channel card.

Another object of the present invention is to provide an apparatus and method for synchronization between DSP modem data outputs in a channel card.

Another object of the present invention is to provide an apparatus and method for synchronization between channel cards in a mobile communication system.

According to a first aspect of the present invention for achieving the above objects, in a mobile communication system, a DSP (Digital Signal Processing) modem and a channel card device for system clock synchronization, the reference signal indicating the start of the transmission is FPGA (Field- Programmable Gate Array (DSP) modem and the time of receiving the reference signal are compared with the GPS timer to record the GPS timer value at that time, and the GPS timer value recorded at a predefined GPS timer reference time point. It characterized in that it comprises the FPGA modem for transmitting to the DSP modem.

According to a second aspect of the present invention for achieving the above object, in a method for system clock synchronization in a DSP (Digital Signal Processing) modem of a channel card, a reference signal indicating the start time of data transmission is FPGA (Field-Programmable) Gate array) and compares the time at the time of receiving the reference signal with a GPS timer, records the GPS timer value at that time, and records the GPS timer value recorded at a predefined GPS timer reference time. And transmitting downlink traffic data along with the adjusted downlink starting time information to the FPGA modem by adjusting downlink starting time information with reference to the GPS timer value. It is done.

According to a third aspect of the present invention for achieving the above objects, a method for synchronizing between channel cards in an FPGA modem of a channel card, the method comprising receiving downlink traffic data from the DSP modem and writing it to a DPRAM; After the time delay of, characterized in that it comprises the step of reading downlink traffic from the DPRAM.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed descriptions of related well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.

Hereinafter, an apparatus and method for synchronizing a DSP modem with a system clock and synchronizing between channel cards in a channel card will be described. In the following description, downlink refers to a channel direction from a DSP (Digital Signal Processing) modem to a field-programmable gate array (FPGA) modem, and uplink refers to a channel direction from an FPGA modem to a DSP modem.

3 is a block diagram of a field-programmable gate array (FPGA) modem device in a channel card according to an embodiment of the present invention. Here, the device diagram of the FPGA modem 202 is mainly focused on the synchronization function between the DSP modem 200 and the system clock synchronization and the data output of the DSP modem 200, and other original modem functions may be added.

Referring to FIG. 3, the FPGA modem 202 includes a GPS timer 300, an input / output matching unit 302, and an MGT matching unit 304.

The GPS timer 300 receives a system clock (e.g., 80 ms) from the GPS (Global Positioning System (hereinafter, referred to as "GPS") to generate a frame clock (5 ms), and "Clock_advanced" and "Clock_retard" functions. , Downlink start point (UL Start), and time synchronization information with the DSP modem. For example, when the GPS timer 300 receives the downlink start signal from the DSP modem, the GPS timer 300 records the downlink start time in a register in comparison with the GPS timer counter value. Thereafter, the downlink start time information recorded in the register is transmitted to the DSP modem at the time of transmitting the uplink start signal to synchronize with the DSP modem using a separate internal clock synchronization. The Clock_advanced function is a function of quickly shifting the downlink reference clock in GPS clock reference processing to compensate for system delay and path delay, and the Clock_retard function is a function to slow down the uplink reference clock.

Referring to FIG. 4, which is an example of a time counter implemented in the GPS timer 300, Modem operation is synchronized based on the GPS counter. First, the GPS timer 300 receives 80 ms clock synchronization information from the GPS. The modem operation is synchronized based on the 80ms GPS counter. Here, since one frame is 5ms, the 80ms (5ms * 16) time counter is counted from 0 to 15 by 4-bit information. The time count for a 5ms frame is 40 times 12500 cycles for 100MHz (5ms = 12500 / 100MHz * 40). Thus, the 5ms frame time counter is counted from 0 to 12499 by 14 bit information. A 100 MHz * 40 cycle time counter is then used for symbol synchronization.

The input / output matching unit 302 formats the timing information and the actual traffic data from the GPS timer 300. That is, after receiving DL data and DL start signal from a DSP modem, the DL start signal is transmitted to the GPS timer 300 and the DL data is a multi-gigabit transceiver. Format the data according to the format and transmit the data to the MGT matching unit 304. In addition, UL data is received from the MGT matching unit 300, system clock information is received from the GPS timer 300, converted to conform to the DSP modem interface standard, and transmitted to the DSP modem 200.

In addition, the input / output matching unit 302 writes downlink traffic data from a DSP modem to a dual-port RAM (DPRAM) in order to solve a timing mismatch between channel cards, and then delays a predetermined time period before the downlink from the DPRAM. Read link traffic data. Referring to FIG. 5, which illustrates the input / output matching unit 302 in detail, the received downlink data is written to the DPRAM, and then the start of the GPS timer reference downlink, which is an absolute time, is set to 10 clocks. After a delay, a read address and a control signal are generated to synchronize data read time from the DPRAM. Therefore, data output from the DPRAM read port is output in synchronization with the GPS clock.

The MGT (Multi Gigabit Transceiver) matching unit 304 performs a function of matching downlink parallel data with serial low voltage differential signaling (LVDS) format with IF (InterFace) or converting uplink serial LVDS input into parallel data. The conversion is transmitted to the input / output matching unit 300.

6 is a flowchart illustrating a system for synchronizing a DSP modem with a system clock in a channel card according to an exemplary embodiment of the present invention. The system clock synchronization means synchronization of a processing clock (eg, 40 MHz) inside the DSP modem with a system clock (eg, 80 MHz) provided to the channel card.

Referring to FIG. 6, first, the DSP modem transmits a DL start message (DL Start message) to an FPGA modem at an arbitrary time point through the downlink after initial system setup in step 600. Referring to FIG. 7 illustrating a downlink data format, the downlink data format includes parallel 16 bit data and 1 bit of a synchronization signal. Here, when the 4 bits, the Least Significant Bit (LSB), are 0xF 1111 in the parallel 16-bit P0 column, the downlink starts, and all others have a value of 0x0 (0000).

In step 602, the FPGA modem compares the time of receiving the downlink start signal with the GPS time. That is, the FPGA modem can know the downlink start time of the DSP modem by referring to LSB 4-bit information of the P0 column of the downlink data format received from the DSP modem.

In step 604, the FPGA modem writes the GPS timer value at the comparison time into an internal register. Here, the GPS timer value is represented by a total of 16 bits, 14 bits of CNT_2 and 2 bits of CNT_3, and the value is recorded in a register. The CNT_2 is a time counter value (0 to 12499) for 5 ms frame synchronization, and the CNT_3 is a time counter value (0 to 3) for symbol synchronization. See FIG. 4 for details.

In step 606, the FPGA modem transmits the GPS timer value of the initial downlink start recorded in the register to the DSP modem at a preset GPS start reference UL start point. The 16-bit data recorded in the register is carried in the (timer) column of the P1 column in the uplink data format of FIG. 8 below. Referring to FIG. 8, which shows the uplink data format, the uplink data format is composed of parallel 16-bit data and a sync signal 1 bit as in the downlink data format. From the downlink data format, the register value in which downlink start time information is stored is transmitted to the DSP modem through 14 bits (b15 to 2) in the P1 column at the uplink start time.

In step 608, the DSP modem adjusts the offset by referring to the time at which the initial downlink start time was transmitted and the downlink start time information contained in the P1 column of the uplink data format. That is, the DSP modem adjusts the downlink start value, which is a GPS time reference, and transmits a downlink start value synchronized with the system clock through a downlink data format, thereby synchronizing with the system clock.

In step 610, the DSP modem regenerates the downlink start signal synchronized with the GPS time.

In step 612, the DSP modem transmits a downlink start signal and traffic data synchronized with GPS time to the FPGA modem.

The channel card then terminates the algorithm of the present invention.

As described above with reference to FIG. 6, the DSP modem adjusts a downlink start value, which is a GPS time reference, and transmits a downlink start value synchronized with the system clock through a downlink data format to match synchronization with the system clock. You can. The DSP modem generates data from an internal core clock to format traffic data to a system clock that is a clock having a different phase and frequency. This causes timing mismatches between channel card outputs due to instability of modem outputs on the board due to the problem that the phases of different frequencies and local clocks are not fixed. A method for solving the timing mismatch problem between channel boards will be described with reference to FIG. 9.

9 illustrates an example for synchronization between channel cards according to an embodiment of the present invention.

Referring to FIG. 9, a memory address is generated in the FPGA internal DPRAM based on an input downlink start time of each data format in the FPGA internal DPRAM for synchronization between channel cards, and is written to the DPRAM. When reading, the synchronization between channel card output between each modem input should be correct, so the downlink start based on the GPS timer, which is an absolute time, is set after the 10 clock delay, which is a sample storage time of DPRAM, based on the read address and time. By generating a control signal, all outputs from the DPRAM read port can be output in synchronization with the GPS clock.

In summary, to keep the initial system synchronized, the DSP modem transfers data to the FPGA modem by any synchronization generated by the local clock. Since the pulse width of the synchronization signal is in units of 100MHz, the synchronization with the 10MHz produced by the GPS does not match. Thus, the FPGA modem writes data from the DSP modem to DPRAM inside the FPGA modem, reads the data back to the GPS clock, and transfers the data to the IF board. In FIG. 6, synchronization means a unit of 10 MHz. In other words, the meaning of the 10MHz period is synchronized between the DSP and the FPGA based on the 10MHz reference. The 100 MHz unit synchronization is synchronized while reading the GPS clock from the DPRAM stage of the FPGA of FIG. 9.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, by transmitting and receiving GPS synchronization information between the DSP modem and the FPGA modem, it is possible to provide synchronization between the DSP modem and the system clock and the channel card in the channel card composed of the DSP modem and the FPGA modem. It is superior in price and performance to existing DSP modems and FPGA modems, and can be more flexible than ASIC-based channel cards.

Claims (19)

A channel card device for synchronizing a system clock with a DSP (Digital Signal Processing) modem in a mobile communication system, A DSP modem for transmitting a reference signal indicating start of transmission to a field-programmable gate array (FPGA) modem; The FPGA modem for recording the GPS timer value at that time by comparing the time of the reference signal with a GPS timer, and transmitting the recorded GPS timer value to the DSP modem at a predefined GPS timer reference time ; Including; The FPGA modem, A GPS timer that receives a system clock from the GPS and records a downlink start time reception time as a GPS timer value; And an input / output matching unit configured to transmit the GPS timer value for the downlink start time reception time to an uplink start time to a DSP modem. And the input / output matching unit outputs the downlink data by storing a downlink data from the DSP modem in a DPRAM and delaying a downlink time point based on a GPS timer by a predetermined clock. The method of claim 1, The DSP modem And adjusting downlink start time information with reference to the GPS timer value. 3. The method of claim 2, The DSP modem And downlink traffic data is transmitted to the FPGA modem together with the adjusted downlink start time information. delete The method of claim 1, MGT matching for receiving downlink traffic data and downlink start time information from the input / output matching unit, transmitting the downlink start time information to the GPS timer, and formatting the downlink traffic data according to a multi-gigabit transceiver (MGT) format. And a unit further comprising a unit. The method of claim 5, The MGT matching unit Downlink parallel data from the input / output matching unit is converted into serial Low Voltage Differential Signals (LVDS) format and matched with an IF (InterFace) board, And converting the uplink serial LVDS input data into parallel data and transmitting the same to the input / output matching unit. delete The method of claim 1, The downlink data format from the DSP modem to the FPGA modem is composed of a parallel 16-bit data and a synchronization signal 1 bit and comprises downlink start information. The method of claim 1, The uplink data format from the FPGA modem to the DSP modem is composed of parallel 16-bit data and a synchronization signal 1 bit, and includes a GPS time reference downlink start information. In the method for system clock synchronization in the DSP (Digital Signal Processing) modem of the channel card, Transmitting a reference signal indicating a start point of data transmission to a field-programmable gate array (FPGA) modem; Compare the time of the reference signal reception time with the GPS timer to record the GPS timer value at that time, and at a predefined GPS timer reference time, Transmitting the recorded GPS timer value to a DSP modem; Adjusting downlink start time information with reference to the GPS timer value to transmit downlink traffic data along with the adjusted downlink start time information to the FPGA modem; And after the downlink traffic data is stored in DPRAM, a downlink time point based on a GPS timer is output with a predetermined clock delay. The method of claim 10, The downlink start time information is represented by predetermined bit information of a timing information frame. The method of claim 11, And said predetermined bit is represented by four bits ("1111") to indicate the start of downlink. The method of claim 10, The GPS timer value is represented by a frame sync timer count value (CNT_2) and a symbol sync timer counter value (CNT_3). The method of claim 10, Receiving the downlink start time information and the downlink traffic data, transmitting the downlink start time information to the GPS timer, and formatting the downlink traffic data according to a multi-gigabit transceiver (MGT) format; A synchronous method, characterized in that. 15. The method of claim 14, The downlink traffic data is converted into a serial Low Voltage Differential Signals (LVDS) format and matched with an IF (InterFace) board. The method of claim 10, The downlink data format from the DSP modem to the FPGA modem is composed of parallel 16-bit data and a synchronization signal 1 bit and comprises downlink start information. The method of claim 10, The uplink data format from the FPGA modem to the DSP modem is composed of parallel 16-bit data and a synchronization signal 1 bit, and includes a GPS time reference downlink start information and uplink start time information. A method for synchronizing between channel cards in an FPGA modem of a channel card, Receiving downlink traffic data from a DSP modem and writing it to DPRAM; After a predetermined time delay, reading downlink traffic from the DPRAM. The method of claim 18, The predetermined time delay is a sample storage time of the DPRAM.

Images