JP4128551B2 - Information processing apparatus and store instruction control method - Google Patents

Description

  The present invention relates to an information processing apparatus and a store instruction control method for executing a store instruction for storing data in a predetermined storage area on a main memory or a cache memory.

Conventionally, there is an information processing apparatus that executes a store instruction for storing data in a predetermined storage area (see, for example, Patent Document 1 below).
FIG. 7 is a block diagram showing a configuration of a conventional information processing apparatus 100. As shown in FIG. 7, the conventional information processing apparatus 100 includes an instruction processing unit 10, an arithmetic unit 20, an address register 21, an arithmetic register 22, store ports 30-0 to 30-n (n is an integer of 0 or more, Here, an integer of 2 or more), an align unit 40, store data buffers 50-0 to 50-n (n is an integer of 0 or more, here an integer of 2 or more), cache memory (storage area) 60, and reset unit 81 Is configured.

  Here, the details of each of the above components of the conventional information processing apparatus 100 shown in FIG. 7 will be described based on the operation thereof. FIG. 8 shows the procedure of the store instruction control method by the conventional information processing apparatus 100 shown in FIG. It is a time chart for demonstrating (operation | movement of the information processing apparatus 100). Note that T1 to T12 in FIG. 8 indicate time units, that is, control clock units in the information processing apparatus 100.

  As shown in FIGS. 7 and 8, in the information processing apparatus 100, first, the instruction processing unit 10 decodes an instruction held in an instruction cache (not shown) (see T1 in FIG. 8). At this time, if the instruction decoded by the instruction processing unit 10 is a store instruction (store request), the instruction processing unit 10 stores the width of data to be stored together with the decoded store instruction (hereinafter referred to as store data width; LENGTH in the figure). ), Alignment instruction information indicating right-justification and left-justification of store data (indicated as ALIGN in the figure), and the number of the address register 21 used for calculation of the store destination address (hereinafter referred to as store address) by the arithmetic unit 20 ( Value) or immediate operand, and the number (value) of the arithmetic register 22 holding data to be stored by the store instruction (hereinafter referred to as store data).

When the address register 21 used for calculation of the store address by the computing unit 20 is determined (see T2 in FIG. 8), the instruction processing unit 10 stores the decoded store instruction, store data width, and alignment instruction information in the store port 30. It is issued to any one of −0 to 30-n (here, store port 30-0) (see T3 in FIG. 8).
On the other hand, when the address register 21 used for calculating the store address is determined (see T2 in FIG. 8), the arithmetic unit 20 executes the store address calculation using the address register 21 (see T3 in FIG. 8). Note that the store address obtained as the calculation result of the arithmetic unit 20 is temporarily held in a storage register (in this case, the address register 21 is an address register 21 because the address register 21 is a general-purpose register).

  Next, the store address calculated by the computing unit 20 is issued to the store ports 30-0 to 30-n (see T4 in FIG. 8). Here, the store address is at least the store port 30-0. A storage area that is an actual store destination using a translation lookaside buffer (TLB) (not shown) by flowing into the pipeline of the storage processing device having ˜30-n and flowing through the pipeline. Here, the cache memory 60 is converted into an address (physical address; hereinafter, simply referred to as a store address if not distinguished from the store address held in the address register 21), and the converted store address is stored in the store port 30. It is issued at −0 (see T4 in FIG. 8). When the issue of the store address from the address register 21 is completed, the address register 21 is released and can be used by other processes.

  The store port 30-0 is information indicating that a store instruction, a store address (physical address), and a store data width have been received (here, a flag; see “VALID”, “ADRS”, and “LENGTH” in FIG. 7). ) When the store instruction is received, the VALID flag 30a is set to the on state, and when the store address is received, the ADRS (Address) flag 30b is set to the on state, and further the store data width is received. And LENGTH flag 30c are set to the on state (see T5 in FIG. 8).

  When the instruction processing unit 10 confirms that the store instruction is issued to the store port 30-0, the instruction processing unit 10 stores the store data to be stored by the store instruction held by the arithmetic register 22 in the store data buffers 50-0 to 50-n ( Here, the issuance lock of the store data from the operation register 22 is released in order to issue it to the store data buffer 50-0) (see T6 in FIG. 8). That is, in the conventional information processing apparatus 100, even if the number (value) of the arithmetic register 22 is fixed, until the store instruction is issued to the store port 30-0, the store data from the arithmetic register 22 is stored. It is configured to suppress (interlock) issuance.

  Next, the store data held in the operation register 22 is issued to the store data buffer 50-0 corresponding to the store port 30-0 (see T7 in FIG. 8). The store data issued from the arithmetic register 22 is aligned using the store data width and alignment instruction information (hereinafter referred to as alignment information) issued to the store port 30-0 together with the store instruction (refer to FIG. 8). Thereafter, the store data aligned by the align unit 40 is held in the store data buffer 50-0 (see T9 in FIG. 8). Note that when the issuance of store data from the arithmetic register 22 is completed, the arithmetic register 22 is released and can be used by other processes.

  The store port 30-0 is configured to hold information (here, a flag; see “RSTDV” in FIG. 7) indicating whether or not store data is held in the store data buffer 50-0. When the store data buffer 50-0 holds the store data issued from the operation register 22, an RSTDV (Received Store Date Valid) flag 30d is set to an on state (see T9 in FIG. 8).

  By the way, when the store address is held in the store port 30-0 (see T5 in FIG. 8), the instruction processing unit 10 extracts the page attribute of the store target area and determines an exception (see T6 in FIG. 8). . That is, the instruction processing unit 10 determines whether or not the store address as the storage target area can be written (stored), and if the store is possible, the instruction processing unit 10 notifies the store port 30-0 that there is no exception, while the store is not possible. If there is an exception, the store port 30-0 is notified that there is an exception, and the execution of the store instruction is cancelled.

  The store port 30-0 is configured to hold information (here, flag; refer to “PSTV” in FIG. 7) indicating the result (existence) of the exception determination, and is received from the instruction processing unit 10. If the exception determination result is no exception, a PSTV (Post Status Valid) flag 30e is set to the on state, while if there is an exception, the PSTV flag 30e is set to the off state.

  Next, the instruction processing unit 10 stores the width of the store instruction, the store address, and the store data in the store port 30-0, the exception determination result of the store instruction is no exception, and the store data is stored in the store data buffer 50- 0 is held (that is, all of the VALID flag 30a, ADRS flag 30b, LENGTH flag 30c, PSTV flag 30e, and RSTDV flag 30d are on), and all instructions preceding the store instruction are completed. Then, it is determined that the store instruction is executable, and store permission is notified to the store port 30-0 (see T10 in FIG. 8).

The store port 30-0 is configured to hold information (here, a flag; see “READY” in FIG. 7) indicating whether or not the store permission has been received from the instruction processing unit 10, and the instruction processing When store permission is received from the unit 10, the READY flag 30f is set to the on state.
When the READY flag 30f of the store port 30-0 is set to the on state, a store instruction is executed (see T11 in FIG. 8), and the cache memory is based on the store address held in the store port 30-0. Store data held in the store data buffer 50-0 is written at a predetermined address at 60, and the store instruction processing is completed (see T12 in FIG. 8).

As described above, in the conventional information processing apparatus 100, the store instruction is always issued first from the instruction processing unit 10 to the store ports 30-0 to 30-n, and thereafter, the store data as the calculation result by the calculator 20 is calculated. It is configured to issue from the register 22 to the store data buffers 50-0 to 50-n, that is, to perform processing in order.
Therefore, as shown in FIG. 7, the conventional information processing apparatus 100 includes a reset unit 81 that can reset the RSTDV flag 30d of the store ports 30-0 to 30-n to an off state. When the issued store instruction is held in the store ports 30-0 to 30-n, the reset unit 81 is configured to reset the RSTDV flag 30d to an off state (see T5 in FIG. 8).

That is, in the conventional information processing apparatus 100, processing is performed in-order. Therefore, when a store instruction is held in the store ports 30-0 to 30-n, the corresponding store data buffers 50-0 to 50-n are stored. Since the store data cannot be held in the storage port 30-0 to 30-n, the reset unit 81 resets the RSTDV flag 30d to the OFF state when the store instruction is held in the store ports 30-0 to 30-n. Has been. As a result, for example, other store data different from the store data that should originally be stored is held in the corresponding store data buffers 50-0 to 50-n, and other data that should not be stored is erroneously stored. Or an error that the store instruction is not executed because the RSTDV flag 30d is erroneously set to the ON state even though the store data buffers 50-0 to 50-n do not hold the store data. Can be done.
Japanese Patent Laid-Open No. 5-289848

  By the way, in the conventional information processing apparatus 100 described above, when the store instruction is issued to the store ports 30-0 to 30-n after the instruction is decoded by the instruction processing unit 10, calculation of the store address by the arithmetic unit 20 is performed. It is necessary that the number (value) of the address register 21 to be used is fixed, and when issuing store data to the store data buffers 50-0 to 50-n, an operation for holding the store data It is necessary that the number (value) of the register 22 is fixed. The order in which the number of the address register 21 and the number of the arithmetic register 22 are determined is not constant.

  However, in the conventional information processing apparatus 100, as described above, the store instruction is always issued first from the instruction processing unit 10 to the store ports 30-0 to 30-n, and then the store data is stored in the store data buffer from the arithmetic register 22. Since the processing is executed in order to issue to 50-0 to 50-n, the number of the arithmetic register 22 is determined before the number of the address register 21 is determined, and the stored data is stored in the arithmetic register 22. Is stored, issuance of store data from the arithmetic register 22 to the store data buffers 50-0 to 50-n until the number of the address register 21 is confirmed and the issue of the store instruction is confirmed. Was locked and had to wait for store data to be issued.

In this way, while waiting for the issuance of store data from the operation register 22 to the store data buffers 50-0 to 50-n, naturally, the operation register 22 holding the store data is also waited for release. 22 could not be used for other operations, and the use efficiency of the operation register 22 was reduced.
The present invention has been devised in view of such problems, and an object of the present invention is to improve the use efficiency of an arithmetic register that holds store data when executing a store instruction.

  In order to achieve the above object, an information processing apparatus of the present invention includes an instruction processing unit that decodes an instruction and issues a processing instruction, and performs an operation according to the operation instruction issued as the processing instruction from the instruction processing unit. An arithmetic unit to be executed, an arithmetic register that holds an arithmetic result by the arithmetic unit, and the arithmetic result that is issued as the processing instruction from the instruction processing unit and stored in the arithmetic register is stored in a predetermined storage area A store port for storing the store instruction and a store data buffer for temporarily storing the operation result issued as store data from the operation register, and the instruction processing unit, in response to the store instruction, When the operation register holding the operation result is confirmed, the operation result is stored as the store data from the operation register to the store data buffer. The store port holds a store data holding flag that is set to an on state when the store data corresponding to the store instruction is held in the store data buffer. And a reset unit that sets the store data retention flag to an off state when the store instruction is retained in the store port, and before the store instruction is retained in the store port, When the store data is held in the store data buffer, the reset unit is prevented from setting the store data holding flag to an off state when the store instruction is held in the store port, and the store data buffer stores the store data. And a deterrence part that maintains the ON state of the data retention flag. It is set to (claim 1).

  Further, an alignment unit for aligning the operation result issued as the store data from the operation register is provided, and the instruction processing unit issues the operation result as the store data from the operation register to the store data buffer. When performing the operation, it is configured to issue alignment information necessary for alignment together with the calculation result and use / non-use information indicating whether or not the alignment information is used in the alignment unit, and use the alignment information in the alignment unit. An alignment information selection unit is further provided for selecting the alignment information from the alignment information issued together with the store data and the alignment information included in the store instruction based on the use / non-use information. (Claim 2).

  At this time, after the instruction processing unit issues the store instruction to the store port, the operation result is issued from the operation register to the store data buffer as the store data. / While setting the non-use information to non-use, the operation result is issued from the operation register to the store data buffer as the store data before the store instruction is issued to the store port. In such a case, it is preferable to set the use / non-use information to use (claim 3).

  A cancel unit for canceling execution of the store instruction; the cancel unit after the store data is issued to the store data buffer; and the store instruction corresponding to the store data is When canceling the store instruction before it is issued to the store port, the store data held in the store data buffer is deleted and the store data holding flag corresponding to the store data is set. It is preferably set to an off state (claim 4).

  Note that when a fetch instruction is issued from the instruction processing unit, a fetch bus for inputting data to be fetched by the fetch instruction from the predetermined storage area to the arithmetic unit or the arithmetic register, and the store data The fetch instruction uses the store data held in the store data buffer by providing store fetch bypass to directly input the store data held in the buffer from the store data buffer to the fetch bus. In this case, it is preferable that the store data is input from the store data buffer to the store fetch bypass.

  In order to achieve the above object, the store instruction control method of the present invention includes an instruction processing unit that decodes an instruction and issues a processing instruction, and an arithmetic instruction issued as the processing instruction from the instruction processing unit. An arithmetic unit that executes an arithmetic operation, an arithmetic register that holds an arithmetic result by the arithmetic unit, and is issued as the processing instruction from the instruction processing unit, and the arithmetic result held in the arithmetic register is stored in a predetermined storage area A store port for storing a store instruction for storing; and a store data buffer for temporarily storing the operation result issued as store data from the operation register, wherein the store port is stored in the store data buffer. When the store data corresponding to the store instruction is held, a store data holding flag that is set to an on state is held. A store instruction control method for controlling execution of the store instruction issued from the instruction processing unit in the configured information processing apparatus, wherein the instruction processing unit holds the operation register holding the operation result. Then, the calculation result is issued as the store data from the calculation register to the store data buffer, and the store instruction is held in the store port before the store data is held in the store data buffer. When the store instruction is held in the store port, the store data holding flag is set to an off state, while the store data is stored before the store instruction is held in the store port. Is stored in the store data buffer, the store instruction is stored in the store port. Said store data hold flag to suppress setting to the off state when it is held, is characterized by maintaining the ON state of said store data hold flag (claim 6).

  Further, when the instruction processing unit issues the operation result as the store data from the operation register to the store data buffer, alignment information necessary for aligning the operation result together with the operation result, and the alignment Use / non-use information indicating whether or not information is used for the alignment is issued, and the alignment information used for the alignment is issued together with the store data based on the use / non-use information. It is preferable to select from the alignment information and the alignment information included in the store instruction.

  At this time, when the operation result is issued from the operation register to the store data buffer as the store data after the store instruction is issued to the store port by the instruction processing unit, the use is performed. / While setting the non-use information to non-use, the operation result is stored as the store data from the operation register before the store instruction is issued to the store port by the instruction processing unit. In the case of issuing to the buffer, it is preferable to set the use / non-use information to use.

  The store instruction is canceled after the store data is issued to the store data buffer and before the store instruction corresponding to the store data is issued to the store port. Preferably, the store data held in the store data buffer is deleted, and the store data holding flag corresponding to the store data is set to an off state (claim 9).

  Note that when a fetch instruction is issued from the instruction processing unit, a fetch bus for inputting data to be fetched by the fetch instruction from the predetermined storage area to the arithmetic unit or the arithmetic register, and the store data In the information processing apparatus further comprising a store fetch bypass for directly inputting the store data held in the buffer from the store data buffer to the fetch bus, the store data is held in the store data buffer. When the store instruction uses the store data, it is preferable that the store data is input from the store data buffer to the store fetch bypass.

  Thus, according to the present invention, when the operation register is determined, the operation result is issued from the operation register to the store data buffer as store data regardless of the issue status of the store instruction to the store port. If the store data is held in the store data buffer before being held in the store port, the store data holding flag is not set in the off state when the store instruction is held in the store port. Therefore, even when the store data is issued to the store data buffer before the store instruction is issued to the store port, the store instruction can be reliably executed. ).

  Therefore, unlike the conventional information processing apparatus, it is not necessary to wait for the issuance of store data from the operation register until it is confirmed that the store instruction is issued, even though the operation register is fixed. As soon as the calculation register is determined, store data (calculation result) is issued from the calculation register, and the calculation register is released as soon as the store data is issued from the calculation register as soon as possible. This makes it possible to improve the usage efficiency of the arithmetic registers.

  Even when the operation result issued as store data from the operation register is aligned, alignment information and use / non-use information are issued together with the store data, and alignment is reliably performed based on the use / non-use information ( Claims 2 and 7) When the store data is issued from the operation register to the store data buffer before the store instruction is issued to the store port, such use / nonuse information is set to use. Therefore, even if store data is issued to the store data buffer before issuing a store instruction to the store port, alignment can be executed reliably, and as a result, the store instruction must be executed reliably. (Claims 3 and 8).

  Further, in the case where the store instruction is canceled after the store data is issued to the store data buffer and before the store instruction corresponding to the store data is issued to the store port, the store data The store data held in the buffer is deleted, and the store data holding flag corresponding to the store data is set to the off state, so that the store data holding flag of the store port is turned on despite the cancellation. It is possible to prevent the store instruction held in the store port after the cancel execution from being mistakenly executed as the store data is already held and being executed erroneously. The store instruction can be executed reliably (claims 4 and 9).

  Further, even when the fetch instruction fetches store data used for the store instruction, the fetch instruction can be executed at an early stage using the store fetch bypass (claims 5 and 10).

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[1] Regarding the First Embodiment of the Present Invention [1-1] Regarding the Configuration of the Information Processing Apparatus First, the configuration of the information processing apparatus as the first embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration of an information processing apparatus as a first embodiment of the present invention. In FIG. 1, the same reference numerals as those described above indicate the same or almost the same parts.

  As shown in FIG. 1, the information processing apparatus 1 according to the first embodiment of the present invention includes an instruction processing unit 10, an arithmetic unit 20, an address register 21, an arithmetic register 22, and store ports 30-0 to 30-n (n Is an integer greater than or equal to 0 (here, an integer greater than or equal to 2), align unit 40, align information selection unit 41, store data buffers 50-0 to 50-n (n is an integer greater than or equal to 0, here an integer greater than or equal to 2), A cache memory (storage area) 60, a fetch bus 70, a store fetch bypass 71, a cancel unit 80, a reset unit 81, and a suppression unit 82 are provided.

  The instruction processing unit 10 decodes an instruction held in an instruction cache (not shown) and issues a processing instruction. The instruction processing unit 10 determines that the decoded instruction is a store instruction (store request). By decoding the instruction, the store data width (denoted as LENGTH in the figure), align instruction information indicating the right or left justification of the store data (denoted as ALIGN in the figure), and an arithmetic unit 20 to be described later The number (value) of the address register 21 used for the calculation of the store destination address (hereinafter referred to as the store address) and the number (value) of the arithmetic register 22 holding the store data described later are acquired.

The arithmetic unit 20 performs an operation in accordance with an arithmetic instruction issued as a processing instruction from the instruction processing unit 10 and should store by the store instruction based on a store instruction issued as a processing instruction from the instruction processing unit 10 The address calculation on a predetermined storage area (here, the cache memory 60) is executed using an address register 21 described later.
The address register 21 is used for the store destination address calculation by the arithmetic unit 20 and temporarily stores a store address as a result of the calculation.

The calculation register 22 is used for calculation by the calculation unit 20 and temporarily stores store data obtained as a result of the calculation. The arithmetic unit 20, the address register 21, and the arithmetic register 22 constitute an arithmetic unit.
The store ports 30-0 to 30-n store operation results (store data) issued as processing instructions from the instruction processing unit 10 and held in the operation register 22 in a predetermined storage area (here, the cache memory 60). For storing store instructions.

That is, the instruction processing unit 10 is configured to issue the decrypted store instruction to the store ports 30-0 to 30-n, and the address register 21 of the address register 21 used for address calculation by the arithmetic unit 20 based on the store instruction. When the number is determined, the store instruction is issued (see T3 in FIG. 3 described later).
The store ports 30-0 to 30-n have a VALID flag 30a, an ADRS (Address) flag 30b, a LENGTH flag 30c, a RSTDV (Received Store Date Valid) flag (store data retention flag) 30d, and a PSTV (Post Status Valid), respectively. ) Flag 30e and READY flag 30f.

The VALID flag 30a is information indicating whether or not the store ports 30-0 to 30-n have received store instructions issued from the instruction processing unit 10, and are set to an on state when receiving store instructions.
The ADRS (Address) flag 30b is information indicating whether or not the store ports 30-0 to 30-n have received a store address from the address register 21, and is set to an on state when the store address is received.

The LENGTH flag 30c is information indicating whether or not the store ports 30-0 to 30-n have received the store data width issued together with the store instruction from the instruction processing unit 10, and are set to the on state when the store data width is received. Is done.
The RSTDV flag 30d is information indicating whether store data buffers 50-0 to 50-n, which will be described later, corresponding to the store ports 30-0 to 30-n have received store data from the arithmetic register 22, respectively. When store data is held in the data buffers 50-0 to 50-n, the on state is set.

  In the PSTV flag 30e, the instruction processing unit 10 extracts the page attribute of the store target area (predetermined storage area; here, the cache memory 60), and determines whether or not the store address as the store target area can be written (stored). This is information indicating an exception determination result. If the exception determination result is no exception (storeable), the information is set to an on state. Note that the timing at which the instruction processing unit 10 performs exception determination will be described later with reference to FIG.

  The READY flag 30f determines that the instruction processing unit 10 can execute the store instruction held in the store ports 30-0 to 30-n, and executes the store instruction in order to execute the store instruction. Information indicating whether or not the store port 30-0 to 30-n has received the store permission to be notified to .about.30-n, and is set to the on state when the store permission is received from the instruction processing unit 10.

  The align unit 40 calculates the calculation result issued as the store data from the calculation register 22, stores the width of the store data issued together with the store instruction from the instruction processing unit 10 (denoted as LENGTH in the figure), and stores the data right-justified or left-justified The store data is aligned using the alignment information including the alignment instruction information (indicated as ALIGN in the figure) indicating the above, or the alignment information issued along with the store data issued from the operation register 22.

  The alignment information selection unit 41 uses the alignment information used for the alignment in the alignment unit 40 based on the use / non-use information (denoted as CODE-VALID in the figure) issued together with the alignment information issued along with the store data. The selection is made from the alignment information issued together with the store instruction from the instruction processing unit 10 and the alignment information issued accompanying the store data.

  That is, when issuing the store instruction to the store ports 30-0 to 30-n, the instruction processing unit 10 issues the alignment information together with the store instruction, and stores the store data from the operation register 22 in the store data buffer. When issuing to 50-0 to 50-n, the alignment information and use / non-use information are issued accompanying the store data.

The store data buffers 50-0 to 50-n are temporarily stored as store data issued from the arithmetic register 22 by the instruction processing unit 10 and aligned by the align unit 40.
The instruction processing unit 10 is configured to issue the operation result held in the operation register 22 based on the store instruction as store data to the store data buffers 50-0 to 50-n. Accordingly, when the operation register 22 holding the operation result to be stored by the store instruction is confirmed (that is, when the operation result is stored in the specified operation register 22), the store port 30-0 of the store instruction is stored. The calculation result is issued as store data from the calculation register 22 regardless of the issue status (whether or not issued) to 30-n (see T4 in FIG. 3 described later).

  Note that the store data buffers 50-0 to 50-n and the store ports 30-0 to 30-n have a one-to-one correspondence, and the instruction processing unit 10 determines which pair the store data buffer 50-0 to 50-n has when the store instruction is issued. Specifies whether to use the store port and store data buffer. Further, at least the store ports 30-0 to 30-n, the align unit 40, the store data buffers 50-0 to 50-n, and the cache memory 60 constitute a storage control device.

When the processing instruction decoded by the instruction processing unit 10 is a fetch instruction, the fetch bus 70 stores data to be fetched by the fetch instruction issued from the instruction processing unit 10 in a predetermined storage area (here, a cache memory). 60) to the arithmetic unit.
When the fetch instruction issued from the instruction processing unit 10 uses store data held in the store data buffers 50-0 to 50-n, the store fetch bypass 71 stores the store data in the store data buffer 50-0. -50-n is a bus for direct input to the fetch bus.

  Here, the instruction processing unit 10 is configured to execute fetch using the store fetch bypass 71 when the decoded instruction is a fetch instruction and satisfies a predetermined condition, for example, When the store data held in the store data buffers 50-0 to 50-n is used by a fetch instruction subsequent to the store instruction using the store data, the store data buffer 50 is executed before the store instruction is executed. The store data is input to the store fetch bypass 71 from −0 to 50-n.

The cancel unit 80 cancels (deletes) a store instruction held in the store ports 30-0 to 30-n when an event for canceling execution of the store instruction occurs.
FIGS. 2A and 2B are diagrams for explaining cancellation of execution of a store instruction by the cancel unit 80. FIG. 2A is a store port 30-0 to 30-n (here, n = 4). FIG. 2B is a diagram for explaining cancellation in the store data buffers 50-0 to 50-n (here, n = 4). In FIG. 2A, the ADRS flag 30b, LENGTH flag 30c, and PSTV flag 30e of the store ports 30-0 to 30-n are omitted here for simplification of the drawing.

  As shown in FIG. 2A, when an event for canceling execution of the store instruction occurs, the cancel unit 80 holds the store instruction in the store ports 30-0 to 30-4 [that is, VALID Flag 30a is in the ON state], the store data is held in the corresponding store data buffer [that is, the RSTDV flag 30d is in the ON state], and the READY flag 30f is in the ON state. A certain store port (here, store port 30-2) is not canceled, and a store port (here, store port 30-3) in which neither a store instruction nor store data is held is canceled. For other store ports (here, store ports 30-0, 30-1, 30-4) Cancels all, resets all the flags 30a to 30f of these store ports 30-0, 30-1 and 30-4 to the OFF state, and deletes the store instruction when the store instruction is held To do.

  On the other hand, as shown in FIG. 2B, in the store data buffers 50-0 to 50-n, the cancel unit 80 is connected to the store ports 30-0, 30-1, and 30-4 shown in FIG. Store data buffers 50-0, 50-1, and 50-4 corresponding to the store data buffers 50-0, 50-1, and 50-4 if the store data is held in the store data buffers 50-0, 50-1, and 50-4. Cancel (delete).

  Therefore, after the store data is issued to the store data buffers 50-0 to 50-n, a store instruction corresponding to the store data is issued to the store ports 30-0 to 30-n. When the store instruction is canceled before [that is, the state of the store port 30-4 and the store data buffer 50-4 in FIGS. 2A and 2B], the cancel unit 80 displays the store data buffer. The store data held in 50-4 is deleted, and the RSTDV flag 30f of the corresponding store port 30-4 is reset (set) to an off state.

The reset unit 81 sets the RSTDV flag 30d of the store port 30-0 to 30-n to an off state when the store instruction issued from the instruction processing unit 10 is held in the store ports 30-0 to 30-n. To do.
The suppression unit 82 stores the store data issued from the arithmetic register 22 by the instruction processing unit 10 before the store instruction issued from the instruction processing unit 10 is held in the store ports 30-0 to 30-n. When held in the data buffers 50-0 to 50-n, the reset unit 81 sets the RSTDV flag 30d to the off state when the store instruction is held in the store ports 30-0 to 30-n. It is suppressed and the ON state of the RSTDV flag 30d is maintained.

  As described above, in the information processing apparatus 1, the instruction processing unit 10 issues a store instruction to the store ports 30-0 to 30-n when the address register 21 used for address calculation by the computing unit 20 is determined. On the other hand, when the operation register 22 holding the operation result as the store data used in the store instruction is determined, regardless of the issue of the store instruction to the store ports 30-0 to 30-n (regardless of the issue status). The calculation result is issued as store data from the calculation register 22 to the store data buffers 50-0 to 50-n. That is, in the information processing apparatus 1, issuing store instructions to the store ports 30-0 to 30-n and issuing store data (calculation results) to the store data buffers 50-0 to 50-n are out-of-order. It is supposed to be executed in.

  As described above, in the information processing apparatus 1, the store data may be held in the store data buffers 50-0 to 50-n before the store instruction is held in the store ports 30-0 to 30-n. Therefore, in such a case, although the store data used for the store instruction is already held in the store data buffers 50-0 to 50-n, the store instruction is stored in the store ports 30-0 to 30-n. In order to prevent the reset unit 81 from resetting the RSTDV flag 30d to the OFF state at the time when it is held in the state, a suppression unit 82 is provided.

[1-2] Store Instruction Control Method (Operation of Information Processing Apparatus 1) Next, a store instruction control method (operation of the information processing apparatus 1) according to the first embodiment of the present invention will be described.
[1-2-1] Case in which issuance of store data is executed prior to issuance of store instruction FIG. 3 shows a store instruction control method according to the first embodiment of the present invention. It is a time chart which shows the procedure of the case where it performs before issue. In FIG. 3, T1 to T12 indicate time units, that is, control clock units in the information processing apparatus 1.

  As shown in FIG. 3, in the information processing apparatus 1, first, the instruction processing unit 10 decodes an instruction held in an instruction cache (not shown) (see T1 in FIG. 3). At this time, if the instruction decoded by the instruction processing unit 10 is a store instruction (store request), the instruction processing unit 10 stores the store data width (indicated as LENGTH in the drawing) together with the decoded store instruction, Align instruction information indicating left justification (indicated as ALIGN in the figure), the number (value) of the address register 21 used for calculating the storage destination address by the arithmetic unit 20, and the store data to be stored by the store instruction are held The number (value) of the arithmetic register 22 is acquired.

  Here, after the instruction is decoded, before the address register 21 used for calculation of the store address by the arithmetic unit 20 is determined (that is, the address register 21 is designated and the address register 21 can be used), When the operation register 22 is finalized (that is, the operation result used as store data is held in the designated operation register 22) (see T2 in FIG. 3), the instruction processing unit 10 stores the store instruction store port 30. Regardless of the issue status (whether or not issued) to −0 to 30-n (here, store port 30-0), the operation data from the operation register 22 is stored as the store data buffer 50-0 to 50-n. (Here, it is issued to the store data buffer 50-0) (see T3 in FIG. 3). Note that it takes time to determine the address register 21 because the address register 21 is occupied by a processing instruction issued before the store instruction.

  At this time, the instruction processing unit 10 causes the alignment information (store data width and alignment instruction information) to be issued along with the store data issued from the arithmetic register 22, and the align information is displayed by the align unit 40. Use / non-use information (CODE-VALID) indicating whether or not to use is issued along with the store data (see T3 in FIG. 3). Note that the instruction processing unit 10 issues the use / nonuse information set to use when the store data is issued from the arithmetic register 22 before the store instruction is issued. To. Note that the operation register 22 is released when the issuance of store data is completed, and can be used by other processes.

  Then, the alignment information selection unit 41 determines the alignment information used in the alignment unit 40 from the alignment information issued together with the store instruction and the alignment information issued accompanying the store data based on the use / non-use information. In this case, since the use / non-use information is set to use, the alignment information selection unit 41 selects the alignment information issued along with the store data, and uses the selected alignment information. The aligning unit 40 aligns the store data issued from the arithmetic register 22 (see T4 in FIG. 3).

Next, the aligned store data is held in the store data buffer 50-0, and the RSTDV flag of the store port 30-0 is set to the on state (see T5 in FIG. 3).
On the other hand, when the address register 21 used for calculation of the store address by the arithmetic unit 20 is determined (see T3 in FIG. 3), the arithmetic unit 20 executes calculation of the store address using the address register 21 (T4 in FIG. 3). reference). The store address obtained as a calculation result of the arithmetic unit 20 is temporarily held in the address register 21.

At this time, the instruction processing unit 10 issues the decoded store instruction to the store port 30-0 together with the store data width and the alignment instruction information (see T4 in FIG. 3).
Then, the store address calculated by the arithmetic unit 20 and held in the address register 21 is issued to the store port 30-0 (see T5 in FIG. 3). Here, the store address is input to a pipeline of a storage processing device having at least the store ports 30-0 to 30-n, and flows through the pipeline, thereby causing a translation lookaside buffer (TLB) (not shown). ) To the address (physical address; hereinafter, simply referred to as the store address if not distinguished from the store address held in the address register 21) on the storage area (here, the cache memory 60) that is the actual store destination The converted store address is issued to the store port 30-0.

Note that the address register 21 is released when the issue of the store address is completed, and can be used by other processes.
Next, when the store port 30-0 receives a store instruction, a store address (physical address), and a store data width, the VALID flag 30a, the ADRS flag 30b, and the LENGTH flag 30c are set to an on state (FIG. 3). (See T6).

At this time, since the store data is already stored in the corresponding store data buffer 50-0, the suppression unit 82 does not cause the reset unit 81 to set the RSTDV flag 30d to the off state, and the reset by the reset unit 81 is performed. And the RSTDV flag 30d is kept on (see T6 in FIG. 3).
When the store port 30-0 receives the store data width together with the store instruction, the instruction processing unit 10 determines whether the fetch instruction subsequent to the store instruction uses the store data used in the store instruction. (That is, whether or not the store target area of the store instruction is used) is determined based on the store data width (not shown). Here, if the subsequent fetch instruction uses the store data used by the store instruction, the instruction processing unit 10 suppresses the execution of the fetch instruction until the execution of the store instruction is completed, or When the store data used by the store instruction is held in the store data buffers 50-0 to 50-n, the store data is fetched from the store data buffers 50-0 to 50-n and fetched by bypassing writing to the cache memory 60. By inputting the data to the data bus 71, the fetch instruction is completed early.

  By the way, when the store address is held in the store port 30-0 (see T6 in FIG. 3), the instruction processing unit 10 extracts the page attribute of the store target area and determines an exception (see T7 in FIG. 3). . That is, the instruction processing unit 10 determines whether or not the store address as the storage target area can be written (stored), and if the store is possible, the instruction processing unit 10 notifies the store port 30-0 that there is no exception, while the store is not possible. If there is an exception, the store port 30-0 is notified that there is an exception, and the execution of the store instruction is cancelled.

Here, since the exception determination result is no exception, the PSTV flag 30e of the store port 30-0 is set to the on state.
Next, the instruction processing unit 10 stores the width of the store instruction, the store address, and the store data in the store port 30-0, the exception determination result of the store instruction is no exception, and the store data is stored in the store data buffer 50- 0 is held (that is, all of the VALID flag 30a, ADRS flag 30b, LENGTH flag 30c, PSTV flag 30e, and RSTDV flag 30d are on), and all instructions preceding the store instruction are completed. Then, it is determined that the store instruction is in an executable state, and store permission is notified to the store port 30-0 (see T10 in FIG. 3).

At this time, the READY flag 30f of the store port 30-0 is set to the on state.
When the READY flag 30f of the store port 30-0 is set to the ON state (see T10 in FIG. 3), the store instruction is executed (see T11 in FIG. 3), and the store held in the store port 30-0 is performed. Based on the address, the store data held in the store data buffer 50-0 is written at a predetermined address in the cache memory 60, and the processing of the store instruction is completed (see T12 in FIG. 3).

[1-2-2] Case in which issuance of store data is executed after issuance of store instruction FIG. 4 shows a store instruction control method according to the first embodiment of the present invention. It is a time chart which shows the procedure of a case where it is performed. In FIG. 4, T1 to T12 indicate time units, that is, control clock units in the information processing apparatus 1.

  As described above, in the information processing apparatus 1 (see FIG. 1) as the first embodiment of the present invention, the instruction processing unit 10 issues the store instruction to the store ports 30-0 to 30-n and calculates the store data. The issue order from the register 22 to the store data buffers 50-0 to 50-n can be executed out of order. Hereinafter, a case in which the issue of the store data by the instruction processing unit 10 is executed after the issue of the store instruction will be described with reference to FIG. 4. Here, the issue of the store data described above with reference to FIG. The description will focus on operations that are different from the case where the operations are executed prior to the issuance of an instruction, and the description of overlapping operations will be omitted.

  In the example shown in FIG. 4, after the instruction is decoded by the instruction processing unit 10 (see T1 in FIG. 4), the address register 21 is first determined (see T2 in FIG. 4). Thereafter, the arithmetic unit 20 performs address calculation using the determined address register 21, and the instruction processing unit 10 stores the store instruction for the store ports 30-0 to 30-n (here, the store port 30-0). Is issued, the operation register 22 is fixed (see T3 in FIG. 4).

  Then, the instruction processing unit 10 issues store data from the operation register 22 to the store data buffers 50-0 to 50-n (here, the store data buffer 50-0), and the alignment information and use / unuse. Information (CODE-VALID) is issued. Here, since the issue of the store instruction is executed before the issue of the store data is executed, the instruction processing unit 10 does not use / not use information. It is set to use and issued (see T4 in FIG. 4).

Therefore, the alignment information selection unit 41 selects the alignment information issued accompanying the store instruction based on the use / non-use information, and the align unit uses the alignment information attached to the selected store instruction to store the information. The data is aligned (see T5 in FIG. 4).
On the other hand, when the store instruction is held in the store port 30-0, the store instruction is held in the store port 30-0 before the store data is held in the store data buffer 50-0. The suppressing unit 82 does not prevent the resetting unit 81 from resetting the RSTDV flag 30d, and the resetting unit 81 temporarily sets (resets) the RSTDV flag 30d (see T5 in FIG. 4).

After that, when the store data is held in the store data buffer 50-0, the RSTDV flag 30d is set to the on state (see T6 in FIG. 4).
After the exception determination (see T6 in FIG. 4), the operations (see T7 to T12 in FIG. 4) from when the store instruction is executed until the store data is stored in the cache memory 60 are described with reference to FIG. This is the same as described above.

[1-3] Effects of the information processing apparatus 1 and the store instruction control method as the first embodiment of the present invention As described above, according to the information processing apparatus 1 and the store instruction control method of the first embodiment of the present invention. For example, when the instruction processing unit 10 determines the operation register 22 regardless of the issue status of the store instruction to the store ports 30-0 to 30-n, the operation data from the operation register 22 is stored as the store data buffer 50-0. To 50-n, and the alignment information and the use / non-use information are issued along with the store data so that the align unit 40 can perform the alignment, and the store instruction is stored in the store port 30- If store data is held in the store data buffers 50-0 to 50-n before being held in 0 to 30-n, suppression is performed. The stopping unit 82 prevents the reset unit 81 from setting the RSTDV flag to the OFF state when the store instruction is held in the store ports 30-0 to 30-n, and maintains the RSTDV flag in the ON state. Therefore, even when the store data is issued to the store data buffers 50-0 to 50-n before the store instruction is issued to the store ports 30-0 to 30-n, the store instruction is surely executed. can do.

  Therefore, as in the conventional information processing apparatus 100 shown in FIG. 7, the issue of the store instruction from the operation register 22 is confirmed even though the operation register 22 is fixed (see FIG. 8 (see T7 in FIG. 8), and store data (calculation result) can be issued from the operation register 22 as soon as the operation register 22 is determined (T3 in FIG. 3 and T4 in FIG. 4). The calculation register 22 is released earlier than the conventional information processing apparatus 100 (by three control clock units in the example shown in FIG. 3 and two control clock units in the example shown in FIG. 4), and the calculation register 22 is released. 22 can be assigned to other processes. That is, the usage efficiency of the arithmetic register 22 can be improved.

  3 and 4, the timing at which the instruction processing unit 10 notifies the store permission is the same as the timing in the conventional information processing apparatus 100 shown in FIG. 8 (T10 in FIGS. 3 and 4 and FIG. 8). However, according to the information processing apparatus 1 and the store instruction control method as the first embodiment of the present invention, the timing of the instruction preceding the store instruction is completed. Can advance the timing at which the store permission can be notified (T8 timing in the example shown in FIG. 3 and T9 timing in the example shown in FIG. 4).

  That is, in the information processing apparatus 1 and the store instruction control method according to the first embodiment of the present invention, the issuance order of the store instruction and the store data can be executed out-of-order. The earlier the timing at which the operation register 22 is determined, the earlier the execution timing of the store instruction can be advanced. Therefore, the processing performance of the information processing apparatus 1 can be improved depending on the store permission issuance timing (store instruction execution timing).

  Note that the execution timing of the store instruction is the earliest after the instruction processing unit 10 decodes the instruction (that is, at the timing of T2 in FIGS. 3 and 4), both the address register 21 and the operation register 22 are determined. In this case, the execution timing of the store instruction can be advanced to the timing of T9 in FIGS. 3 and 4, and the processing performance of the information processing apparatus 1 can be improved.

  Further, according to the information processing apparatus 1 and the store instruction control method as the first embodiment of the present invention, as described above, the instruction processing unit 10 issues the store instruction to the store ports 30-0 to 30-n. Regardless of the situation, when the operation register 22 is determined, the operation register 22 issues the operation result as store data to the store data buffers 50-0 to 50-n, and the store instruction is sent to the store ports 30-0 to 30-n. When the store data is held in the store data buffers 50-0 to 50-n before being held, the suppression unit 82 is when the store instruction is held in the store ports 30-0 to 30-n. In order to prevent the reset unit 81 from setting the RSTDV flag to the off state and to keep the RSTDV flag in the on state, a fetch subsequent to the store instruction is performed. Decrees, even when fetching store data to be used for the store instruction, the instruction processing unit 10 can be surely performed by using the store fetch bypass 71 such subsequent fetch instruction.

  Furthermore, in the information processing apparatus 1 and the store instruction control method according to the first embodiment of the present invention, after store data is issued to the store data buffers 50-0 to 50-n, the store data is stored in the store data. When the event that the store instruction is canceled occurs before the corresponding store instruction is issued to the store ports 30-0 to 30-n [the store port 30-4 in FIG. 2A and FIG. b), the cancel unit 80 deletes the store data held in the store data buffers 50-0 to 50-n (here, the store data buffer 50-4), and The RSTDV flag 30d of the corresponding store port 30-0 to 30-n (here, store port 30-4) is set to an off state.

  Thereby, even if a store instruction is held before the store data is held in the store data buffer 50-4 for the store port 30-4 after cancellation by the cancel unit 80, the corresponding store data buffer 50 is stored. -4 RSTDV flag 30d is set to the OFF state, so that the store instruction after the cancel execution by the cancel unit 80 can be reliably executed. That is, the RSTDV flag 30d of the store port 30-4 remains in the ON state, it is mistaken that the store data is held in the store data buffer 50-4, and the store instruction after the cancel execution by the cancel unit 80 is incorrect. Can be prevented from being executed.

[2] Second Embodiment of the Present Invention Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram showing a configuration of an information processing apparatus 1 'as a second embodiment of the present invention. . In FIG. 5, the same reference numerals as those described above indicate the same or almost the same parts.
As shown in FIG. 5, in the information processing apparatus 1 ′ as the second embodiment of the present invention, the issue order of the store instruction and the issue of the store data is executed according to the in-order execution in which the issue of the store instruction always precedes. (Switching unit 83 is provided for switching between (first mode) and out-of-order execution (second mode) in which store data is issued regardless of the issue status of store instructions). The configuration is the same as the information processing apparatus 1 of the first embodiment shown in FIG. Therefore, the detailed description of the parts common to the information processing apparatus 1 of the first embodiment is omitted here.

  The information processing apparatus 1 ′ according to the second embodiment of the present invention includes a switching unit 83, and the switching unit 83 stores store instructions 30-0 to 30-n for store instructions by the instruction processing unit 10. In-order processing (first mode) in which issuance to the store data is always preceded by issuance to the store data buffers 50-0 to 50-n from the operation register 22 and an operation in which the operation result is held When the register 22 is determined, an out-of-order process for issuing an operation result from the operation register 22 to the store data buffers 50-0 to 50-n as store data regardless of the issue of the store instruction (regardless of the issue state). (Second mode) is selectively switched. The switching unit 83 is configured to be able to switch between in-order processing and out-of-order processing by a switching register (Operation Status Register; not shown).

  When in-order processing is executed by switching of the switching unit 83, that is, when in-order processing is selected by the switching unit 83, the instruction processing unit 10 selects the store instructions 30-0 to 30-n for the store instruction. Until issuance is completed, issuance of store data from the arithmetic register 22 is interlocked, and when a store instruction is held in the store ports 30-0 to 30-n, the reset unit 81 turns off the RSTDV flag 30d. Set (reset) to.

At this time, the instruction processing unit 10 issues the alignment information and the use / non-use information together with the issue of the store data, but sets the use / non-use information to non-use.
When executing in-order processing, the instruction processing unit 10 may be configured not to issue the alignment information and the use / non-use information together with the issue of the store data.
On the other hand, when the out-of-order processing is executed by switching the switching unit 83, that is, when the out-of-order processing is selected by the switching unit 83, the instruction processing unit 10 issues store data from the arithmetic register 22. When the operation register 22 is fixed regardless of the issuance status of store instructions to the store ports 30-0 to 30-n, store data is stored from the operation register 22 into the store data buffer 50-0. Issue to 50-n.

At this time, the instruction processing unit 10 issues alignment information and use / non-use information accompanying the store data, and sets the use / non-use information to use.
In addition, if the instruction processing unit 10 holds the store data in the store data buffers 50-0 to 50-n before the store instruction is held in the store ports 30-0 to 30-n, it is suppressed. When the store instruction is held in the store ports 30-0 to 30-n, the unit 82 prevents the reset unit 81 from setting the RSTDV flag to the off state, and maintains the RSTDV flag in the on state.

  As described above, according to the information processing apparatus 1 ′ as the second embodiment of the present invention, the same effect as that of the first embodiment described above can be obtained, and the switching unit 83 stores the instruction by the instruction processing unit 10. Issuance of instructions to the store ports 30-0 to 30-n and issuance of store data from the operation register 22 to the store data buffers 50-0 to 50-n are performed in in-order processing and out-of-order processing. By selectively switching, it is possible to test the performance improvement during out-of-order processing compared to in-order processing. That is, by switching between in-order processing and out-of-order processing by the switching unit 83, as soon as the arithmetic register 22 is determined, store data is issued, the arithmetic register 22 is released, and assigned to other processing. Thus, improvement in the usage efficiency of the arithmetic register 22 can be confirmed.

[3] Others The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above-described embodiment, when the operation result is issued from the operation register 22 to the store data buffers 50-0 to 50-n as the store data, the instruction processing unit 10 uses the alignment information and use along with the store data. The instruction processing unit 10 issues a store instruction to the store ports 30-0 to 30-n, and then stores the store data from the arithmetic register 22 to the store data buffer 50-0. When issuing to 50-n, the use / non-use information is set to non-use, while store data is issued prior to issuing a store instruction to store ports 30-0 to 30-n. When issuing from the arithmetic register 22 to the store data buffers 50-0 to 50-n, the use / nonuse information is set to use. However, the present invention is not limited to this. After the instruction processing unit 10 issues a store instruction to the store ports 30-0 to 30-n, the store data is stored from the arithmetic register 22. When issuing to the data buffers 50-0 to 50-n, the alignment information and the use / non-use information are not issued together with the store data, while the store instructions are stored in the store ports 30-0 to 30-n. When the store data is issued from the operation register 22 to the store data buffers 50-0 to 50-n prior to being issued to the store data, only the alignment information may be issued together with the store data. . In this case, the alignment unit 40 is configured so that, when the instruction processing unit 10 issues the alignment information together with the store data, the alignment information is used so that the alignment information accompanying the store instruction is not used. The alignment information selection unit 41 can be omitted, and the alignment by the alignment unit 40 can be reliably executed with a simpler configuration, and the store instruction can be reliably executed.

  In the above-described embodiment, the align unit 40 is configured to be interposed between the arithmetic register 22 and the store data buffers 50-0 to 50-n. However, the present invention is not limited to this. Absent. 6 is a block diagram showing the configuration of an information processing apparatus 1 ″ as a modification of the present invention. For example, as shown in FIG. 6, the align unit 40 is connected to store data buffers 50-0 to 50-n. It may be provided in a subsequent stage (that is, between the store data buffers 50-0 to 50-n and the cache memory 60. In this case, the alignment information selection unit 41 can be omitted, and further, instruction processing is performed. When the unit 10 issues the store data from the arithmetic register 22, the store data held in the store data buffers 50-0 to 50-n is not issued without issuing the alignment information and the use / non-use information together with the store data. When storing in the cache memory 60, the aligning unit 40 aligns the store data using the alignment information issued accompanying the store instruction. It may be configured to.

  Furthermore, in the above-described embodiment, the store data storage (write) destination by execution of the store instruction is the cache memory 60. However, the present invention is not limited to this, and the store data storage destination is the information processing apparatus. An external storage device connected to 1 (1 ') may be used.

Further, the functions as the instruction processing unit 10, the alignment unit 40, the alignment information selection unit 41, the cancellation unit 80, the reset unit 81, the suppression unit 82, and the switching unit 83 described above are computers (CPU, information processing apparatus, various terminals). Is implemented by executing a predetermined application program (store instruction control program).
The program is provided in a form recorded on a computer-readable recording medium such as a flexible disk, CD-ROM, CD-R, CD-RW, or DVD. In this case, the computer reads the store instruction control program from the recording medium, transfers it to the internal storage device or the external storage device, and uses it. Further, the program may be recorded in a storage device (recording medium) such as a magnetic disk, an optical disk, or a magneto-optical disk, and provided from the storage device to a computer via a communication line.

  Here, the computer is a concept including hardware and an OS (operating system) and means hardware that operates under the control of the OS. Further, when the OS is unnecessary and the hardware is operated by the application program alone, the hardware itself corresponds to the computer. The hardware includes at least a microprocessor such as a CPU and means for reading a computer program recorded on a recording medium. The application program as the store instruction control program is stored in the computer as described above as the instruction processing unit 10, the align unit 40, the align information selection unit 41, the cancel unit 80, the reset unit 81, the suppression unit 82, and the switching unit 83. The program code that realizes the function is included. Also, some of the functions may be realized by the OS instead of the application program.

  In addition to the above-mentioned flexible disk, CD-ROM, CD-R, CD-RW, DVD, magnetic disk, optical disk, magneto-optical disk, IC card, ROM cartridge, magnetic tape as recording media according to the present embodiment , Various types of computer-readable media such as punch cards, computer internal storage devices (memory such as RAM and ROM), external storage devices, and printed materials on which codes such as bar codes are printed. .

[4] Appendix (Appendix 1)
An instruction processing unit for decoding instructions and issuing processing instructions;
An arithmetic unit that performs an operation in accordance with an operation instruction issued as the processing instruction from the instruction processing unit;
A calculation register for holding a calculation result by the calculator;
A store port that stores a store instruction that is issued as the processing instruction from the instruction processing unit and stores the operation result held in the operation register in a predetermined storage area;
A store data buffer for temporarily holding the calculation result issued as store data from the calculation register;
The instruction processing unit is configured to issue the operation result as the store data from the operation register to the store data buffer when the operation register holding the operation result is determined according to the store instruction. And
The store port is configured to hold a store data holding flag that is set to an on state when the store data corresponding to the store instruction is held in the store data buffer;
A reset unit that sets the store data retention flag to an off state when the store instruction is retained in the store port;
If the store data is held in the store data buffer prior to the store instruction being held in the store port, the reset unit may store the store instruction when the store instruction is held in the store port. An information processing apparatus, further comprising a suppression unit that suppresses setting a data retention flag to an off state and maintains the on state of the store data retention flag.

(Appendix 2)
An instruction processing unit for decoding instructions and issuing processing instructions;
An arithmetic unit that performs an operation in accordance with an operation instruction issued as the processing instruction from the instruction processing unit;
A calculation register for holding a calculation result by the calculator;
A store port that stores a store instruction that is issued as the processing instruction from the instruction processing unit and stores the operation result held in the operation register in a predetermined storage area;
A store data buffer for temporarily holding the calculation result issued as store data from the calculation register;
A first mode in which issuance of the store instruction to the store port is always preceded by issuance of the operation result to the store data buffer; and when the operation register holding the operation result is determined, the store instruction A switching unit that selectively switches between the second mode for causing the calculation result to be issued from the calculation register to the store data buffer as the store data regardless of the issuance of
The store port is configured to hold a store data holding flag that is set to an on state when the store data corresponding to the store instruction is held in the store data buffer;
A reset unit that sets the store data retention flag to an off state when the store instruction is retained in the store port;
By selecting the second mode by the switching unit, when the store data is held in the store data buffer before the store instruction is held in the store port, the store instruction is And further comprising a deterring unit that inhibits the reset unit from setting the store data retention flag to an off state when the store data is retained in the store port, and maintains the on state of the store data retention flag. An information processing apparatus characterized by comprising:

(Appendix 3)
When the instruction processing unit issues the operation result as the store data from the operation register to the store data buffer before issuing the store instruction to the store port, the operation processing unit It is configured to issue the alignment information necessary for aligning the operation result together with the result,
An alignment unit for aligning the operation result issued from the operation register based on the alignment information issued from the instruction processing unit or the alignment information included in the store instruction is further provided. The information processing apparatus according to Supplementary Note 1 or 2.

(Appendix 4)
An align unit for aligning the operation results issued as the store data from the operation register;
When the instruction processing unit issues the operation result as the store data from the operation register to the store data buffer, the alignment unit uses the alignment information necessary for alignment and the alignment information together with the operation result. Configured to issue usage / non-use information indicating whether or not
An alignment information selection unit that selects the alignment information used in the alignment unit from the alignment information issued together with the store data and the alignment information included in the store instruction based on the use / non-use information. The information processing apparatus according to appendix 1 or 2, further comprising:

(Appendix 5)
The instruction processing unit
When issuing the store instruction to the store port and then issuing the calculation result as the store data from the calculation register to the store data buffer, the use / nonuse information is set to non-use. While
Before issuing the store instruction to the store port, the operation result is used as the store data from the operation register to the store data buffer. The information processing apparatus according to appendix 4, wherein the information processing apparatus is set to

(Appendix 6)
A cancel unit for canceling execution of the store instruction;
The cancel unit executes the store instruction after the store data is issued to the store data buffer and before the store instruction corresponding to the store data is issued to the store port. When canceling, the store data held in the store data buffer is deleted, and the store data holding flag corresponding to the store data is set to an off state. 6. The information processing apparatus according to any one of 5 above.

(Appendix 7)
A fetch bus for inputting data to be fetched by the fetch instruction from the predetermined storage area to the arithmetic unit or the arithmetic register when a fetch instruction is issued from the instruction processing unit;
A store fetch bypass for directly sending the store data held in the store data buffer from the store data buffer to the fetch bus;
Supplementary notes 1 to 6, wherein when the fetch instruction uses the store data held in the store data buffer, the store data is input from the store data buffer to the store fetch bypass. The information processing apparatus according to any one of the above.

(Appendix 8)
The computing unit calculates a store address on the predetermined storage area for storing the computation result based on the store instruction issued by the instruction processing unit, and
Further comprising an address register used for calculation of the store address by the computing unit,
8. The information processing apparatus according to claim 1, wherein the instruction processing unit issues the store instruction to the store port when the address register is determined.

(Appendix 9)
An instruction processing unit that decodes an instruction and issues a processing instruction, an arithmetic unit that executes an operation according to an arithmetic instruction issued as the processing instruction from the instruction processing unit, and an operation that holds an operation result by the arithmetic unit A register, a store port that is issued as the processing instruction from the instruction processing unit and stores the operation result stored in the operation register in a predetermined storage area, and store data from the operation register A store data buffer that temporarily holds the operation result issued as the store port, and the store port is set to an ON state when the store data corresponding to the store instruction is held in the store data buffer. Issued from the instruction processing unit in an information processing apparatus configured to hold a store data holding flag A store instruction control method for controlling the execution of the serial store instruction,
When the operation register holding the operation result is determined by the instruction processing unit, the operation result is issued from the operation register to the store data buffer as the store data.
If the store instruction is held in the store port before the store data is held in the store data buffer, the store data holding flag is set when the store instruction is held in the store port. While setting to off
If the store data is held in the store data buffer before the store instruction is held in the store port, the store data holding flag is set when the store instruction is held in the store port. The store instruction control method is characterized in that the store data holding flag is kept in an on state by suppressing the setting of the store state to the off state.

(Appendix 10)
An instruction processing unit that decodes an instruction and issues a processing instruction, an arithmetic unit that executes an operation according to an arithmetic instruction issued as the processing instruction from the instruction processing unit, and an operation that holds an operation result by the arithmetic unit A register, a store port that is issued as the processing instruction from the instruction processing unit and stores the operation result stored in the operation register in a predetermined storage area, and store data from the operation register A store data buffer that temporarily holds the operation result issued as a first, and a first mode that always issues the store instruction to the store port prior to issuing the operation result to the store data buffer When the operation register holding the operation result is confirmed, the operation result is stored in the store register regardless of the issue of the store instruction. A switching unit that selectively switches the second register to be issued from the arithmetic register to the store data buffer as a data, and the store port stores the store data corresponding to the store instruction in the store data buffer. In an information processing apparatus configured to hold a store data holding flag that is set to an on state when the data is held, a store instruction control method that controls execution of the store instruction issued from the instruction processing unit There,
When the store instruction is held in the store port before the store data is held in the store data buffer by the instruction processing unit, the time when the store instruction is held in the store port To set the store data retention flag to the off state,
When the store data is held in the store data buffer before the store instruction is held in the store port by selecting the second mode by the switching unit, the store instruction The store instruction control method is characterized in that the store data retention flag is inhibited from being set to an off state at the time when the store data retention flag is held in the store port, and the store data retention flag is kept on. 11)
When the operation result is issued from the operation register to the store data buffer as the store data before the instruction processing unit issues the store instruction to the store port, the operation processing unit 11. The store instruction control method according to appendix 9 or 10, wherein alignment information necessary for aligning the operation result is issued together with the result.

(Appendix 12)
When the instruction processing unit causes the operation result to be issued from the operation register to the store data buffer as the store data, the operation information together with the alignment information necessary for aligning the operation result, and the alignment information Use / non-use information indicating whether or not to use at the time of alignment,
The alignment information used for the alignment is selected from the alignment information issued together with the store data and the alignment information included in the store instruction based on the use / non-use information. The store instruction control method according to appendix 9 or 10.

(Appendix 13)
When the operation result is issued from the operation register to the store data buffer as the store data after the store instruction is issued to the store port by the instruction processing unit, the use / unuse While setting the information to non-use,
When the operation result is issued from the operation register to the store data buffer as the store data before the store instruction is issued to the store port by the instruction processing unit, the use The store instruction control method according to appendix 12, wherein non-use information is set to use.

(Appendix 14)
When canceling the store instruction after the store data is issued to the store data buffer and before the store instruction corresponding to the store data is issued to the store port Any one of appendices 9 to 13, wherein the store data held in the store data buffer is deleted and the store data holding flag corresponding to the store data is set to an off state. The store instruction control method described.

(Appendix 15)
When a fetch instruction is issued from the instruction processing unit, a fetch bus for inputting data to be fetched by the fetch instruction from the predetermined storage area to the arithmetic unit or the arithmetic register, and the store data buffer The store stored in the store data buffer in the information processing apparatus further comprising a store fetch bypass for directly inputting the stored store data from the store data buffer to the fetch bus The store instruction control method according to any one of appendices 9 to 14, wherein when the data is used by the fetch instruction, the store data is input from the store data buffer to the store fetch bypass. .

(Appendix 16)
Note that the instruction processing unit issues the store instruction to the store port when an address register used when calculating a store address in the predetermined storage area for storing the operation result is determined. The store instruction control method according to any one of 9 to 15.

(Appendix 17)
An arithmetic unit that executes an operation in accordance with an arithmetic instruction issued as a processing instruction, an arithmetic register that holds an arithmetic result by the arithmetic unit, and the arithmetic result that is issued as the processing instruction and held in the arithmetic register A store port for storing a store instruction for storing in a predetermined storage area; and a store data buffer for temporarily storing the operation result issued as store data from the operation register. Controlling execution of the store instruction in an information processing apparatus configured to hold a store data holding flag that is set to an on state when the store data corresponding to the store instruction is held in a store data buffer A store instruction control program for causing a computer to realize a function,
Decoding the instruction and issuing the processing instruction, and when the operation register holding the operation result is determined according to the store instruction issued as the processing instruction, the operation result is stored as the store data in the operation register. An instruction processing unit for issuing to the store data buffer from
A reset unit that sets the store data retention flag to an off state when the store instruction is retained in the store port; and
If the store data is held in the store data buffer prior to the store instruction being held in the store port, the reset unit may store the store instruction when the store instruction is held in the store port. A store instruction control program that causes the computer to function as a suppression unit that suppresses setting a data retention flag to an off state and maintains the on state of the store data retention flag.

(Appendix 18)
An arithmetic unit that executes an operation in accordance with an arithmetic instruction issued as a processing instruction, an arithmetic register that holds an arithmetic result by the arithmetic unit, and the arithmetic result that is issued as the processing instruction and held in the arithmetic register A store port for storing a store instruction for storing in a predetermined storage area; and a store data buffer for temporarily storing the operation result issued as store data from the operation register. Controlling execution of the store instruction in an information processing apparatus configured to hold a store data holding flag that is set to an on state when the store data corresponding to the store instruction is held in a store data buffer Computer storing a store instruction control program for causing a computer to realize the function A recording medium that can be taken,
The store instruction control program is
Decoding the instruction and issuing the processing instruction, and when the operation register holding the operation result is determined according to the store instruction issued as the processing instruction, the operation result is stored as the store data in the operation register. An instruction processing unit for issuing to the store data buffer from
A reset unit that sets the store data retention flag to an off state when the store instruction is retained in the store port; and
If the store data is held in the store data buffer prior to the store instruction being held in the store port, the reset unit may store the store instruction when the store instruction is held in the store port. A computer-readable storage medium storing a store instruction control program, wherein the computer is caused to function as a suppression unit that suppresses setting a data retention flag to an off state and maintains the on state of the store data retention flag Possible recording media.

(Appendix 19)
An arithmetic unit that executes an operation in accordance with an arithmetic instruction issued as a processing instruction, an arithmetic register that holds an arithmetic result by the arithmetic unit, and the arithmetic result that is issued as the processing instruction and held in the arithmetic register A store port for storing a store instruction for storing in a predetermined storage area; and a store data buffer for temporarily storing the operation result issued as store data from the operation register. Controlling execution of the store instruction in an information processing apparatus configured to hold a store data holding flag that is set to an on state when the store data corresponding to the store instruction is held in a store data buffer A store instruction control program for causing a computer to realize a function,
An instruction processing unit for decoding the instruction and issuing the processing instruction;
A first mode in which issuance of the store instruction to the store port is always preceded by issuance of the operation result to the store data buffer; and when the operation register holding the operation result is determined, the store instruction A switching section that selectively switches the second result to be issued from the operation register to the store data buffer as the store data regardless of the issuance of
A reset unit that sets the store data retention flag to an off state when the store instruction is retained in the store port; and
By selecting the second mode by the switching unit, when the store data is held in the store data buffer before the store instruction is held in the store port, the store instruction is Preventing the reset unit from setting the store data retention flag to an off state at the time when the store data is retained in the store port, and causing the computer to function as a deterrence unit that maintains the on state of the store data retention flag A store instruction control program.

(Appendix 20)
An arithmetic unit that executes an operation in accordance with an arithmetic instruction issued as a processing instruction, an arithmetic register that holds an arithmetic result by the arithmetic unit, and the arithmetic result that is issued as the processing instruction and held in the arithmetic register A store port for storing a store instruction for storing in a predetermined storage area; and a store data buffer for temporarily storing the operation result issued as store data from the operation register. Controlling execution of the store instruction in an information processing apparatus configured to hold a store data holding flag that is set to an on state when the store data corresponding to the store instruction is held in a store data buffer Computer storing a store instruction control program for causing a computer to realize the function A recording medium that can be taken,
The store instruction control program is
An instruction processing unit for decoding the instruction and issuing the processing instruction;
A first mode in which issuance of the store instruction to the store port is always preceded by issuance of the operation result to the store data buffer; and when the operation register holding the operation result is determined, the store instruction A switching section that selectively switches the second result to be issued from the operation register to the store data buffer as the store data regardless of the issuance of
A reset unit that sets the store data retention flag to an off state when the store instruction is retained in the store port; and
By selecting the second mode by the switching unit, when the store data is held in the store data buffer before the store instruction is held in the store port, the store instruction is Preventing the reset unit from setting the store data retention flag to an off state at the time when the store data is retained in the store port, and causing the computer to function as a deterrence unit that maintains the on state of the store data retention flag A computer-readable recording medium having a store instruction control program recorded thereon.

It is a block diagram which shows the structure of the information processing apparatus as 1st Embodiment of this invention. 2A and 2B are diagrams for explaining cancellation by a cancellation unit of the information processing apparatus according to the first embodiment of the present invention, in which FIG. 1A is a diagram for explaining cancellation in a store port, and FIG. 2B is cancellation in a store data buffer; It is a figure for demonstrating. It is a time chart for demonstrating the procedure of the store instruction control method as 1st Embodiment of this invention. It is a time chart for demonstrating the procedure of the store instruction control method as 1st Embodiment of this invention. It is a block diagram which shows the structure of the information processing apparatus as 2nd Embodiment of this invention. It is a block diagram which shows the structure of the information processing apparatus as a modification of this invention. It is a block diagram which shows the structure of the conventional information processing apparatus. It is a time chart for demonstrating the procedure of the conventional store instruction control method.

Explanation of symbols

1, 1 ′, 1 ″, 100 Information processing apparatus 10 Instruction processing unit 20 Operation unit 21 Address register 22 Operation register 30-0 to 30-n Store port 30a VALID flag 30b ADRS flag 30c LENGTH flag 30d RSTDV flag (store data hold flag)
30e PSTV flag 30f READY flag 40 align unit 41 align information selection unit 50-0 to 50-n store data buffer 60 cache memory (storage area)
70 fetch bus 71 store fetch bypass 80 cancel unit 81 reset unit 82 suppression unit 83 switching unit

Claims (10)

An instruction processing unit for decoding instructions and issuing processing instructions;
An arithmetic unit that performs an operation in accordance with an operation instruction issued as the processing instruction from the instruction processing unit;
A calculation register for holding a calculation result by the calculator;
A store port that stores a store instruction that is issued as the processing instruction from the instruction processing unit and stores the operation result held in the operation register in a predetermined storage area;
A store data buffer for temporarily holding the calculation result issued as store data from the calculation register;
The instruction processing unit is configured to issue the operation result as the store data from the operation register to the store data buffer when the operation register holding the operation result is determined according to the store instruction. And
The store port is configured to hold a store data holding flag that is set to an on state when the store data corresponding to the store instruction is held in the store data buffer;
A reset unit that sets the store data retention flag to an off state when the store instruction is retained in the store port;
If the store data is held in the store data buffer prior to the store instruction being held in the store port, the reset unit may store the store instruction when the store instruction is held in the store port. An information processing apparatus, further comprising a suppression unit that suppresses setting a data retention flag to an off state and maintains the on state of the store data retention flag. An align unit for aligning the operation results issued as the store data from the operation register;
When the instruction processing unit issues the operation result as the store data from the operation register to the store data buffer, the alignment unit uses the alignment information necessary for alignment and the alignment information together with the operation result. Configured to issue usage / non-use information indicating whether or not
An alignment information selection unit that selects the alignment information used in the alignment unit from the alignment information issued together with the store data and the alignment information included in the store instruction based on the use / non-use information. The information processing apparatus according to claim 1, further comprising: The instruction processing unit
When issuing the store instruction to the store port and then issuing the calculation result as the store data from the calculation register to the store data buffer, the use / nonuse information is set to non-use. While
Before issuing the store instruction to the store port, the operation result is used as the store data from the operation register to the store data buffer. The information processing apparatus according to claim 2, wherein A cancel unit for canceling execution of the store instruction;
The cancel unit executes the store instruction after the store data is issued to the store data buffer and before the store instruction corresponding to the store data is issued to the store port. 2. When canceling, the store data held in the store data buffer is deleted, and the store data holding flag corresponding to the store data is set to an off state. The information processing apparatus according to any one of? A fetch bus for inputting data to be fetched by the fetch instruction from the predetermined storage area to the arithmetic unit or the arithmetic register when a fetch instruction is issued from the instruction processing unit;
A store fetch bypass for directly sending the store data held in the store data buffer from the store data buffer to the fetch bus;
The store data is input from the store data buffer to the store fetch bypass when the fetch instruction uses the store data held in the store data buffer. 5. The information processing apparatus according to any one of 4. An instruction processing unit that decodes an instruction and issues a processing instruction, an arithmetic unit that executes an operation according to an arithmetic instruction issued as the processing instruction from the instruction processing unit, and an operation that holds an operation result by the arithmetic unit A register, a store port that is issued as the processing instruction from the instruction processing unit and stores the operation result stored in the operation register in a predetermined storage area, and store data from the operation register A store data buffer that temporarily holds the operation result issued as the store port, and the store port is set to an ON state when the store data corresponding to the store instruction is held in the store data buffer. Issued from the instruction processing unit in an information processing apparatus configured to hold a store data holding flag A store instruction control method for controlling the execution of the serial store instruction,
When the operation register holding the operation result is determined by the instruction processing unit, the operation result is issued from the operation register to the store data buffer as the store data.
If the store instruction is held in the store port before the store data is held in the store data buffer, the store data holding flag is set when the store instruction is held in the store port. While setting to off
If the store data is held in the store data buffer before the store instruction is held in the store port, the store data holding flag is set when the store instruction is held in the store port. The store instruction control method is characterized in that the store data holding flag is kept in an on state by suppressing the setting of the store state to the off state. When the instruction processing unit causes the operation result to be issued from the operation register to the store data buffer as the store data, the operation information together with the alignment information necessary for aligning the operation result, and the alignment information Use / non-use information indicating whether or not to use at the time of alignment,
The alignment information used for the alignment is selected from the alignment information issued together with the store data and the alignment information included in the store instruction based on the use / non-use information. The store instruction control method according to claim 6. When the operation result is issued from the operation register to the store data buffer as the store data after the store instruction is issued to the store port by the instruction processing unit, the use / unuse While setting the information to non-use,
When the operation result is issued from the operation register to the store data buffer as the store data before the store instruction is issued to the store port by the instruction processing unit, the use 8. The store instruction control method according to claim 7, wherein the non-use information is set to use.   When canceling the store instruction after the store data is issued to the store data buffer and before the store instruction corresponding to the store data is issued to the store port The store data held in the store data buffer is deleted, and the store data holding flag corresponding to the store data is set to an off state. 2. A store instruction control method according to 1.   When a fetch instruction is issued from the instruction processing unit, a fetch bus for inputting data to be fetched by the fetch instruction from the predetermined storage area to the arithmetic unit or the arithmetic register, and the store data buffer The store stored in the store data buffer in the information processing apparatus further comprising a store fetch bypass for directly inputting the stored store data from the store data buffer to the fetch bus 10. The store instruction control according to claim 6, wherein when the data is used by the fetch instruction, the store data is input from the store data buffer to the store fetch bypass. Method.

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