KR100837730B1 - How to encode an LDPC code using the result of checking the parity specified in advance - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a Low Density Parity Check (LDPC) code encoding method.

2. The technical problem to be solved by the invention

According to the present invention, a parity bit is arbitrarily assigned in advance, and the parity bit is inversely determined using a double-parity parity check matrix. The object of the present invention is to provide a method of encoding an LDPC code using a result of checking a predetermined parity for deriving in parallel in matrix units.

3. Summary of Solution to Invention

The present invention provides a method of encoding a low density parity check code (hereinafter referred to as an "LDPC code") using an H matrix, comprising: constructing a parity partial matrix including a specific number of rows / columns on a subblock basis on the H matrix; ; Setting (specifying) the parity bit value in sub-block units with an arbitrary binary value for the configured parity partial matrix; Checking whether the parity partial matrix on the last subblock of the H matrix having a parity bit value is correct (true) according to an arbitrary binary value of the set subblock unit; Searching for an incorrect parity bit value based on the parity partial matrix check result; And parity bit of the H matrix by inverting the parity bit value set according to the arbitrary binary value in sub-block units with respect to the searched invalid parity bit value in sub-block units ["0-> 1", "1-> 0"]. Including determining by value.

4. Important uses of the invention

The present invention is used for LDPC code encoding.

Low Density Parity Check (LDPC) code encoding, H matrix, double diagonal, parity check matrix, submatrix units, parallelism, cyclic shift

Description

Method for reducing complexity encoder generating low density parity check codes}

1 is a diagram illustrating an embodiment of a concept of general LDPC code encoding.

2 is an explanatory diagram illustrating an H matrix used in the present invention.

2 is a diagram illustrating an embodiment for showing the H matrix proposed in the present invention.

FIG. 3 is a diagram for explaining an embodiment of converting an input word into a vector x according to the present invention; FIG.

FIG. 4 is a diagram illustrating an embodiment of an H matrix in which all of the parity bit portions on the H matrix shown in FIG. 2 are set to 0 according to the present invention; FIG.

FIG. 5 is a diagram for explaining an embodiment of a cyclic shift used in the present invention. FIG.

FIG. 6 is an explanatory diagram illustrating a case where a parity check result of an H matrix is calculated according to an embodiment of the present invention and the parity check result has failed. FIG.

7 is a diagram illustrating a case where a parity partial matrix of an H matrix is calculated according to the present invention, and a result of parity check is modified by an XOR operation to determine a final parity bit.

8 is a diagram illustrating an example of a result of calculating a parity partial matrix of an H matrix when a cyclic shift is performed on a first column of an H matrix according to the present invention;

9 is a flowchart illustrating a method of encoding an LDPC code using a result of checking a parity specified in advance according to the present invention.

The present invention relates to a Low Density Parity Check (LDPC) code encoding method. More particularly, the parity bit value can be arbitrarily assigned in advance, Conversely, the result of checking parity of the specified value using a double diagonal parity check matrix and using the result of checking a predetermined parity to derive the final parity bits in sub-matrix units in parallel using LDPC code It relates to a method of encoding.

The Low Density Parity Check (LDPC) code (hereinafter referred to as the "LDPC code") is not used as a hardware limitation despite its superior performance near the Shannon limit. Recently, active research has been conducted as a channel coding technique for reducing an error rate caused by high speed communication in next generation wired and wireless communication systems.

The LDPC code is assumed to be coded in a systematic manner. That is, a part of the packet goes out as an output in the same form as the input bit, and the rest of the packet goes out with the original information as side information as a parity bit (sign check bit).

Although all input signals must be input to the LDPC code encoder as described above, the encoding operation can be performed, and the ratio of parity bits in the entire packet is different according to the code rate. This code rate is fixed by an H matrix.

On the other hand, the conventional technique of the LDPC code encoding technique is "Efficient Encoding of Low Density Parity Check Codes" proposed by Richardson [IEEE Transactions on Information Theory, Vol. 47, No. 2, 2001] .

In the prior art, the H matrix is divided and divided into sub matrices, and then an output parity bit is generated when an input vector of the system of equations is given.

Recently, a simple LDPC code coding scheme has been proposed in IEEE 802.16e by Motorola Co., Ltd., compared to Richardson's LDPC code coding scheme. The parity bit is obtained by encoding the LDPC code.

However, Richardson's LDPC code coding method is not easy to process a signal at high speed due to the operation of dividing the sub-matrix, and the LDPC code coding method of Motorola has a high coding complexity and hardware resource load due to the direct parity bit. There is a growing problem.

Therefore, in encoding LDPC codes, a technique suitable for high-speed communication and capable of minimizing encoding complexity and resource requirements is urgently required.

The present invention has been proposed in order to solve the above problems and meet the above requirements, by arbitrarily designating a parity bit value in advance, and inverting the parity of the specified value inversely through a system of equations. The purpose of the present invention is to provide a method of encoding an LDPC code using a result of checking parity specified in advance to derive the final parity bit in sub-matrix units in parallel using the result obtained by using a parity check matrix having a diagonal structure. There is this.

A method of the present invention for achieving the above object is a method of encoding a low density parity check code (hereinafter referred to as "LDPC code") using an H matrix, the specific number of rows on the H matrix in units of subblocks. Constructing a parity submatrix of / columns; Setting (specifying) the parity bit value in sub-block units with an arbitrary binary value for the configured parity partial matrix; Checking whether the parity partial matrix on the last subblock of the H matrix having a parity bit value is correct (true) according to an arbitrary binary value of the set subblock unit; Searching for an incorrect parity bit value based on the parity partial matrix check result; And parity bit of the H matrix by inverting the parity bit value set according to the arbitrary binary value in sub-block units with respect to the searched invalid parity bit value in sub-block units ["0-> 1", "1-> 0"]. Determining by value.

Meanwhile, in the present invention, a low density parity check (LDPC) code encoder (hereinafter referred to as an "LDPC code encoder") has the same first parity bit parity check matrix. A computer readable recording medium having data corresponding to an H matrix having a double diagonal structure having a value of a click shift is provided.

On the other hand, the present invention relates to a low density parity check (LDPC) code encoder (hereinafter referred to as an "LDPC code encoder"), in which all parity bit check matrices therein are represented as an identity matrix ( A computer readable recording medium having recorded thereon data corresponding to an H matrix having an identity matrix structure is provided.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. There will be. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, the LDPC code coding scheme, which is suitable for high-speed communication and minimizes coding complexity and resource requirements, can be solved by designing a parity check matrix. While maintaining the same as each other, while presenting an H matrix having a structure in which the value of the cyclic shift of the parity check matrix therein is changed.

In addition, in the present invention, the general Richardson LDPC code encoding technique can be used as it is, and in particular, only as much as the size of an arbitrary sub-block as the solution of the parity bits in determining the parity bits in LDPC code encoding. Insert the parity check matrix into a dual diagonal structure, and consequently obtain the remaining solutions of the parity bits, and insert the first arbitrary solution in sub-block units by inserting the first arbitrary solution for the incorrectly obtained parity bit solution. We want to solve the correct parity bit.

1 is a diagram for explaining an example of general LDPC code encoding.

The basic idea of the LDPC code coding scheme is an "H matrix". A packet encoded through the H matrix in the encoder of the transmitter is decoded through the H matrix in the decoder of the receiver.

In Fig. 1, an LDPC code encoder having a code rate of “R = 3/4” is shown. As shown in Fig. 1, a 15-bit binary vector as an output signal is output as it is and 5 parity bits are based on the input vector. Is determined by the LDPC code encoder and comes together as an output signal. For example, it can be seen that the code rate "R = 3/4" as "input bit [15] / output bit [20] = 3/4".

Next, the structure of the H matrix proposed in the present invention will be described with reference to FIGS. 2 to 8.

2 is an explanatory diagram illustrating an H matrix used in the present invention, and the middle and bottom of FIG. 2 are explanatory diagrams illustrating an H matrix proposed in the present invention.

FIG. 3 is a diagram for explaining an embodiment of converting an input word into a vector x according to the present invention.

FIG. 4 is an exemplary explanatory diagram showing an H matrix in which all of the parity bit portions on the H matrix shown in FIG. 2 are set to 0 according to the present invention, and the H matrix has a code rate of “R = 1/2”. In addition, the subblock has a size of 38 × 38.

FIG. 5 is a diagram illustrating an embodiment of a cyclic shift used in the present invention. FIG. 5 is a cyclic shift 0 on the left side of FIG. 5 and a cyclic shift 2 on the right side of FIG. 5. Shown.

FIG. 2 shows an H matrix applied to an LDPC code encoder consisting of cyclic shifts of a projection matrix. The first matrix of the parity bit region on the general H matrix shown at the top of FIG. 2 is shown in the middle of FIG. And as shown below, the matrix H is presented in the present invention.

For example, the upper portion of FIG. 2 shows the structure of an H matrix having a code rate of “R = 5/6” as presented in the IEEE 802.11n standard, which is currently being standardized. The H matrix is an 81 × 81 subblock matrix. It consists of. Also, the numbers on the H matrix represent the values of the cyclic shifts.

On the other hand, Figure 4 shows an example of the cyclic shift in the matrix H of the size 38x38 subblock, each subblock has a structure of a circular matrix (circulant matrix).

On the other hand, if the subblock unit on the H matrix shown in FIG. 3 is 81x81, the size of the H matrix of FIG. 3 is 324x1944.

In particular, the H matrix shown in FIG. 3 has a structure of the H matrix proposed by Richardson, and the H matrix can be divided into an input bit portion and a parity bit portion as shown in FIG. 2. The characteristic of this H matrix is that the parity bit portion, that is, parity bit check matrix P has a double diagonal structure. Hereinafter, in describing the present invention, the parity bit check matrix P will be used in parallel with the term parity bit part or parity part matrix.

As described above, the structure of the H matrix proposed in the present invention, as shown in the middle of FIG. 2, makes all the parity bit portions zero cyclic shift, for example, an identity matrix, so that the bottom of FIG. As shown in FIG. 9, the parity bits are determined in parallel at the same time by the length of the diagonal portion of the subblock.

Next, prior to describing an algorithm for determining parity bits in parallel in units of subblocks as described above, a process of determining parity bits in bits will be described with reference to FIG. 4.

As shown in FIG. 4, it can be seen that in the H matrix having a code rate of “R = 1/2”, all parts indicated by “▨” in the parity bit portion are modified as 0 cyclic shifts. Here, the result of multiplying the H matrix by the code word vector c encoded by the H matrix must satisfy the following Equation 1.

In Equation 1, the c vector represents the output vector c of the LDPC code encoder shown in FIG.

Accordingly, the LDPC code encoder may determine parity bits drawn by wheat lines among the output vectors shown in FIG. 1, and 456 parity bits, ie, subs, satisfying “H · C ^T = 0” on the H matrix shown in FIG. 4. Since the number of blocks is 38, we need to find 456 [38 * 12 = 456] parity bits.

As mentioned above, the H matrix shown in FIG. 4 consists of a matrix of subblock units, and this subblock unit matrix is composed of cyclic shifts shown in FIG. 5.

A process of finding the 456 parity bits will now be described.

Define each of the 456 parity bits as "P ₀ , P ₁ , ..., P ₄₅₄ , P ₄₅₅ ".

Then, if parity bit P ₀ and parity bit P ₁ satisfy the above Equation 1, 1st row, 13th row, 59th row, 112th row, 184th row, 308 out of 456 rows The sum of the input bits corresponding to the first row and the parity bits corresponding to the 0th row and the 38th row should be 0. That is, it must be an even number because it is a modulo 2 operation. Here, the operation "H C ^T = 0" for the first row can be expressed by the following Equation 2.

는 비트 연산, 즉 modulo 2 연산을 나타내며, 이는 LDPC 코드 부호화 과정의 연산이 비트 단위의 연산임을 의미한다.In Equation 2,

Denotes a bit operation, that is, a modulo 2 operation, which means that the operation of the LDPC code encoding process is a bit unit operation.

In Equation 2, (H) _j indicates the j th row of the H matrix.

As can be seen from Equation 2, S ₀ , S ₅₉ , S ₁₁₂ , S ₁₈₄ and S ₃₀₈ are given as input signals, but parity bits P ₀ and P ₃₈ must be calculated.

Furthermore, there are 456 parity bits on the H matrix shown in FIG. 4, so that the 456 parity bits "P ₀ , P ₁ ,..., P ₄₅₄ , P ₄₅₅ " may be used to solve Equation 2 above. We have to get all the values for.

However, the solution for the 456 parity bits cannot be obtained by the system of equations.

Therefore, in the present invention, if you set the value of a specific parity bit prior to target that it can obtain the values of the other parity bits, as 0. The initial value of the parity bit P ₀ in advance set parity bits corresponding P ₃₈ value of Obtain For example, since the value of the parity bit P ₃₈ is known, the value of the parity bit P ₇₆ corresponding to the 38th row of the H matrix is obtained by the following equation (3).

As can be seen from [Equation 3], parity bit P ₇₆ is located on the 38th row. Thus, parity bit P ₁₁₄ located on the same 38th row without the value of parity bit P ₇₆ can be obtained. Will be. Here, parity bit P ₁₁₄ has a value in the 72th row.

Via the parity bit calculation process as above, 380 standing finding a value of the parity bit P of second line _418, the obtained value of the parity bit P ₄₁₈ is the value of the parity bit P ₄₁₈ in the 418-th row.

As above, when the sum of the input and parity bits corresponding to the 418th line is 0, the parity bits "P ₀ , P ₃₈ , P ₇₆ , P ₁₁₄ , P ₁₅₂ , P ₁₉₀ , P ₂₂₈ , P ₂₆₆ , The values of P ₃₀₄ and P ₄₁₈ "are all determined as correct values.

On the other hand, if the sum of the input bit and the parity bit corresponding to the 418th line does not become 0, the process returns to the first step, for example, to set the initial value of the parity bit P ₀ in advance, and then the initial value of the parity bit P ₀ . Set to 1 to perform the subsequent steps.

However, since the process of checking whether the parity bit value on the matrix is correct while changing the initial value of the parity bit P ₀ may be a bit more computational, the parity bits “P ₀ , P ₃₈ , and P ₇₆ as another example of the present invention. XOR operation of "P ₀ , P ₃₈ , P ₇₆ , P ₁₁₄ , P ₁₅₂ , P ₁₉₀ , P ₂₂₈ " among _,, P ₁₁₄ , P ₁₅₂ , P ₁₉₀ , P ₂₂₈ , P ₂₆₆ , P ₃₀₄ , and P ₄₁₈ " It is desirable to determine the final parity bit.

In detail, "P ₂₆₆ , P ₃₀₄ , and P ₄₁₈ " of the parity bits are excluded from the XOR operation because the values of "P ₂₆₆ , P ₃₀₄ and P ₄₁₈ " do not change. That is, three parity bits should be determined in the 228th row. When the first and second odd parity bits are determined, the third parity bit always has a constant value.

As described above, the process of determining parity bits in units of bits according to the present invention has been described. Hereinafter, a process of determining parity bits in parallel in units of subblocks in the present invention will be described with reference to FIGS. 6 and 7. It will be described later in detail.

FIG. 6 is an exemplary explanatory diagram illustrating a case where a parity check matrix of an H matrix is a result of failing a parity check result according to the present invention, and FIG. 7 is a parity part of an H matrix according to the present invention. As a result of calculating the matrix, the parity check result is modified by an XOR operation to explain a case where the final parity bit is determined. Here, the H matrix is composed of 4 × 4 subblocks.

For the process of determining the parity bits in the bit unit described above with reference to FIG. 4, in the present invention, the parity bits may be determined in parallel at the same time in the subblock unit.

That is, when parity bits "P ₀ and P ₃₇ " are determined, parity bits "P ₀ " to "P ₃₇ " are immediately determined through the sub-block unit parallel processing of the present invention.

As shown in FIGS. 6 and 7, the information bit portion of the H matrix corresponds to the vector x as shown in FIG. 3. Such a vector x is represented by a modulo 2 operation. For the vector x, the 0th row portion on the H matrix shown in FIG. 4 is expressed by Equation 4 below.

In Equation 4, j represents j rows of the vector x.

Then, in order to apply the H matrix shown in FIG. 4 to the LDPC code encoder, the value of the vector x corresponding to 456 parity bits is generated using Equation 4 as described above.

In the state where all vectors x are generated using Equation 4, assuming that the size of the subblock matrix on the H matrix is 4 × 4, the LPCP code encoding process is shown in FIG. 6.

Referring to FIG. 6, the columns of the first subblock of the parity bit portion indicated by "▨" are all initialized as zero. This means that the parity bits "P ₀ , P ₁ , P ₂ , P ₃ " are all set as zero.

As described above with reference to FIG. 4, the parity bits "P ₄ , P ₅ , P ₆ , and P ₇ " may be obtained as "0, 1, 0, 1" by Equation 1, and then parity The bits "P ₈ , P ₉ , P ₁₀ , P ₁₁ " and "P ₁₂ , P ₁₃ , P ₁₄ and P ₁₅ " can be obtained in this order.

Then, the parity check result (ie, Equation 1) for the parity bits finally obtained from the 12th to 15th rows may be represented as a subblock denoted by "▥" in FIG. 6 [sub-block check result].

If a non-zero portion, eg, 1, is present among the subblocks indicated by " ▥ " shown in Fig. 6, then the parity check result means failure, that is, failure to generate a desired LDPC code (does not satisfy Equation 1). In FIG. 6, it can be seen that the parity bit of the 12th row is wrong.

In this case, since the parity check result in FIG. 6 has failed, it should be corrected to determine the final parity bit. This process is shown in FIG.

That is, as a result of the parity check of FIG. 6, for example, a subblock denoted by "▥" in FIG. 6, a subblock denoted by "▨" in FIG. 6, and a subblock denoted by "▧" in FIG. 6. XOR the block.

As a result of the XOR operation, the result as shown in FIG. 7 may be obtained. In particular, when parity bit checks are performed from the 12th row to the 15th row, a subblock indicated by "

That is, FIG. 7 shows finally obtained parity bits "P ₀ " to "P ₁₅ " satisfying Equation 1 above.

Note that in determining the final parity bit as described above, the parity bit portion indicated by "▤" in FIG. 7 is excluded from the XOR operation.

For example, the H matrix illustrated in FIG. 6 may be confirmed by a process of modifying the H matrix illustrated in FIG. 7. The sub-block of the parity portion indicated by "▥" in FIG. 6 and the parity indicated by "▧" in FIG. 6. Even if the subblock of the portion and the subblock of the parity portion indicated by "에" in FIG. 7 and the subblock of the parity portion indicated by "에" in FIG. 7 are respectively changed, the subblock of the parity bit portion indicated by "부분" It means that the value of the block does not change. This is the same in the process of determining parity bits in parallel in units of subblocks, similarly to the reason why three parity bits are determined in the process of determining parity bits in bits as described above with reference to FIG. 4.

On the other hand, the parity bit determination process proposed in the present invention, in addition to the feature of determining the parity bit in parallel in units of sub-blocks, as another feature, all the columns corresponding to the parity portion indicated by "▥" in Figure 7 is the same cyclic The shift may have no effect, for example, on LDPC code encoding. This will be described with reference to FIG. 8.

FIG. 8 is an exemplary explanatory diagram illustrating a result of calculating a parity partial matrix of the H matrix when the first column on the H matrix is cyclic shifted according to the present invention. FIG. It shows a case where

As shown in Fig. 8, the columns corresponding to the parity portion indicated by "▥" all have the same cyclic shift. Although such cyclic shift has some influence on the LDPC code encoding performance, it is described above. The LDPC code encoding process according to the present invention has the same result.

In the following LDPC code encoding process, the flow of the above-described parity bit determination process of the present invention will be summarized with reference to FIG.

9 is a flowchart illustrating a parity bit determination process in particular among methods of encoding an LDPC code using a result of checking a parity specified in advance according to the present invention.

A process of LDPC code encoding an information sequence of length K with a code of length N will be described as an example.

First, the parity check matrix portion of the H matrix in constructing a parity bit check matrix having a dual diagonal structure composed of (NK) rows and (NK) columns of check nodes based on the H matrix. The first column of the parity part of H matrix performs the same number of cyclic shifts (901). As another example, in configuring the present parity bit check matrix, the parity bit check matrix may be configured as an identity matrix.

Then, in a state where a parity bit check matrix is configured on the H matrix, a binary value is inserted in sub-block units to calculate a value of a corresponding parity bit on the configured parity bit check matrix. (902). This process assigns an arbitrary binary value as the parity bit value of the parity bit check matrix on the first subblock on the H matrix, and sequentially calculates all parity bit values of the parity bit check matrix on the other subblocks on the H matrix. Will be.

Then, check the value of the calculated parity bit (903), if the value of the parity bit is not correct, check the parity bit corresponding to the last subblock on the H matrix (904), check this parity bit The parity bit portion whose result is " 1 " is searched (905). Referring to FIG. 6, the last subblock on the H matrix indicates a 4 × 4 subblock located in rows 12 to 15, and the first subblock on the H matrix corresponds to a row 0 to 3. Point to the 4x4 subblock located.

Then, the searched parity bit portion is first performed by performing an XOR operation on the parity bit portion in which a binary value is first arbitrarily inserted and the parity bit portion obtained through a system of parity bits in units of subblocks (906). The value of the parity bit satisfying H C ^T = 0 "(Equation 1) is determined as the value of the H matrix (907).

In addition, in the present invention described above, although the initial value of the parity bit P _{0 (that} is, the initial value of the subblock) is set as 0, even if any combination of random numbers of binary numbers is used as the initial value, The parity bit check of the block may be performed by performing an XOR operation on the subblock except for the parity bit portion indicated by “▤” in FIGS. 6 and 7 to determine the final parity bit that satisfies [Equation 1].

Further, even if the parity bit initial value is limited to the subblock of the first column, the parity bit determination process may be performed by selecting from the subblocks of the remaining columns except for the parity bit portion indicated by "▤" in FIG. It's okay.

As described above, the method of the present invention may be implemented as a program and stored in a recording medium (CD-ROM, RAM, ROM, floppy disk, hard disk, magneto-optical disk, etc.) in a computer-readable form. Since this process can be easily implemented by those skilled in the art will not be described in more detail.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by the drawings.

As described above, the present invention is suitable for high speed communication in LDPC code encoding, and has an effect of minimizing encoding complexity and resource requirements.

In addition, while the structure of the parity check matrix is maintained in the same manner as the conventional LDPC code encoding method, the LDPC code can be efficiently encoded by only slightly changing the structure of the H matrix.

In addition, the present invention has an effect that can accurately solve the parity bit on the H matrix.

In addition, the present invention has the effect of changing the structure of the LDPC code decoder corresponding to the H matrix in the aspect of the device to perform the LDPC code coding operation.

Claims (10)

In the method of encoding a low density parity check code (hereinafter referred to as "LDPC code") using an H matrix, Constructing a parity submatrix of a specific number of rows / columns on the H matrix in units of subblocks; Setting (specifying) the parity bit value in sub-block units with an arbitrary binary value for the configured parity partial matrix; Checking whether the parity partial matrix on the last subblock of the H matrix having a parity bit value is correct (true) according to an arbitrary binary value of the set subblock unit; Searching for an incorrect parity bit value based on the parity partial matrix check result; And The parity bit value of the H matrix is inverted ["0-> 1", "1-> 0"] by inverting the parity bit value set according to the arbitrary binary value with respect to the searched invalid parity bit value. Step to decide And encoding an LDPC code using a result of checking a parity specified in advance. The method of claim 1, Configuring the parity partial matrix, And performing the same number of cyclic shifts on the first column of the parity sub-matrix to form the parity sub-matrix. The method of claim 1, Configuring the parity partial matrix, And encoding the parity partial matrix as a unit matrix using the result of checking a parity specified in advance. The method of claim 1, The setting of the parity bit value in sub-block units with an arbitrary binary value for the configured parity partial matrix may include: A parity bit value of a parity sub-matrix on another subblock on the H matrix is calculated by designating the arbitrary binary value as the parity bit value of the parity sub-matrix on the first subblock on the H matrix A method of encoding an LDPC code using parity check results. The method according to any one of claims 1 to 4, Determining the parity bit value of the H matrix, Performing an XOR operation on a parity bit value obtained through a system of parity bit values and parity bits of a parity sub-matrix on the first subblock of the H matrix with respect to the searched incorrect parity bit value in units of subblocks; And Determining a parity bit value in which a value obtained by multiplying the H matrix and a codeword vector encoded by the H matrix from the result of performing the XOR operation as a corresponding parity bit value of the H matrix And encoding an LDPC code using a result of checking a parity specified in advance. The method of claim 5, wherein And said random binary value is a combination value of "0" or a random binary number. The method of claim 5, wherein The random binary value is a combination of random binary numbers, The process of performing the XOR operation, The LDPC code is encoded using a result of checking a parity specified in advance, wherein a parity bit value whose value does not change regardless of the LDPC encoding among the parity partial matrices on the sub-block on the H matrix is excluded from the XOR operation. How to. delete delete delete

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